 Rodrigo Vivi
|
2c2f6e30d5
drm/i915/glk: Remove 99% limitation.
|
6 years ago |
 Gustavo A. R. Silva
|
f0d759f038
drm/i915: Mark expected switch fall-throughs
|
7 years ago |
 Paulo Zanoni
|
9378985eb0
drm/i915/icl: implement DVFS for ICL
|
7 years ago |
 Imre Deak
|
602a9de513
drm/i915/skl: Add warn about unsupported CDCLK rates
|
7 years ago |
|
Rodrigo Vivi
|
3297234a05
drm/i915: Adjust eDP's logical vco in a reliable place.
|
7 years ago |
 Abhay Kumar
|
904e1b1ff4
drm/i915/audio: set minimum CD clock to twice the BCLK
|
7 years ago |
 Linus Torvalds
|
672a9c1069
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial
|
7 years ago |
 Masanari Iida
|
bc8282a730
treewide: Fix typos in printk
|
7 years ago |
 Hans de Goede
|
405cacc947
drm/i915/vlv: Add cdclk workaround for DSI
|
7 years ago |
|
Paulo Zanoni
|
186a277e31
drm/i915/icl: add the main CDCLK functions
|
7 years ago |
 Tvrtko Ursulin
|
c56b89f16d
drm/i915: Use INTEL_GEN everywhere
|
7 years ago |
|
Imre Deak
|
5e1df40f40
drm/i915/bxt, glk: Increase PCODE timeouts during CDCLK freq changing
|
7 years ago |
|
Imre Deak
|
006bb4ccac
drm/i915/bxt, glk: Avoid long atomic poll during CDCLK change
|
7 years ago |
|
Imre Deak
|
e76019a819
drm/i915/bxt, glk: Increase PCODE timeouts during CDCLK freq changing
|
7 years ago |
 Anusha Srivatsa
|
4ef99abd07
drm/i915/icp: Get/set proper Raw clock frequency on ICP
|
7 years ago |
|
Imre Deak
|
b6c51c3e28
drm/i915: Add tracking for CDCLK bypass frequency
|
7 years ago |
 Dave Airlie
|
4a6cc7a44e
BackMerge tag 'v4.15-rc8' into drm-next
|
7 years ago |
 Lucas De Marchi
|
30414f3010
drm/i915: Apply Display WA #1183 on skl, kbl, and cfl
|
7 years ago |
|
Hans de Goede
|
c8dae55a8c
drm/i915/vlv: Add cdclk workaround for DSI
|
7 years ago |
|
Lucas De Marchi
|
53421c2fe9
drm/i915: Apply Display WA #1183 on skl, kbl, and cfl
|
7 years ago |
 Maarten Lankhorst
|
24f2845056
drm/i915: Make ips_enabled a property depending on whether IPS is enabled, v3.
|
7 years ago |
|
Rodrigo Vivi
|
43037c86d1
drm/i915/cnl: Allow 2 pixel per clock on Cannonlake.
|
7 years ago |
 Ville Syrjälä
|
cfddadc98a
drm/i915: Perform a central cdclk state sanity check
|
7 years ago |
|
Ville Syrjälä
|
0c9f353f01
drm/i915: Sanity check cdclk in vlv_set_cdclk()
|
7 years ago |
|
Ville Syrjälä
|
53e9bf5e81
drm/i915: Adjust system agent voltage on CNL if required by DDI ports
|
7 years ago |
|
Ville Syrjälä
|
48469eced2
drm/i915: Use cdclk_state->voltage on CNL
|
7 years ago |
|
Ville Syrjälä
|
2123f442ca
drm/i915: Use cdclk_state->voltage on BXT/GLK
|
7 years ago |
|
Ville Syrjälä
|
2aa97491da
drm/i915: Use cdclk_state->voltage on SKL/KBL/CFL
|
7 years ago |
|
Ville Syrjälä
|
d7ffaeef96
drm/i915: Use cdclk_state->voltage on BDW
|
7 years ago |
|
Ville Syrjälä
|
999c5766f3
drm/i915: Use cdclk_state->voltage on VLV/CHV
|
7 years ago |
