 James Hogan
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c04de7b1ad
MIPS: CM: Drop WARN_ON(vp != 0)
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%!s(int64=7) %!d(string=hai) anos |
 Paul Burton
|
fb615d61b5
Update MIPS email addresses
|
%!s(int64=8) %!d(string=hai) anos |
 Paul Burton
|
e83f7e02af
MIPS: CPS: Have asm/mips-cps.h include CM & CPC headers
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%!s(int64=8) %!d(string=hai) anos |
|
Paul Burton
|
68923cdc2e
MIPS: CM: Add cluster & block args to mips_cm_lock_other()
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%!s(int64=8) %!d(string=hai) anos |
|
Paul Burton
|
f875a832d2
MIPS: Abstract CPU core & VP(E) ID access through accessor functions
|
%!s(int64=8) %!d(string=hai) anos |
|
Paul Burton
|
846e1913f5
MIPS: CPS: Use change_*, set_* & clear_* where appropriate
|
%!s(int64=8) %!d(string=hai) anos |
|
Paul Burton
|
93c5bba575
MIPS: CM: Use BIT/GENMASK for register fields, order & drop shifts
|
%!s(int64=8) %!d(string=hai) anos |
|
Paul Burton
|
b025d51873
MIPS: CM: Specify register size when generating accessors
|
%!s(int64=8) %!d(string=hai) anos |
|
Paul Burton
|
abe852ea3a
MIPS: CM: Rename mips_cm_base to mips_gcr_base
|
%!s(int64=8) %!d(string=hai) anos |
|
Paul Burton
|
2f93a60c3d
MIPS: CM: WARN on attempt to lock invalid VP, not BUG
|
%!s(int64=8) %!d(string=hai) anos |
|
Paul Burton
|
516db1c61f
MIPS: CM: Avoid per-core locking with CM3 & higher
|
%!s(int64=8) %!d(string=hai) anos |
 Masahiro Yamada
|
97f2645f35
tree-wide: replace config_enabled() with IS_ENABLED()
|
%!s(int64=9) %!d(string=hai) anos |
 Adam Buchbinder
|
92a76f6d85
MIPS: Fix misspellings in comments.
|
%!s(int64=9) %!d(string=hai) anos |
|
Paul Burton
|
78a54c4d8e
MIPS: CM, CPC: Ensure core-other GCRs reflect the correct core
|
%!s(int64=10) %!d(string=hai) anos |
|
Paul Burton
|
23d5de8efb
MIPS: CM: Introduce core-other locking functions
|
%!s(int64=10) %!d(string=hai) anos |
|
Paul Burton
|
47b26a467d
MIPS: Always read full 64 bit CM error GCRs for CM3
|
%!s(int64=10) %!d(string=hai) anos |
|
Paul Burton
|
f88e632480
MIPS: Avoid buffer overrun in mips_cm_error_report
|
%!s(int64=10) %!d(string=hai) anos |
|
Paul Burton
|
03b1b85d3d
MIPS: Don't read GCRs when a CM is not present
|
%!s(int64=10) %!d(string=hai) anos |
 Markos Chandras
|
3885c2b463
MIPS: CM: Add support for reporting CM cache errors
|
%!s(int64=10) %!d(string=hai) anos |
|
Markos Chandras
|
038b0f536e
MIPS: CM: The CMGCRBase register is 64-bit on 64 bit kernels.
|
%!s(int64=10) %!d(string=hai) anos |
|
Markos Chandras
|
c0b584a269
MIPS: mips-cm: Extend CM accessors for 64-bit CPUs
|
%!s(int64=10) %!d(string=hai) anos |
|
Markos Chandras
|
c014d164f2
MIPS: Add platform callback before initializing the L2 cache
|
%!s(int64=10) %!d(string=hai) anos |
 Ralf Baechle
|
15d45cce3a
MIPS: Replace use of phys_t with phys_addr_t.
|
%!s(int64=11) %!d(string=hai) anos |
|
Paul Burton
|
9f98f3dd0c
MIPS: Add generic CM probe & access code
|
%!s(int64=11) %!d(string=hai) anos |
