 Thierry Reding
|
666cb87332
drm/tegra: dc: Unify enabling the display controller
|
10 年之前 |
|
Thierry Reding
|
3f0fb52ef0
drm/tegra: Remove unused ->mode_fixup() callbacks
|
10 年之前 |
|
Thierry Reding
|
ebd14afe8f
drm/tegra: dsi: Implement ->atomic_check()
|
10 年之前 |
|
Thierry Reding
|
9d44189f55
drm/tegra: Atomic conversion, phase 2
|
10 年之前 |
|
Thierry Reding
|
4aa3df7149
drm/tegra: Atomic conversion, phase 1
|
10 年之前 |
|
Thierry Reding
|
328ec69e7f
drm/tegra: Output cleanup functions cannot fail
|
10 年之前 |
|
Thierry Reding
|
ea130b240d
drm/tegra: Remove remnants of the output midlayer
|
10 年之前 |
|
Thierry Reding
|
4009c22420
drm/tegra: debugfs cleanup cannot fail
|
10 年之前 |
|
Thierry Reding
|
5b901e78b2
drm/tegra: dsi: Demidlayer
|
10 年之前 |
|
Thierry Reding
|
36904adf21
drm/tegra: Stop CRTC at CRTC disable time
|
10 年之前 |
|
Thierry Reding
|
62b9e06321
drm/tegra: Use tegra_commit_dc() in output drivers
|
10 年之前 |
|
Thierry Reding
|
201106d83e
drm/tegra: dsi: Reset across ->exit()/->init()
|
10 年之前 |
|
Thierry Reding
|
92f0e073ed
drm/tegra: dsi: Soft-reset controller on ->disable
|
10 年之前 |
|
Thierry Reding
|
9c0b4ca112
drm/tegra: dsi: Registers are 32-bit
|
10 年之前 |
 Sean Paul
|
7e3bc3a98f
drm/tegra: dsi: Set up PHY_TIMING & BTA_TIMING registers earlier
|
11 年之前 |
|
Thierry Reding
|
030611ecc5
drm/tegra: dsi: Replace 1000000 by USEC_PER_SEC
|
10 年之前 |
|
Thierry Reding
|
369bc65b6b
drm/tegra: dsi: Replace 1000000000UL by NSEC_PER_SEC
|
10 年之前 |
|
Thierry Reding
|
0fffdf6ca9
drm/tegra: dsi: Implement host transfers
|
10 年之前 |
|
Thierry Reding
|
e94236cde4
drm/tegra: dsi: Add ganged mode support
|
11 年之前 |
|
Thierry Reding
|
3f6b406f7d
drm/tegra: dsi: Split out tegra_dsi_set_timeout()
|
10 年之前 |
|
Thierry Reding
|
337b443d58
drm/tegra: dsi: Add command mode support
|
10 年之前 |
|
Thierry Reding
|
563eff1f98
drm/tegra: dsi: Refactor in preparation for command mode
|
10 年之前 |
|
Thierry Reding
|
d2d0a9d212
drm/tegra: dsi: Properly cleanup on probe failure
|
10 年之前 |
|
Thierry Reding
|
ba3df97922
drm/tegra: dsi: Mark connector hotpluggable
|
10 年之前 |
|
Thierry Reding
|
41a8e72e0e
drm/tegra: dsi: Leave parent clock alone
|
10 年之前 |
|
Thierry Reding
|
183ef2883d
drm/tegra: dsi: Do not manage clock on enable/disable
|
10 年之前 |
|
Thierry Reding
|
976cebc35b
drm/tegra: dsi: Make FIFO depths host parameters
|
11 年之前 |
 Stephen Warren
|
ef70728c7a
drm/tegra: add MODULE_DEVICE_TABLEs
|
11 年之前 |
 Alexandre Courbot
|
0c6b1e4ba7
drm/tegra: dsi - Handle non-continuous clock flag
|
11 年之前 |
|
Thierry Reding
|
9910f5c455
drm/tegra: Remove host1x drm_bus implementation
|
11 年之前 |
