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@@ -820,7 +820,7 @@ static int tegra_output_dsi_setup_clock(struct tegra_output *output,
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/*
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* Compute bit clock and round up to the next MHz.
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*/
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- plld = DIV_ROUND_UP(bclk * 8, 1000000) * 1000000;
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+ plld = DIV_ROUND_UP(bclk * 8, USEC_PER_SEC) * USEC_PER_SEC;
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/*
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* We divide the frequency by two here, but we make up for that by
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