 Bob Paauwe
|
adda50b8b3
drm/i915/skl: Don't clear all watermarks when updating. (v2)
|
10 years ago |
 Arun Siluvery
|
5b88abacd4
drm/i915/bxt: Add WaSetClckGatingDisableMedia
|
10 years ago |
 Nick Hoath
|
a754615971
drm/i915/bxt: Clean up bxt_init_clock_gating
|
10 years ago |
 Jani Nikula
|
742f491d2c
drm/i915: use the yesno helper for logging
|
10 years ago |
 Kumar, Mahesh
|
395ab7541a
drm/i915/skl: Avoid using un-initialized bits_per_pixel
|
10 years ago |
 Ville Syrjälä
|
c2699524d6
drm/i915: Add HAS_PCH_LPT_LP() macro
|
10 years ago |
 Daniel Vetter
|
06059d5090
Merge tag 'topic/drm-misc-2015-07-28' into drm-intel-next-queued
|
10 years ago |
|
Arun Siluvery
|
245d96670d
drm/i915:skl: Add WaEnableGapsTsvCreditFix
|
10 years ago |
|
Daniel Vetter
|
4ea50e99bd
drm: Simplify drm_for_each_legacy_plane arguments
|
10 years ago |
|
Daniel Vetter
|
dd92d8de83
Partially revert "drm/i915: s/mdelay/msleep/" in ilk rps code
|
10 years ago |
 Mika Kuoppala
|
661abfc028
drm/i915: Fix divide by zero on watermark update
|
10 years ago |
|
Arun Siluvery
|
a4106a782d
drm/i915/gen9: Add WaFlushCoherentL3CacheLinesAtContextSwitch workaround
|
10 years ago |
|
Nick Hoath
|
6381b55016
drm/i915/gen9: Implement WaDisableKillLogic for gen 9
|
10 years ago |
 Akash Goel
|
97d3308ab2
drm/i915: Add HAS_CORE_RING_FREQ macro
|
10 years ago |
|
Akash Goel
|
cc017fb4d7
drm/i915/skl: Restrict the ring frequency table programming to SKL
|
10 years ago |
 Deepak S
|
cd25dd5b76
drm/i915: Update PM interrupts before updating the freq
|
10 years ago |
|
Akash Goel
|
4c8c7743b5
drm/i915/skl: Ring frequency table programming changes
|
10 years ago |
|
Akash Goel
|
c5e0688cc7
drm/i915/skl: Retrieve the Rpe value from Pcode
|
10 years ago |
 Paulo Zanoni
|
7733b49bb0
drm/i915: use dev_priv for the FBC functions
|
10 years ago |
|
Daniel Vetter
|
6adfb1ef10
drm/i915: s/mdelay/msleep/
|
10 years ago |
|
Ville Syrjälä
|
2cb389b7e4
drm/i915: Zero unused WM1 watermarks on VLV/CHV
|
10 years ago |
|
Ville Syrjälä
|
6f9c784b7e
drm/i915: Don't do PM5/DDR DVFS with multiple pipes
|
10 years ago |
|
Ville Syrjälä
|
852eb00dc4
drm/i915: Try to make sure cxsr is disabled around plane enable/disable
|
10 years ago |
|
Ville Syrjälä
|
26e1fe4fbd
drm/i915: Use the memory latency based WM computation on VLV too
|
10 years ago |
|
Ville Syrjälä
|
54f1b6e15d
drm/i915: Compute display FIFO split dynamically for CHV
|
10 years ago |
|
Ville Syrjälä
|
262cd2e154
drm/i915: CHV DDR DVFS support and another watermark rewrite
|
10 years ago |
|
Ville Syrjälä
|
6eb1a68172
drm/i915: Read wm values from hardware at init on CHV
|
10 years ago |
|
Ville Syrjälä
|
a7a6c49892
drm/i915: POSTING_READ() in intel_set_memory_cxsr()
|
10 years ago |
|
Bob Paauwe
|
350405623f
drm/i915: Update rps frequencies for BXT
|
10 years ago |
|
Daniel Vetter
|
e7d66d89bc
drm/i915: Remove more ilk rc6 remnants
|
10 years ago |
