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@@ -1097,6 +1097,15 @@ static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *ring,
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{
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uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES);
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+ /*
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+ * WaDisableLSQCROPERFforOCL:skl
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+ * This WA is implemented in skl_init_clock_gating() but since
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+ * this batch updates GEN8_L3SQCREG4 with default value we need to
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+ * set this bit here to retain the WA during flush.
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+ */
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+ if (IS_SKYLAKE(ring->dev) && INTEL_REVID(ring->dev) <= SKL_REVID_E0)
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+ l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;
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+
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wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8(1) |
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MI_SRM_LRM_GLOBAL_GTT));
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wa_ctx_emit(batch, index, GEN8_L3SQCREG4);
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@@ -1253,6 +1262,7 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring,
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uint32_t *const batch,
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uint32_t *offset)
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{
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+ int ret;
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struct drm_device *dev = ring->dev;
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uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
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@@ -1261,6 +1271,12 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring,
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(IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0)))
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wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
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+ /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
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+ ret = gen8_emit_flush_coherentl3_wa(ring, batch, index);
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+ if (ret < 0)
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+ return ret;
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+ index = ret;
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+
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/* Pad to end of cacheline */
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while (index % CACHELINE_DWORDS)
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wa_ctx_emit(batch, index, MI_NOOP);
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