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@@ -5021,6 +5021,7 @@ static void __gen6_update_ring_freq(struct drm_device *dev)
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int min_freq = 15;
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unsigned int gpu_freq;
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unsigned int max_ia_freq, min_ring_freq;
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+ unsigned int max_gpu_freq, min_gpu_freq;
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int scaling_factor = 180;
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struct cpufreq_policy *policy;
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@@ -5045,17 +5046,31 @@ static void __gen6_update_ring_freq(struct drm_device *dev)
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/* convert DDR frequency from units of 266.6MHz to bandwidth */
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min_ring_freq = mult_frac(min_ring_freq, 8, 3);
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+ if (IS_SKYLAKE(dev)) {
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+ /* Convert GT frequency to 50 HZ units */
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+ min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
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+ max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
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+ } else {
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+ min_gpu_freq = dev_priv->rps.min_freq;
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+ max_gpu_freq = dev_priv->rps.max_freq;
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+ }
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+
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/*
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* For each potential GPU frequency, load a ring frequency we'd like
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* to use for memory access. We do this by specifying the IA frequency
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* the PCU should use as a reference to determine the ring frequency.
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*/
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- for (gpu_freq = dev_priv->rps.max_freq; gpu_freq >= dev_priv->rps.min_freq;
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- gpu_freq--) {
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- int diff = dev_priv->rps.max_freq - gpu_freq;
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+ for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
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+ int diff = max_gpu_freq - gpu_freq;
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unsigned int ia_freq = 0, ring_freq = 0;
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- if (INTEL_INFO(dev)->gen >= 8) {
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+ if (IS_SKYLAKE(dev)) {
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+ /*
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+ * ring_freq = 2 * GT. ring_freq is in 100MHz units
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+ * No floor required for ring frequency on SKL.
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+ */
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+ ring_freq = gpu_freq;
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+ } else if (INTEL_INFO(dev)->gen >= 8) {
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/* max(2 * GT, DDR). NB: GT is 50MHz units */
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ring_freq = max(min_ring_freq, gpu_freq);
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} else if (IS_HASWELL(dev)) {
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