Merge branch 'connectivity-ti-linux-4.19.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel into ti-linux-4.19.y

TI-Feature: connectivity
TI-Tree: git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel.git
TI-Branch: connectivity-ti-linux-4.19.y

* 'connectivity-ti-linux-4.19.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel:
  PCI: dra7xx: Clear PCIe wrapper's MSI INT status before dwc's MSI INT STATUS
  ARM: dts: am57xx-beagle-x15-revb1: Fix ddr pinmux names for mmc2
  ARM: dts: am57xx-beagle-x15-revc: Fix ddr pinmux names for mmc2
  arm64: dts: ti: k3-am65-mcu: add cpsw-phy-sel node
  arm64: dts: ti: k3-am65-mcu: add scm node
  arm64: dts: k3-am6: Add "dma-coherent" property to PCIe DT nodes

Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>

arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts

@@ -32,7 +32,7 @@
 };
 
 &mmc2 {
-	pinctrl-names = "default", "hs", "ddr_1_8v";
+	pinctrl-names = "default", "hs", "ddr_3_3v";
 	pinctrl-0 = <&mmc2_pins_default>;
 	pinctrl-1 = <&mmc2_pins_hs>;
 	pinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 &mmc2_iodelay_ddr_3_3v_rev11_conf>;

arch/arm/boot/dts/am57xx-beagle-x15-revc.dts

@@ -32,7 +32,7 @@
 };
 
 &mmc2 {
-	pinctrl-names = "default", "hs", "ddr_1_8v";
+	pinctrl-names = "default", "hs", "ddr_3_3v";
 	pinctrl-0 = <&mmc2_pins_default>;
 	pinctrl-1 = <&mmc2_pins_hs>;
 	pinctrl-2 = <&mmc2_pins_ddr_rev20>;

arch/arm64/boot/dts/ti/k3-am65-main.dtsi

@@ -1288,6 +1288,7 @@
 		num-ob-windows = <16>;
 		num-viewport = <16>;
 		max-link-speed = <3>;
+		dma-coherent;
 		interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
 		#interrupt-cells = <1>;
 		interrupt-map-mask = <0 0 0 7>;
@@ -1316,6 +1317,7 @@
 		num-ib-windows = <16>;
 		num-ob-windows = <16>;
 		max-link-speed = <3>;
+		dma-coherent;
 		interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
 		status = "disabled";
 	};
@@ -1338,6 +1340,7 @@
 		num-ob-windows = <16>;
 		num-viewport = <16>;
 		max-link-speed = <3>;
+		dma-coherent;
 		interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
 		#interrupt-cells = <1>;
 		interrupt-map-mask = <0 0 0 7>;
@@ -1365,6 +1368,7 @@
 		num-ib-windows = <16>;
 		num-ob-windows = <16>;
 		max-link-speed = <3>;
+		dma-coherent;
 		interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
 		status = "disabled";
 	};

arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi

@@ -7,8 +7,17 @@
 
 &cbass_mcu {
 	mcu_conf: scm_conf@40f00000 {
-		compatible = "syscon";
-		reg = <0 0x40f00000 0 0x20000>;
+		compatible = "syscon", "simple-mfd";
+		reg = <0x0 0x40f00000 0x0 0x20000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0x40f00000 0x20000>;
+
+		phy_sel: cpsw-phy-sel@4040 {
+			compatible = "ti,am654-cpsw-phy-sel";
+			reg = <0x4040 0x4>;
+			reg-names = "gmii-sel";
+		};
 	};
 
 	mcu_uart0: serial@40a00000 {
@@ -134,6 +143,7 @@
 		clock-names = "fck";
 		power-domains = <&k3_pds 5>;
 		ti,psil-base = <0x7000>;
+		cpsw-phy-sel = <&phy_sel>;
 
 		interrupt-parent = <&main_udmass_inta>;
 

arch/arm64/boot/dts/ti/k3-am65.dtsi

@@ -77,6 +77,7 @@
 			 /* MCUSS Range */
 			 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
 			 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
+			 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
 			 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
 			 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
 			 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>,
@@ -95,6 +96,7 @@
 			#size-cells = <2>;
 			ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
 				 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
+				 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
 				 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
 				 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
 				 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, /* MCU SRAM */

drivers/pci/controller/dwc/pci-dra7xx.c

@@ -265,6 +265,7 @@ static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
 	int count = 0;
 
 	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);
+	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg);
 
 	switch (reg) {
 	case MSI:
@@ -297,8 +298,6 @@ static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
 		break;
 	}
 
-	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg);
-
 	return IRQ_HANDLED;
 }