TEMP: arm64: dts: ti: k3-am65-main: Add IEP and CORE clock muxes

The ICSSG module has clock muxes for IEP clock and CORE clock.
Add these clock muxes. The default parents for these mux clocks
are also assigned.

Signed-off-by: Roger Quadros <rogerq@ti.com>
[s-anna@ti.com: minor formatting changes]
Signed-off-by: Suman Anna <s-anna@ti.com>

arch/arm64/boot/dts/ti/k3-am65-main.dtsi

@@ -499,6 +499,22 @@
 				reg = <0xb026000 0x200>;
 			};
 
+			icssg0_coreclk_mux: coreclk_mux {
+				#clock-cells = <0>;
+				clocks = <&k3_clks 62 19>, /* icssg0_core_clk */
+					 <&k3_clks 62 3>;  /* icssg0_iclk */
+				assigned-clocks = <&icssg0_coreclk_mux>;
+				assigned-clock-parents = <&k3_clks 62 3>;
+			};
+
+			icssg0_iepclk_mux: iepclk_mux {
+				#clock-cells = <0>;
+				clocks = <&k3_clks 62 10>,	/* icssg0_iep_clk */
+					 <&icssg0_coreclk_mux>;	/* core_clk */
+				assigned-clocks = <&icssg0_iepclk_mux>;
+				assigned-clock-parents = <&icssg0_coreclk_mux>;
+			};
+
 			icssg0_iep0: iep@b02e000 {
 				compatible = "syscon";
 				reg = <0xb02e000 0x1000>;
@@ -628,6 +644,22 @@
 				reg = <0xb126000 0x200>;
 			};
 
+			icssg1_coreclk_mux: coreclk_mux {
+				#clock-cells = <0>;
+				clocks = <&k3_clks 63 19>, /* icssg1_core_clk */
+					 <&k3_clks 63 3>;  /* icssg1_iclk */
+				assigned-clocks = <&icssg1_coreclk_mux>;
+				assigned-clock-parents = <&k3_clks 63 3>;
+			};
+
+			icssg1_iepclk_mux: iepclk_mux {
+				#clock-cells = <0>;
+				clocks = <&k3_clks 63 10>,	/* icssg1_iep_clk */
+					 <&icssg1_coreclk_mux>;	/* core_clk */
+				assigned-clocks = <&icssg1_iepclk_mux>;
+				assigned-clock-parents = <&icssg1_coreclk_mux>;
+			};
+
 			icssg1_iep0: iep@b12e000 {
 				compatible = "syscon";
 				reg = <0xb12e000 0x1000>;
@@ -757,6 +789,22 @@
 				reg = <0xb226000 0x200>;
 			};
 
+			icssg2_coreclk_mux: coreclk_mux {
+				#clock-cells = <0>;
+				clocks = <&k3_clks 64 19>, /* icssg1_core_clk */
+					 <&k3_clks 64 3>;  /* icssg1_iclk */
+				assigned-clocks = <&icssg2_coreclk_mux>;
+				assigned-clock-parents = <&k3_clks 64 3>;
+			};
+
+			icssg2_iepclk_mux: iepclk_mux {
+				#clock-cells = <0>;
+				clocks = <&k3_clks 64 10>,	/* icssg1_iep_clk */
+					 <&icssg2_coreclk_mux>;	/* core_clk */
+				assigned-clocks = <&icssg2_iepclk_mux>;
+				assigned-clock-parents = <&icssg2_coreclk_mux>;
+			};
+
 			icssg2_iep0: iep@b22e000 {
 				compatible = "syscon";
 				reg = <0xb22e000 0x1000>;