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Kconfig
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ca6f2796ee
clk: tegra: Add BPMP clock driver
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8 years ago |
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Makefile
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b24413180f
License cleanup: add SPDX GPL-2.0 license identifier to files with no license
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7 years ago |
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clk-audio-sync.c
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f6da46a307
clk: tegra: Remove CLK_IS_ROOT
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9 years ago |
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clk-bpmp.c
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231ca2e583
clk: tegra: Check BPMP response return code
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8 years ago |
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clk-dfll.c
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1752c9ee23
clk: tegra: dfll: Fix drvdata overwriting issue
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7 years ago |
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clk-dfll.h
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1752c9ee23
clk: tegra: dfll: Fix drvdata overwriting issue
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7 years ago |
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clk-divider.c
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3ed9c82437
tegra/clk-divider: fix wrong do_div() usage
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9 years ago |
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clk-emc.c
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2dcabf053c
clk: tegra: Mark HCLK, SCLK and EMC as critical
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7 years ago |
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clk-id.h
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fc35c1966e
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
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7 years ago |
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clk-periph-fixed.c
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1ec7032ad5
clk: tegra: Add fixed factor peripheral clock type
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9 years ago |
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clk-periph-gate.c
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9619dba832
clk: tegra: Fix disable unused for clocks sharing enable bit
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8 years ago |
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clk-periph.c
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8be95190da
clk: tegra: Add peripheral clock registration helper
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8 years ago |
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clk-pll-out.c
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584ac4e935
clk: tegra: Properly include clk.h
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10 years ago |
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clk-pll.c
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c35b518f9b
clk: tegra: Fix pll_u rate configuration
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7 years ago |
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clk-super.c
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e827ba1840
clk: tegra: Add super clock mux/divider
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8 years ago |
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clk-tegra-audio.c
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319af7975c
clk: tegra: Define Tegra210 DMIC sync clocks
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8 years ago |
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clk-tegra-fixed.c
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a9caa84812
clk: tegra: Remove trailing blank line
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9 years ago |
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clk-tegra-periph.c
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2dcabf053c
clk: tegra: Mark HCLK, SCLK and EMC as critical
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7 years ago |
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clk-tegra-pmc.c
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a63b6186f9
clk: tegra: Propagate clk_out_x rate to parent
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8 years ago |
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clk-tegra-super-gen4.c
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2dcabf053c
clk: tegra: Mark HCLK, SCLK and EMC as critical
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7 years ago |
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clk-tegra114.c
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c485ad63ab
clk: tegra: Specify VDE clock rate
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7 years ago |
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clk-tegra124-dfll-fcpu.c
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1752c9ee23
clk: tegra: dfll: Fix drvdata overwriting issue
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7 years ago |
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clk-tegra124.c
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c485ad63ab
clk: tegra: Specify VDE clock rate
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7 years ago |
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clk-tegra20.c
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c485ad63ab
clk: tegra: Specify VDE clock rate
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7 years ago |
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clk-tegra210.c
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2dcabf053c
clk: tegra: Mark HCLK, SCLK and EMC as critical
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7 years ago |
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clk-tegra30.c
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c485ad63ab
clk: tegra: Specify VDE clock rate
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7 years ago |
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clk.c
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4236e752f1
clk: tegra: Implement reset control reset
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8 years ago |
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clk.h
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cbfc8d0a85
clk: tegra: add fence_delay for clock registers
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7 years ago |
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cvb.c
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42134fa2b7
clk: tegra: dfll: improve function-level documentation
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9 years ago |
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cvb.h
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f7c42d9862
clk: tegra: dfll: Properly clean up on failure and removal
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9 years ago |
Marcel Ziswiler
c35b518f9b
clk: tegra: Fix pll_u rate configuration