12345678910111213141516171819202122232425262728293031323334353637383940414243444546 |
- /*
- * GXBB clock tree IDs
- */
- #ifndef __GXBB_CLKC_H
- #define __GXBB_CLKC_H
- #define CLKID_CPUCLK 1
- #define CLKID_HDMI_PLL 2
- #define CLKID_FCLK_DIV2 4
- #define CLKID_FCLK_DIV3 5
- #define CLKID_FCLK_DIV4 6
- #define CLKID_GP0_PLL 9
- #define CLKID_CLK81 12
- #define CLKID_MPLL2 15
- #define CLKID_I2C 22
- #define CLKID_SAR_ADC 23
- #define CLKID_RNG0 25
- #define CLKID_SPI 34
- #define CLKID_ETH 36
- #define CLKID_AIU_GLUE 38
- #define CLKID_I2S_OUT 40
- #define CLKID_MIXER_IFACE 44
- #define CLKID_AIU 47
- #define CLKID_USB0 50
- #define CLKID_USB1 51
- #define CLKID_USB 55
- #define CLKID_HDMI_PCLK 63
- #define CLKID_USB1_DDR_BRIDGE 64
- #define CLKID_USB0_DDR_BRIDGE 65
- #define CLKID_SANA 69
- #define CLKID_GCLK_VENCI_INT0 77
- #define CLKID_AOCLK_GATE 80
- #define CLKID_AO_I2C 93
- #define CLKID_SD_EMMC_A 94
- #define CLKID_SD_EMMC_B 95
- #define CLKID_SD_EMMC_C 96
- #define CLKID_SAR_ADC_CLK 97
- #define CLKID_SAR_ADC_SEL 98
- #define CLKID_MALI_0_SEL 100
- #define CLKID_MALI_0 102
- #define CLKID_MALI_1_SEL 103
- #define CLKID_MALI_1 105
- #define CLKID_MALI 106
- #endif /* __GXBB_CLKC_H */
|