 Mahesh Kumar
|
83db373853
drm/i915/icl: Fix DDI/TC port clk_off bits
|
6 years ago |
|
Mahesh Kumar
|
a9b84b4492
drm/i915/icl: create function to identify combophy port
|
6 years ago |
 Dhinakaran Pandiyan
|
9e3b5ce948
drm/i915/psr: Enable AUX-A IO power well on ICL for PSR
|
7 years ago |
 Ville Syrjälä
|
9f9d594d95
drm/i915: Fix ICL+ HDMI clock readout
|
7 years ago |
 Imre Deak
|
2b5cf4ef54
drm/i915/dp_mst: Fix enabling pipe clock for all streams
|
7 years ago |
 Manasi Navare
|
7b19f544ed
drm/i915/icl: Get DDI clock for ICL for MG PLL and TBT PLL
|
7 years ago |
 Jani Nikula
|
dc5977da99
drm/i915: set DP Main Stream Attribute for color range on DDI platforms
|
7 years ago |
 Paulo Zanoni
|
bc334d914e
drm/i915/icl: toggle PHY clock gating around link training
|
7 years ago |
|
Paulo Zanoni
|
340a44bef2
drm/i915/icl: program MG_DP_MODE
|
7 years ago |
|
Manasi Navare
|
07685c827b
drm/i915/icl: Implement voltage swing programming sequence for MG PHY DDI
|
7 years ago |
|
Ville Syrjälä
|
b6ca3eee18
drm/i915: Nuke dev_priv->irq_port[]
|
7 years ago |
 Clint Taylor
|
90c3e21987
drm/i915/glk: Add Quirk for GLK NUC HDMI port issues.
|
7 years ago |
|
Imre Deak
|
b79ebe74e1
drm/i915/ddi: Simplify get_encoder_power_domains()
|
7 years ago |
 Gustavo A. R. Silva
|
f0d759f038
drm/i915: Mark expected switch fall-throughs
|
7 years ago |
|
Imre Deak
|
525280552b
drm/i915/ddi: Get AUX power domain for DP main link too
|
7 years ago |
|
Paulo Zanoni
|
9378985eb0
drm/i915/icl: implement DVFS for ICL
|
7 years ago |
|
Paulo Zanoni
|
1fa11ee2d9
drm/i915/icl: start adding the TBT pll
|
7 years ago |
|
Imre Deak
|
c737376442
drm/i915/ddi: Set HDMI infoframes with pipe clocks enabled
|
7 years ago |
|
Imre Deak
|
afb2c4437d
drm/i915/ddi: Push pipe clock enabling to encoders
|
7 years ago |
|
Manasi Navare
|
dccc7228b5
drm/i915/icl: Add DDI HDMI level selection for ICL
|
7 years ago |
 Arkadiusz Hiler
|
5428bf5a9a
drm/i915/icl: Calculate link clock using the new registers
|
7 years ago |
|
Manasi Navare
|
51c83cfaf9
drm/i915/icl: Get DDI clock for ICL based on PLLs.
|
7 years ago |
|
Mahesh Kumar
|
c46ef57d20
drm/i915/icl: fix icl_unmap/map_plls_to_ports
|
7 years ago |
|
Ville Syrjälä
|
f606bc6d9d
drm/i915: Move intel_ddi_get_crtc_new_encoder() out from ddi code
|
7 years ago |
|
Ville Syrjälä
|
4718a365cf
drm/i915: Use the same vswing->max_preemph mapping on HSW/BDW as on SKL+
|
7 years ago |
|
Paulo Zanoni
|
c27e917e2b
drm/i915/icl: add basic support for the ICL clocks
|
7 years ago |
|
Manasi Navare
|
36cf89f53b
drm/i915/icl: Fix the DP Max Voltage for ICL
|
7 years ago |
|
Manasi Navare
|
fb5c8e9d43
drm/i915/icl: Implement voltage swing programming sequence for Combo PHY DDI
|
7 years ago |
 Lyude Paul
|
be1c63c801
drm/i915/dp: Send DPCD ON for MST before phy_up
|
7 years ago |
 Lucas De Marchi
|
0823eb9c52
drm/i915: use id from intel_shared_dpll.info
|
7 years ago |
