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@@ -916,7 +916,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
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level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
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if (IS_ICELAKE(dev_priv)) {
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- if (port == PORT_A || port == PORT_B)
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+ if (intel_port_is_combophy(dev_priv, port))
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icl_get_combo_buf_trans(dev_priv, port,
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INTEL_OUTPUT_HDMI, &n_entries);
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else
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@@ -1535,7 +1535,7 @@ static void icl_ddi_clock_get(struct intel_encoder *encoder,
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uint32_t pll_id;
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pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
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- if (port == PORT_A || port == PORT_B) {
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+ if (intel_port_is_combophy(dev_priv, port)) {
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if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
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link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
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else
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@@ -2235,7 +2235,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
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int n_entries;
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if (IS_ICELAKE(dev_priv)) {
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- if (port == PORT_A || port == PORT_B)
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+ if (intel_port_is_combophy(dev_priv, port))
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icl_get_combo_buf_trans(dev_priv, port, encoder->type,
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&n_entries);
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else
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@@ -2669,9 +2669,10 @@ static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
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u32 level,
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enum intel_output_type type)
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{
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+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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enum port port = encoder->port;
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- if (port == PORT_A || port == PORT_B)
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+ if (intel_port_is_combophy(dev_priv, port))
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icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
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else
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icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
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@@ -2757,7 +2758,7 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc,
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val = I915_READ(DPCLKA_CFGCR0_ICL);
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WARN_ON((val & DPCLKA_CFGCR0_DDI_CLK_OFF(port)) == 0);
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- if (port == PORT_A || port == PORT_B) {
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+ if (intel_port_is_combophy(dev_priv, port)) {
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val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
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val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
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I915_WRITE(DPCLKA_CFGCR0_ICL, val);
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@@ -2810,7 +2811,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
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mutex_lock(&dev_priv->dpll_lock);
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if (IS_ICELAKE(dev_priv)) {
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- if (port >= PORT_C)
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+ if (!intel_port_is_combophy(dev_priv, port))
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I915_WRITE(DDI_CLK_SEL(port),
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icl_pll_to_ddi_pll_sel(encoder, pll));
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} else if (IS_CANNONLAKE(dev_priv)) {
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@@ -2852,7 +2853,7 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
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enum port port = encoder->port;
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if (IS_ICELAKE(dev_priv)) {
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- if (port >= PORT_C)
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+ if (!intel_port_is_combophy(dev_priv, port))
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I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
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} else if (IS_CANNONLAKE(dev_priv)) {
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I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
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