 Thierry Reding
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8097d4c75f
clk: tegra: Make vde a child of pll_c3
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%!s(int64=7) %!d(string=hai) anos |
|
Thierry Reding
|
26f8590c4a
clk: tegra: Make vic03 a child of pll_c3
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%!s(int64=7) %!d(string=hai) anos |
 Dmitry Osipenko
|
5d797111af
clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20
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%!s(int64=7) %!d(string=hai) anos |
|
Dmitry Osipenko
|
c485ad63ab
clk: tegra: Specify VDE clock rate
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%!s(int64=7) %!d(string=hai) anos |
|
Dmitry Osipenko
|
2dcabf053c
clk: tegra: Mark HCLK, SCLK and EMC as critical
|
%!s(int64=7) %!d(string=hai) anos |
 Peter De Schrijver
|
bfa34832df
clk: tegra: Add CEC clock
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%!s(int64=8) %!d(string=hai) anos |
 Andrew Bresticker
|
15d68e8c2e
clk: tegra: Initialize UTMI PLL when enabling PLLU
|
%!s(int64=9) %!d(string=hai) anos |
|
Thierry Reding
|
eede7113aa
clk: tegra: dpaux and dpaux1 are fixed factor clocks
|
%!s(int64=10) %!d(string=hai) anos |
 Rhyland Klein
|
86c679a522
clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate
|
%!s(int64=10) %!d(string=hai) anos |
|
Rhyland Klein
|
3706b43629
clk: tegra: pll: Don't unconditionally set LOCK flags
|
%!s(int64=10) %!d(string=hai) anos |
|
Thierry Reding
|
385f9adf62
clk: tegra: Constify pdiv-to-hw mappings
|
%!s(int64=9) %!d(string=hai) anos |
|
Thierry Reding
|
8d99704fde
clk: tegra: Format tables consistently
|
%!s(int64=10) %!d(string=hai) anos |
|
Thierry Reding
|
e52d7c04bb
clk: tegra: Miscellaneous coding style cleanups
|
%!s(int64=10) %!d(string=hai) anos |
|
Thierry Reding
|
c4947e364b
clk: tegra: Fix 26 MHz oscillator frequency
|
%!s(int64=10) %!d(string=hai) anos |
|
Rhyland Klein
|
88d909bedf
clk: tegra: Modify tegra_audio_clk_init to accept more plls
|
%!s(int64=10) %!d(string=hai) anos |
 Stephen Boyd
|
c5a132a84a
clk: tegra: Fix some static checker problems
|
%!s(int64=10) %!d(string=hai) anos |
|
Stephen Boyd
|
a7c602bf42
Merge tag 'tegra-for-4.3-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next
|
%!s(int64=10) %!d(string=hai) anos |
|
Stephen Boyd
|
584ac4e935
clk: tegra: Properly include clk.h
|
%!s(int64=10) %!d(string=hai) anos |
 Tuomas Tynkkynen
|
c38864a703
clk: tegra: Save/restore CCLKG_BURST_POLICY on suspend
|
%!s(int64=10) %!d(string=hai) anos |
 Paul Walmsley
|
a3c83ff20c
clk: tegra: Add DFLL DVCO reset control for Tegra124
|
%!s(int64=10) %!d(string=hai) anos |
 Tomeu Vizoso
|
ac67477f8f
clk: tegra: Set the EMC clock as the parent of the MC clock
|
%!s(int64=10) %!d(string=hai) anos |
 Mikko Perttunen
|
2db04f16b5
clk: tegra: Add EMC clock driver
|
%!s(int64=10) %!d(string=hai) anos |
|
Mikko Perttunen
|
374ffadaf3
clk: tegra: Remove old Tegra124 EMC clock
|
%!s(int64=10) %!d(string=hai) anos |
|
Thierry Reding
|
c1d676cec5
clk: tegra: Use the proper parent for plld_dsi
|
%!s(int64=10) %!d(string=hai) anos |
|
Thierry Reding
|
63cc5a4da1
clk: tegra: Model oscillator as clock
|
%!s(int64=10) %!d(string=hai) anos |
 Dylan Reid
|
04794d982e
clk: tegra: Enable HDA to HDMI clocks on Tegra124
|
%!s(int64=11) %!d(string=hai) anos |
 Mark Zhang
|
b270491eb9
clk: tegra: Define PLLD_DSI and remove dsia(b)_mux
|
%!s(int64=10) %!d(string=hai) anos |
|
Paul Walmsley
|
08acae34e8
clk: tegra: Add support for the Tegra132 CAR IP block
|
%!s(int64=10) %!d(string=hai) anos |
 Sean Paul
|
f892f24b37
clk: tegra124: Add init data for dsi lp clocks
|
%!s(int64=11) %!d(string=hai) anos |
|
Thierry Reding
|
4f4f85fa0b
clk: tegra: Implement memory-controller clock
|
%!s(int64=11) %!d(string=hai) anos |
