 Jerome Brunet
|
87173557d2
clk: meson: clk-pll: remove od parameters
|
%!s(int64=7) %!d(string=hai) anos |
|
Jerome Brunet
|
7df533a7e3
clk: meson: add gen_clk
|
%!s(int64=7) %!d(string=hai) anos |
 Yixun Lan
|
cddcb20b2b
clk: meson-axg: add clocks required by pcie driver
|
%!s(int64=7) %!d(string=hai) anos |
|
Jerome Brunet
|
05f814402d
clk: meson: add fdiv clock gates
|
%!s(int64=7) %!d(string=hai) anos |
|
Jerome Brunet
|
513b67ac39
clk: meson: add mpll pre-divider
|
%!s(int64=7) %!d(string=hai) anos |
|
Jerome Brunet
|
093c3fac46
clk: meson: axg: add hifi pll clock
|
%!s(int64=7) %!d(string=hai) anos |
|
Jerome Brunet
|
d610b54f77
clk: meson: split divider and gate part of mpll
|
%!s(int64=7) %!d(string=hai) anos |
 Qiufang Dai
|
78b4af312f
clk: meson-axg: add clock controller drivers
|
%!s(int64=7) %!d(string=hai) anos |
