 Jerome Brunet
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87173557d2
clk: meson: clk-pll: remove od parameters
|
7 years ago |
|
Jerome Brunet
|
7df533a7e3
clk: meson: add gen_clk
|
7 years ago |
 Yixun Lan
|
cddcb20b2b
clk: meson-axg: add clocks required by pcie driver
|
7 years ago |
|
Jerome Brunet
|
05f814402d
clk: meson: add fdiv clock gates
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7 years ago |
|
Jerome Brunet
|
513b67ac39
clk: meson: add mpll pre-divider
|
7 years ago |
|
Jerome Brunet
|
093c3fac46
clk: meson: axg: add hifi pll clock
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7 years ago |
|
Jerome Brunet
|
d610b54f77
clk: meson: split divider and gate part of mpll
|
7 years ago |
 Qiufang Dai
|
78b4af312f
clk: meson-axg: add clock controller drivers
|
7 years ago |
