 Jerome Brunet
|
d6ee1e7e90
clk: meson: axg: mark fdiv2 and fdiv3 as critical
|
há 6 anos atrás |
 Yixun Lan
|
69b93104c7
clk: meson-axg: pcie: drop the mpll3 clock parent
|
há 7 anos atrás |
|
Jerome Brunet
|
dd601dbc01
clk: meson: clk-pll: drop hard-coded rates from pll tables
|
há 7 anos atrás |
|
Jerome Brunet
|
87173557d2
clk: meson: clk-pll: remove od parameters
|
há 7 anos atrás |
|
Jerome Brunet
|
2303a9ca69
clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessary
|
há 7 anos atrás |
|
Jerome Brunet
|
e40c7e3cda
clk: meson: clk-pll: add enable bit
|
há 7 anos atrás |
|
Jerome Brunet
|
7df533a7e3
clk: meson: add gen_clk
|
há 7 anos atrás |
|
Yixun Lan
|
cddcb20b2b
clk: meson-axg: add clocks required by pcie driver
|
há 7 anos atrás |
|
Jerome Brunet
|
60e267f3fd
clk: meson: remove obsolete register access
|
há 7 anos atrás |
|
Jerome Brunet
|
de1ca2d07b
clk: meson: axg: let mpll clocks round closest
|
há 7 anos atrás |
 Stephen Boyd
|
5d1c04dde0
clk: meson: Drop unused local variable and add static
|
há 7 anos atrás |
|
Jerome Brunet
|
05f814402d
clk: meson: add fdiv clock gates
|
há 7 anos atrás |
|
Jerome Brunet
|
513b67ac39
clk: meson: add mpll pre-divider
|
há 7 anos atrás |
|
Jerome Brunet
|
093c3fac46
clk: meson: axg: add hifi pll clock
|
há 7 anos atrás |
|
Jerome Brunet
|
c77de0e5c9
clk: meson: add gp0 frac parameter for axg and gxl
|
há 7 anos atrás |
|
Jerome Brunet
|
c178b003bf
clk: meson: remove special gp0 lock loop
|
há 7 anos atrás |
|
Jerome Brunet
|
117863e842
clk: meson: poke pll CNTL last
|
há 7 anos atrás |
|
Jerome Brunet
|
4162dd5b3a
clk: meson: use hhi syscon if available
|
há 7 anos atrás |
|
Jerome Brunet
|
d610b54f77
clk: meson: split divider and gate part of mpll
|
há 7 anos atrás |
|
Jerome Brunet
|
722825dcd5
clk: meson: migrate plls clocks to clk_regmap
|
há 7 anos atrás |
|
Jerome Brunet
|
c763e61ae8
clk: meson: migrate mplls clocks to clk_regmap
|
há 7 anos atrás |
|
Jerome Brunet
|
2513a28c10
clk: meson: migrate muxes to clk_regmap
|
há 7 anos atrás |
|
Jerome Brunet
|
f06ddd2852
clk: meson: migrate dividers to clk_regmap
|
há 7 anos atrás |
|
Jerome Brunet
|
7f9768a540
clk: meson: migrate gates to clk_regmap
|
há 7 anos atrás |
|
Jerome Brunet
|
161f6e5baa
clk: meson: add regmap to the clock controllers
|
há 7 anos atrás |
|
Jerome Brunet
|
7b174c5ebe
clk: meson: remove obsolete comments
|
há 7 anos atrás |
|
Jerome Brunet
|
14bd7b9c8d
clk: meson: only one loop index is necessary in probe
|
há 7 anos atrás |
|
Jerome Brunet
|
332b32a232
clk: meson: use devm_of_clk_add_hw_provider
|
há 7 anos atrás |
|
Jerome Brunet
|
323346d31d
clk: meson: use dev pointer where possible
|
há 7 anos atrás |
|
Jerome Brunet
|
6c00e7b760
clk: meson: add axg misc bit to the mpll driver
|
há 7 anos atrás |
