 Chen Zhong
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c955bf3998
clk: mediatek: add the option for determining PLL source clock
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%!s(int64=8) %!d(string=hai) anos |
 weiyi.lu@mediatek.com
|
e2f744a82d
clk: mediatek: Add MT2712 clock support
|
%!s(int64=8) %!d(string=hai) anos |
 Shunli Wang
|
e986211827
clk: mediatek: Add MT2701 clock support
|
%!s(int64=9) %!d(string=hai) anos |
 James Liao
|
928f3bfb81
clk: mediatek: remove __init from clk registration functions
|
%!s(int64=9) %!d(string=hai) anos |
|
James Liao
|
cdb2bab78a
clk: mediatek: Add USB clock support in MT8173 APMIXEDSYS
|
%!s(int64=10) %!d(string=hai) anos |
|
James Liao
|
75ce0cdb62
clk: mediatek: Add MT8173 MMPLL change rate support
|
%!s(int64=10) %!d(string=hai) anos |
|
James Liao
|
196de71a9d
clk: mediatek: Fix calculation of PLL rate settings
|
%!s(int64=10) %!d(string=hai) anos |
|
James Liao
|
b3be457e58
clk: mediatek: Fix PLL registers setting flow
|
%!s(int64=10) %!d(string=hai) anos |
 Ricky Liang
|
95f589814c
clk: mediatek: Initialize clk_init_data
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%!s(int64=10) %!d(string=hai) anos |
|
James Liao
|
9741b1a680
clk: mediatek: Add initial common clock support for Mediatek SoCs.
|
%!s(int64=10) %!d(string=hai) anos |
