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+/*
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+ * Copyright (c) 2014 MediaTek Inc.
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+ * Author: James Liao <jamesjj.liao@mediatek.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#include <linux/of.h>
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+#include <linux/of_address.h>
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+#include <linux/io.h>
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+#include <linux/slab.h>
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+#include <linux/clkdev.h>
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+#include <linux/delay.h>
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+
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+#include "clk-mtk.h"
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+
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+#define REG_CON0 0
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+#define REG_CON1 4
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+
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+#define CON0_BASE_EN BIT(0)
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+#define CON0_PWR_ON BIT(0)
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+#define CON0_ISO_EN BIT(1)
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+#define CON0_PCW_CHG BIT(31)
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+
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+#define AUDPLL_TUNER_EN BIT(31)
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+
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+#define POSTDIV_MASK 0x7
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+#define INTEGER_BITS 7
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+
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+/*
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+ * MediaTek PLLs are configured through their pcw value. The pcw value describes
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+ * a divider in the PLL feedback loop which consists of 7 bits for the integer
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+ * part and the remaining bits (if present) for the fractional part. Also they
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+ * have a 3 bit power-of-two post divider.
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+ */
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+
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+struct mtk_clk_pll {
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+ struct clk_hw hw;
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+ void __iomem *base_addr;
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+ void __iomem *pd_addr;
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+ void __iomem *pwr_addr;
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+ void __iomem *tuner_addr;
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+ void __iomem *pcw_addr;
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+ const struct mtk_pll_data *data;
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+};
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+
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+static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw)
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+{
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+ return container_of(hw, struct mtk_clk_pll, hw);
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+}
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+
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+static int mtk_pll_is_prepared(struct clk_hw *hw)
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+{
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+ struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
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+
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+ return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0;
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+}
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+
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+static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
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+ u32 pcw, int postdiv)
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+{
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+ int pcwbits = pll->data->pcwbits;
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+ int pcwfbits;
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+ u64 vco;
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+ u8 c = 0;
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+
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+ /* The fractional part of the PLL divider. */
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+ pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0;
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+
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+ vco = (u64)fin * pcw;
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+
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+ if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0)))
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+ c = 1;
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+
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+ vco >>= pcwfbits;
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+
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+ if (c)
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+ vco++;
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+
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+ return ((unsigned long)vco + postdiv - 1) / postdiv;
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+}
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+
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+static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
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+ int postdiv)
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+{
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+ u32 con1, pd, val;
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+ int pll_en;
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+
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+ /* set postdiv */
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+ pd = readl(pll->pd_addr);
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+ pd &= ~(POSTDIV_MASK << pll->data->pd_shift);
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+ pd |= (ffs(postdiv) - 1) << pll->data->pd_shift;
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+ writel(pd, pll->pd_addr);
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+
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+ pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN;
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+
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+ /* set pcw */
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+ val = readl(pll->pcw_addr);
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+
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+ val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1,
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+ pll->data->pcw_shift);
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+ val |= pcw << pll->data->pcw_shift;
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+ writel(val, pll->pcw_addr);
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+
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+ con1 = readl(pll->base_addr + REG_CON1);
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+
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+ if (pll_en)
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+ con1 |= CON0_PCW_CHG;
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+
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+ writel(con1, pll->base_addr + REG_CON1);
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+ if (pll->tuner_addr)
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+ writel(con1 + 1, pll->tuner_addr);
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+
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+ if (pll_en)
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+ udelay(20);
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+}
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+
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+/*
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+ * mtk_pll_calc_values - calculate good values for a given input frequency.
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+ * @pll: The pll
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+ * @pcw: The pcw value (output)
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+ * @postdiv: The post divider (output)
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+ * @freq: The desired target frequency
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+ * @fin: The input frequency
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+ *
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+ */
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+static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
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+ u32 freq, u32 fin)
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+{
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+ unsigned long fmin = 1000 * MHZ;
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+ u64 _pcw;
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+ u32 val;
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+
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+ if (freq > pll->data->fmax)
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+ freq = pll->data->fmax;
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+
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+ for (val = 0; val < 4; val++) {
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+ *postdiv = 1 << val;
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+ if (freq * *postdiv >= fmin)
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+ break;
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+ }
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+
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+ /* _pcw = freq * postdiv / fin * 2^pcwfbits */
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+ _pcw = ((u64)freq << val) << (pll->data->pcwbits - INTEGER_BITS);
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+ do_div(_pcw, fin);
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+
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+ *pcw = (u32)_pcw;
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+}
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+
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+static int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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+ unsigned long parent_rate)
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+{
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+ struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
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+ u32 pcw = 0;
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+ u32 postdiv;
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+
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+ mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate);
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+ mtk_pll_set_rate_regs(pll, pcw, postdiv);
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+
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+ return 0;
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+}
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+
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+static unsigned long mtk_pll_recalc_rate(struct clk_hw *hw,
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+ unsigned long parent_rate)
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+{
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+ struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
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+ u32 postdiv;
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+ u32 pcw;
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+
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+ postdiv = (readl(pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK;
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+ postdiv = 1 << postdiv;
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+
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+ pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift;
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+ pcw &= GENMASK(pll->data->pcwbits - 1, 0);
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+
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+ return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv);
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+}
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+
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+static long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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+ unsigned long *prate)
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+{
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+ struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
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+ u32 pcw = 0;
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+ int postdiv;
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+
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+ mtk_pll_calc_values(pll, &pcw, &postdiv, rate, *prate);
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+
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+ return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv);
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+}
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+
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+static int mtk_pll_prepare(struct clk_hw *hw)
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+{
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+ struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
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+ u32 r;
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+
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+ r = readl(pll->pwr_addr) | CON0_PWR_ON;
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+ writel(r, pll->pwr_addr);
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+ udelay(1);
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+
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+ r = readl(pll->pwr_addr) & ~CON0_ISO_EN;
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+ writel(r, pll->pwr_addr);
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+ udelay(1);
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+
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+ r = readl(pll->base_addr + REG_CON0);
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+ r |= pll->data->en_mask;
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+ writel(r, pll->base_addr + REG_CON0);
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+
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+ if (pll->tuner_addr) {
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+ r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
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+ writel(r, pll->tuner_addr);
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+ }
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+
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+ udelay(20);
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+
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+ if (pll->data->flags & HAVE_RST_BAR) {
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+ r = readl(pll->base_addr + REG_CON0);
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+ r |= pll->data->rst_bar_mask;
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+ writel(r, pll->base_addr + REG_CON0);
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+ }
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+
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+ return 0;
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+}
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+
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+static void mtk_pll_unprepare(struct clk_hw *hw)
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+{
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+ struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
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+ u32 r;
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+
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+ if (pll->data->flags & HAVE_RST_BAR) {
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+ r = readl(pll->base_addr + REG_CON0);
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+ r &= ~pll->data->rst_bar_mask;
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+ writel(r, pll->base_addr + REG_CON0);
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+ }
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+
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+ if (pll->tuner_addr) {
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+ r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
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+ writel(r, pll->tuner_addr);
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+ }
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+
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+ r = readl(pll->base_addr + REG_CON0);
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+ r &= ~CON0_BASE_EN;
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+ writel(r, pll->base_addr + REG_CON0);
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+
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+ r = readl(pll->pwr_addr) | CON0_ISO_EN;
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+ writel(r, pll->pwr_addr);
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+
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+ r = readl(pll->pwr_addr) & ~CON0_PWR_ON;
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+ writel(r, pll->pwr_addr);
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+}
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+
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+static const struct clk_ops mtk_pll_ops = {
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+ .is_prepared = mtk_pll_is_prepared,
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+ .prepare = mtk_pll_prepare,
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+ .unprepare = mtk_pll_unprepare,
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+ .recalc_rate = mtk_pll_recalc_rate,
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+ .round_rate = mtk_pll_round_rate,
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+ .set_rate = mtk_pll_set_rate,
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+};
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+
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+static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
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+ void __iomem *base)
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+{
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+ struct mtk_clk_pll *pll;
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+ struct clk_init_data init;
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+ struct clk *clk;
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+ const char *parent_name = "clk26m";
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+
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+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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+ if (!pll)
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+ return ERR_PTR(-ENOMEM);
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+
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+ pll->base_addr = base + data->reg;
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+ pll->pwr_addr = base + data->pwr_reg;
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+ pll->pd_addr = base + data->pd_reg;
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+ pll->pcw_addr = base + data->pcw_reg;
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+ if (data->tuner_reg)
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+ pll->tuner_addr = base + data->tuner_reg;
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+ pll->hw.init = &init;
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+ pll->data = data;
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+
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+ init.name = data->name;
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+ init.ops = &mtk_pll_ops;
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+ init.parent_names = &parent_name;
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+ init.num_parents = 1;
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+
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+ clk = clk_register(NULL, &pll->hw);
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+
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+ if (IS_ERR(clk))
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+ kfree(pll);
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+
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+ return clk;
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+}
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+
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+void __init mtk_clk_register_plls(struct device_node *node,
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+ const struct mtk_pll_data *plls, int num_plls, struct clk_onecell_data *clk_data)
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+{
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+ void __iomem *base;
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+ int r, i;
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+ struct clk *clk;
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+
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+ base = of_iomap(node, 0);
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+ if (!base) {
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+ pr_err("%s(): ioremap failed\n", __func__);
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+ return;
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+ }
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+
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+ for (i = 0; i < num_plls; i++) {
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+ const struct mtk_pll_data *pll = &plls[i];
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+
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+ clk = mtk_clk_register_pll(pll, base);
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+
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+ if (IS_ERR(clk)) {
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+ pr_err("Failed to register clk %s: %ld\n",
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+ pll->name, PTR_ERR(clk));
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+ continue;
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+ }
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+
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+ clk_data->clks[pll->id] = clk;
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+ }
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+
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+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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+ if (r)
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+ pr_err("%s(): could not register clock provider: %d\n",
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+ __func__, r);
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+}
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James Liao