 Atish Patra
|
f99fb607fb
RISC-V: Use Linux logical CPU number instead of hartid
|
%!s(int64=6) %!d(string=hai) anos |
|
Atish Patra
|
a37d56fc40
RISC-V: Use WRITE_ONCE instead of direct access
|
%!s(int64=6) %!d(string=hai) anos |
 Palmer Dabbelt
|
46373cb442
RISC-V: Use mmgrab()
|
%!s(int64=6) %!d(string=hai) anos |
|
Palmer Dabbelt
|
177fae4515
RISC-V: Rename im_okay_therefore_i_am to found_boot_cpu
|
%!s(int64=6) %!d(string=hai) anos |
|
Palmer Dabbelt
|
b2f8cfa7ac
RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid
|
%!s(int64=6) %!d(string=hai) anos |
|
Atish Patra
|
6db170ff4c
RISC-V: Disable preemption before enabling interrupts
|
%!s(int64=6) %!d(string=hai) anos |
|
Palmer Dabbelt
|
b18d6f0525
RISC-V: Comment on the TLB flush in smp_callin()
|
%!s(int64=6) %!d(string=hai) anos |
 Palmer Dabbelt
|
62b0194368
clocksource: new RISC-V SBI timer driver
|
%!s(int64=7) %!d(string=hai) anos |
|
Palmer Dabbelt
|
76d2a0493a
RISC-V: Init and Halt Code
|
%!s(int64=8) %!d(string=hai) anos |
