 Rodrigo Vivi
|
8a00678a09
drm/i915/cnl: Simplify dco_fraction calculation.
|
7 years ago |
|
Rodrigo Vivi
|
cacf6fe7c6
drm/i915/cnl: Don't blindly replace qdiv.
|
7 years ago |
|
Rodrigo Vivi
|
063c886197
drm/i915/cnl: Fix wrpll math for higher freqs.
|
7 years ago |
|
Rodrigo Vivi
|
5eca81de88
drm/i915/cnl: Fix, simplify and unify wrpll variable sizes.
|
7 years ago |
|
Rodrigo Vivi
|
ecc2069a02
drm/i915/cnl: Remove useless conversion.
|
7 years ago |
|
Rodrigo Vivi
|
ec2f343e72
drm/i915/cnl: Remove spurious central_freq.
|
7 years ago |
 Ville Syrjälä
|
005b5bc694
drm/i915: Replace dig_port->port with encoder port for BXT DPLL selection
|
7 years ago |
|
Ville Syrjälä
|
f49b44ab84
drm/i915: Start using output_types for DPLL selection
|
7 years ago |
|
Ville Syrjälä
|
53e9bf5e81
drm/i915: Adjust system agent voltage on CNL if required by DDI ports
|
7 years ago |
|
Rodrigo Vivi
|
614ee07acf
drm/i915/cnl: Fix PLL initialization for HDMI.
|
8 years ago |
|
Rodrigo Vivi
|
c1b56c52aa
drm/i915/cnl: Dump the right pll registers when dumping pipe config.
|
8 years ago |
 Colin Ian King
|
29962acaa0
drm/i915/cnl: make function cnl_ddi_dp_set_dpll_hw_state static
|
8 years ago |
 Kahola, Mika
|
1fa62e1b76
drm/i915/cnl: Enable wrpll computation for CNL
|
8 years ago |
|
Rodrigo Vivi
|
a927c927de
drm/i915/cnl: Initialize PLLs
|
8 years ago |
 Ander Conselvan de Oliveira
|
370a81fb89
drm/i915: Remove unused function intel_ddi_get_link_dpll()
|
8 years ago |
 Lee, Shawn C
|
0aab2c721d
drm/i915/bxt: Add MST support when do DPLL calculation
|
8 years ago |
|
Rodrigo Vivi
|
b976dc53ec
drm/i915: Introduce IS_GEN9_BC for Skylake and Kabylake.
|
8 years ago |
|
Ander Conselvan de Oliveira
|
8e45ac1f0f
drm/i915: Move intel_atomic_get_shared_dpll_state() to intel_dpll_mgr.c
|
8 years ago |
|
Ander Conselvan de Oliveira
|
f50b79f096
drm/i915: Add dpll entrypoint for dumping hw state
|
8 years ago |
|
Ander Conselvan de Oliveira
|
294591cfbd
drm/i915: Update kerneldoc for intel_dpll_mgr.c
|
8 years ago |
|
Ander Conselvan de Oliveira
|
eac6176cbd
drm/i915: Rename intel_shared_dpll->mode_set() to prepare()
|
8 years ago |
|
Ander Conselvan de Oliveira
|
2c42e53514
drm/i915: Rename intel_shared_dpll_config to intel_shared_dpll_state
|
8 years ago |
|
Ander Conselvan de Oliveira
|
3c0fb58820
drm/i915: Rename intel_shared_dpll_commit() to _swap_state()
|
8 years ago |
|
Ander Conselvan de Oliveira
|
a1c414ee82
drm/i915: Introduce intel_release_shared_dpll()
|
8 years ago |
 Madhav Chauhan
|
f7044dd904
drm/i915/glk: Update Port PLL enable sequence for Geminilkae
|
8 years ago |
|
Ander Conselvan de Oliveira
|
51b3ee35af
drm/i915/glk: Set DCC delay range 2 in PLL enable sequence
|
8 years ago |
|
Ander Conselvan de Oliveira
|
0a116ce895
drm/i915/glk: Implement Geminilake DDI init sequence
|
8 years ago |
|
Ander Conselvan de Oliveira
|
cc3f90f063
drm/i915/glk: Reuse broxton code for geminilake
|
8 years ago |
 Tvrtko Ursulin
|
66478475b5
drm/i915: Assorted INTEL_INFO(dev) cleanups
|
8 years ago |
|
Ander Conselvan de Oliveira
|
ed37892e6d
drm/i915: Address broxton phy registers based on phy and channel number
|
8 years ago |
