 Dave Airlie
|
4a6cc7a44e
BackMerge tag 'v4.15-rc8' into drm-next
|
7 年之前 |
 Lucas De Marchi
|
30414f3010
drm/i915: Apply Display WA #1183 on skl, kbl, and cfl
|
7 年之前 |
 Maarten Lankhorst
|
24f2845056
drm/i915: Make ips_enabled a property depending on whether IPS is enabled, v3.
|
7 年之前 |
 Rodrigo Vivi
|
43037c86d1
drm/i915/cnl: Allow 2 pixel per clock on Cannonlake.
|
8 年之前 |
 Ville Syrjälä
|
cfddadc98a
drm/i915: Perform a central cdclk state sanity check
|
7 年之前 |
|
Ville Syrjälä
|
0c9f353f01
drm/i915: Sanity check cdclk in vlv_set_cdclk()
|
7 年之前 |
|
Ville Syrjälä
|
53e9bf5e81
drm/i915: Adjust system agent voltage on CNL if required by DDI ports
|
7 年之前 |
|
Ville Syrjälä
|
48469eced2
drm/i915: Use cdclk_state->voltage on CNL
|
7 年之前 |
|
Ville Syrjälä
|
2123f442ca
drm/i915: Use cdclk_state->voltage on BXT/GLK
|
7 年之前 |
|
Ville Syrjälä
|
2aa97491da
drm/i915: Use cdclk_state->voltage on SKL/KBL/CFL
|
7 年之前 |
|
Ville Syrjälä
|
d7ffaeef96
drm/i915: Use cdclk_state->voltage on BDW
|
7 年之前 |
|
Ville Syrjälä
|
999c5766f3
drm/i915: Use cdclk_state->voltage on VLV/CHV
|
7 年之前 |
|
Ville Syrjälä
|
64600bd5b8
drm/i915: Start tracking voltage level in the cdclk state
|
7 年之前 |
|
Ville Syrjälä
|
2b58417ffb
drm/i915: Clean up some cdclk switch statements
|
7 年之前 |
 Sagar Arun Kamble
|
9f817501bd
drm/i915: Move rps.hw_lock to dev_priv and s/hw_lock/pcu_lock
|
8 年之前 |
 Marta Lofstedt
|
3164888a40
drm/i915: Increase poll time for BDW FCLK_DONE
|
8 年之前 |
|
Ville Syrjälä
|
9c61de4c69
drm/i915: Consolidate max_cdclk_freq check in intel_crtc_compute_min_cdclk()
|
8 年之前 |
|
Ville Syrjälä
|
d305e06146
drm/i915: Track minimum acceptable cdclk instead of "minimum dotclock"
|
8 年之前 |
 Gabriel Krisman Bertazi
|
886015a0ad
drm/i915: reintroduce VLV/CHV PFI programming power domain workaround
|
8 年之前 |
|
Rodrigo Vivi
|
d1999e9ef8
drm/i915/cnl: Allow dynamic cdclk changes on CNL
|
8 年之前 |
|
Ville Syrjälä
|
d8d4a512a6
drm/i915/cnl: Implement CNL display init/unit sequence
|
8 年之前 |
|
Ville Syrjälä
|
ef4f7a689a
drm/i915/cnl: Implement .set_cdclk() for CNL
|
8 年之前 |
|
Ville Syrjälä
|
945f2672cc
drm/i915/cnl: Implement .get_display_clock_speed() for CNL
|
8 年之前 |
|
Rodrigo Vivi
|
9d81a99713
drm/i915/cnp: Get/set proper Raw clock frequency on CNP.
|
8 年之前 |
|
Ville Syrjälä
|
6f38123eca
drm/i915: Fix rawclk readout for g4x
|
8 年之前 |
 Madhav Chauhan
|
97f55ca5b6
drm/i915/glk: limit pixel clock to 99% of cdclk workaround
|
8 年之前 |
 Pandiyan, Dhinakaran
|
8cbeb06dc6
drm/i915: Implement cdclk restrictions based on Azalia BCLK
|
8 年之前 |
|
Pandiyan, Dhinakaran
|
78cfa580f8
drm/i915/glk: Apply cdclk workaround for DP audio
|
8 年之前 |
|
Maarten Lankhorst
|
e6963ccf5b
drm/i915: Use new atomic iterator macros in cdclk
|
8 年之前 |
 Paulo Zanoni
|
6b9e441df4
drm/i915: remove potentially confusing IS_G4X checks
|
8 年之前 |
