 Gaurav K Singh
|
20dbe1a1cb
drm/i915: Changes required to enable DSI Video Mode on CHT
|
10 years ago |
|
Gaurav K Singh
|
3c5c6d8885
drm/i915: Support for higher DSI clk
|
10 years ago |
 Jani Nikula
|
260c1ad199
drm/i915/dsi: abstract dsi bpp derivation from pixel format
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10 years ago |
 Ville Syrjälä
|
a580516d9f
drm/i915: s/dpio_lock/sb_lock/
|
10 years ago |
|
Jani Nikula
|
a856c5bdf4
drm/i915/dsi: add support for DSI PLL N1 divisor values
|
10 years ago |
|
Jani Nikula
|
7471bf4e0e
drm/i915: clean up dsi pll calculation
|
10 years ago |
|
Gaurav K Singh
|
3c860ab40c
drm/i915: Use DSI Pll1 for enabling MIPI DSI on Port C
|
10 years ago |
|
Gaurav K Singh
|
3770f0eec4
drm/i915: cck reg used for checking DSI Pll locked
|
10 years ago |
|
Gaurav K Singh
|
58cf8887c9
drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual link
|
10 years ago |
 Daniel Vetter
|
7f3de8336f
drm/i915: Align intel_dsi*.c files a bit
|
11 years ago |
 Shobhit Kumar
|
7f0c860533
drm/i915: Add support for Video Burst Mode for MIPI DSI
|
11 years ago |
|
Shobhit Kumar
|
f573de5a84
drm/i915: Add correct hw/sw config check for DSI encoder
|
11 years ago |
|
Shobhit Kumar
|
8e1eed5aa8
drm/i915: Try harder to get best m, n, p values with minimal error
|
11 years ago |
|
Shobhit Kumar
|
44d4c6eebb
drm/i915: Compute dsi_clk from pixel clock
|
11 years ago |
|
Ville Syrjälä
|
a748214542
drm/i915: Use adjusted_mode in DSI PLL calculations
|
12 years ago |
 ymohanma
|
be4fc046be
drm/i915: add VLV DSI PLL Calculations
|
12 years ago |
