 Bin Gao
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f3a02ecebe
x86/tsc: Set TSC_KNOWN_FREQ and TSC_RELIABLE flags on Intel Atom SoCs
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%!s(int64=8) %!d(string=hai) anos |
 Len Brown
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02c0cd2dcf
x86/tsc_msr: Remove irqoff around MSR-based TSC enumeration
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%!s(int64=9) %!d(string=hai) anos |
|
Len Brown
|
6fcb41cdae
x86/tsc_msr: Add Airmont reference clock values
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%!s(int64=9) %!d(string=hai) anos |
|
Len Brown
|
05680e7fa8
x86/tsc_msr: Correct Silvermont reference clock values
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%!s(int64=9) %!d(string=hai) anos |
|
Len Brown
|
9e0cae9f62
x86/tsc_msr: Update comments, expand definitions
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%!s(int64=9) %!d(string=hai) anos |
|
Len Brown
|
14bb4e3486
x86/tsc_msr: Remove debugging messages
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%!s(int64=9) %!d(string=hai) anos |
|
Len Brown
|
ba8268330d
x86/tsc_msr: Identify Intel-specific code
|
%!s(int64=9) %!d(string=hai) anos |
|
Len Brown
|
fc5f3ac247
Revert "x86/tsc: Add missing Cherrytrail frequency to the table"
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%!s(int64=9) %!d(string=hai) anos |
 Jeremy Compostella
|
e2724e9d96
x86/tsc: Add missing Cherrytrail frequency to the table
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%!s(int64=9) %!d(string=hai) anos |
 Chen Yu
|
886123fb3a
x86/tsc: Read all ratio bits from MSR_PLATFORM_INFO
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%!s(int64=9) %!d(string=hai) anos |
 Mika Westerberg
|
3e11e818bf
x86: tsc: Add missing Baytrail frequency to the table
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%!s(int64=11) %!d(string=hai) anos |
 Thomas Gleixner
|
5f0e030930
x86, tsc: Fallback to normal calibration if fast MSR calibration fails
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%!s(int64=11) %!d(string=hai) anos |
 H. Peter Anvin
|
ca1e631c3a
x86, tsc, apic: Unbreak static (MSR) calibration when CONFIG_X86_LOCAL_APIC=n
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%!s(int64=11) %!d(string=hai) anos |
 Bin Gao
|
7da7c15613
x86, tsc: Add static (MSR) TSC calibration on Intel Atom SoCs
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%!s(int64=11) %!d(string=hai) anos |
