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@@ -76,9 +76,10 @@ static int match_cpu(u8 family, u8 model)
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(freq_desc_tables[cpu_index].freqs[freq_id])
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/*
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- * Do MSR calibration only for known/supported CPUs.
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+ * MSR-based CPU/TSC frequency discovery for certain CPUs.
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*
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- * Returns the calibration value or 0 if MSR calibration failed.
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+ * Set global "lapic_timer_frequency" to bus_clock_cycles/jiffy
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+ * Return processor base frequency in KHz, or 0 on failure.
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*/
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unsigned long try_msr_calibrate_tsc(void)
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{
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@@ -100,31 +101,17 @@ unsigned long try_msr_calibrate_tsc(void)
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rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
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ratio = (hi >> 8) & 0x1f;
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}
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- pr_info("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
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-
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- if (!ratio)
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- goto fail;
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/* Get FSB FREQ ID */
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rdmsr(MSR_FSB_FREQ, lo, hi);
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freq_id = lo & 0x7;
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freq = id_to_freq(cpu_index, freq_id);
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- pr_info("Resolved frequency ID: %u, frequency: %u KHz\n",
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- freq_id, freq);
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- if (!freq)
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- goto fail;
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/* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
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res = freq * ratio;
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- pr_info("TSC runs at %lu KHz\n", res);
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#ifdef CONFIG_X86_LOCAL_APIC
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lapic_timer_frequency = (freq * 1000) / HZ;
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- pr_info("lapic_timer_frequency = %d\n", lapic_timer_frequency);
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#endif
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return res;
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-
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-fail:
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- pr_warn("Fast TSC calibration using MSR failed\n");
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- return 0;
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}
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