 Paul Burton
|
1091bfa20b
MIPS: Add P6600 cases to CPU switch statements
|
%!s(int64=9) %!d(string=hai) anos |
 Govindraj Raja
|
56fa81fc9a
MIPS: scache: Fix scache init with invalid line size.
|
%!s(int64=9) %!d(string=hai) anos |
|
Paul Burton
|
3af5a67c86
MIPS: Fix early CM probing
|
%!s(int64=9) %!d(string=hai) anos |
|
Paul Burton
|
4d03551692
MIPS: Enable L2 prefetching for CM >= 2.5
|
%!s(int64=10) %!d(string=hai) anos |
 Andrzej Hajda
|
05513992c6
MIPS: Remove invalid check
|
%!s(int64=10) %!d(string=hai) anos |
 Markos Chandras
|
c014d164f2
MIPS: Add platform callback before initializing the L2 cache
|
%!s(int64=10) %!d(string=hai) anos |
|
Paul Burton
|
7d53e9c4cd
MIPS: CM3: Add support for CM3 L2 cache.
|
%!s(int64=10) %!d(string=hai) anos |
|
Markos Chandras
|
b5ad2c2193
MIPS: mm: scache: Add secondary cache support for MIPS R6 cores
|
%!s(int64=10) %!d(string=hai) anos |
 Leonid Yegoshin
|
4695089f03
MIPS: Add cases for CPU_QEMU_GENERIC
|
%!s(int64=10) %!d(string=hai) anos |
 James Hogan
|
aced4cbd6e
MIPS: Add cases for CPU_P5600
|
%!s(int64=11) %!d(string=hai) anos |
 Steven J. Hill
|
442e14a2c5
MIPS: Add 1074K CPU support explicitly.
|
%!s(int64=11) %!d(string=hai) anos |
|
Leonid Yegoshin
|
26ab96dfa9
MIPS: Add support for interAptiv cores
|
%!s(int64=11) %!d(string=hai) anos |
|
Leonid Yegoshin
|
708ac4b870
MIPS: Add support for the proAptiv cores
|
%!s(int64=11) %!d(string=hai) anos |
 Ralf Baechle
|
69f24d1784
MIPS: Optimize current_cpu_type() for better code.
|
%!s(int64=12) %!d(string=hai) anos |
 Paul Gortmaker
|
078a55fc82
MIPS: Delete __cpuinit/__CPUINIT usage from MIPS code
|
%!s(int64=12) %!d(string=hai) anos |
 Deng-Cheng Zhu
|
adb3789264
MIPS: Fix ISA level which causes secondary cache init bypassing and more
|
%!s(int64=12) %!d(string=hai) anos |
 David Howells
|
b81947c646
Disintegrate asm/system.h for MIPS
|
%!s(int64=13) %!d(string=hai) anos |
 Kevin Cernekee
|
081d835fa4
MIPS: Fix build errors in sc-mips.c
|
%!s(int64=14) %!d(string=hai) anos |
|
Kevin Cernekee
|
ea31a6b203
MIPS: Honor L2 bypass bit
|
%!s(int64=15) %!d(string=hai) anos |
|
Kevin Cernekee
|
96983ffefc
MIPS: MIPSxx SC: Avoid destructive invalidation on partial L2 cachelines.
|
%!s(int64=16) %!d(string=hai) anos |
|
Ralf Baechle
|
234fcd1484
[MIPS] Fix loads of section missmatches
|
%!s(int64=17) %!d(string=hai) anos |
|
Ralf Baechle
|
49a89efbbb
[MIPS] Fix "no space between function name and open parenthesis" warnings.
|
%!s(int64=18) %!d(string=hai) anos |
 Atsushi Nemoto
|
a2c2bc4b26
[MIPS] MIPS32/MIPS64 S-cache fix and cleanup
|
%!s(int64=19) %!d(string=hai) anos |
 Chris Dearman
|
9318c51acd
[MIPS] MIPS32/MIPS64 secondary cache management
|
%!s(int64=19) %!d(string=hai) anos |
