 Dmitry Osipenko
|
4d48edb3c3
ARM: tegra20: Store CPU "resettable" status in IRAM
|
10 years ago |
|
Dmitry Osipenko
|
e4a680099a
ARM: tegra: Re-add removed SoC id macro to tegra_resume()
|
11 years ago |
 Thierry Reding
|
304664eab9
ARM: tegra: Use a function to get the chip ID
|
11 years ago |
|
Thierry Reding
|
a0524acc94
ARM: tegra: Sort includes alphabetically
|
11 years ago |
 Russell King
|
b16cee70fd
ARM: l2c: tegra: convert to common l2c310 early resume functionality
|
11 years ago |
 Joseph Lo
|
d127e9c5c5
ARM: tegra: make tegra_resume can work with current and later chips
|
12 years ago |
|
Joseph Lo
|
5b795d051c
ARM: tegra: add common resume handling code for LP1 resuming
|
12 years ago |
|
Joseph Lo
|
2f5aaa3d27
ARM: tegra: set up the correct L2 data RAM latency for Cortex-A15
|
12 years ago |
|
Joseph Lo
|
c04c77540a
ARM: tegra: do v7_invalidate_l1 only when CPU is Cortex-A9
|
12 years ago |
|
Joseph Lo
|
af7f322ea8
ARM: tegra: remove ifdef in the tegra_resume
|
12 years ago |
|
Joseph Lo
|
33d5c01915
ARM: tegra114: add CPU hotplug support
|
12 years ago |
|
Joseph Lo
|
ecc4d9da21
ARM: tegra: make tegra_resume can work for Tegra114
|
12 years ago |
|
Joseph Lo
|
4b3e2edacf
ARM: tegra: add an assembly marco to check Tegra SoC ID
|
12 years ago |
|
Joseph Lo
|
a65dc10ffa
ARM: tegra: fix relocation truncated error when THUMB2_KERNEL enabled
|
12 years ago |
|
Joseph Lo
|
b095ae2b9f
ARM: tegra: don't unlock MMIO access to DBGLAR
|
12 years ago |
 Stephen Warren
|
c34f30e588
ARM: tegra: add CPU errata WARs to Tegra reset handler
|
12 years ago |
|
Joseph Lo
|
9e32366fe5
ARM: tegra: make device can run on UP
|
12 years ago |
