 Ville Syrjälä
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18a8067c57
drm/i915: Assert the dbuf is enabled when disabling DC5/6
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9 years ago |
|
Ville Syrjälä
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342be926e0
drm/i915: Replace bxt_verify_cdclk_state() with a more generic cdclk check
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9 years ago |
|
Ville Syrjälä
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70c2c18406
drm/i915: Move SKL+ DBUF enable/disable to display core init/uninit
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9 years ago |
|
Ville Syrjälä
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9f7eb31af2
drm/i915: Unify SKL cdclk init paths
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9 years ago |
|
Ville Syrjälä
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19ab4ed329
drm/i915: Update RAWCLK_FREQ register on VLV/CHV
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9 years ago |
 Imre Deak
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f62c79b33f
drm/i915/bxt: Enable DC5 during runtime resume
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9 years ago |
|
Imre Deak
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da2f41d107
drm/i915/bxt: Sanitize DC state tracking during system resume
|
9 years ago |
|
Imre Deak
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80dbe9973a
drm/i915/kbl: Don't WARN for expected secondary MISC IO power well request
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9 years ago |
|
Ville Syrjälä
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9d0996b590
drm/i915: Define HSW/BDW display power domains the right way up
|
9 years ago |
|
Ville Syrjälä
|
465ac0c6b6
drm/i915: Define VLV/CHV display power well domains properly
|
9 years ago |
|
Ville Syrjälä
|
998bd66a9d
drm/i915: Set .domains=POWER_DOMAIN_MASK for the always-on well
|
9 years ago |
|
Imre Deak
|
f74ed08d55
drm/i915/gen9: Fix runtime PM refcounting in case DMC firmware isn't loaded
|
9 years ago |
|
Imre Deak
|
5f304c8736
drm/i915/kbl: Reset secondary power well requests left on by DMC/KVMR
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9 years ago |
|
Imre Deak
|
f11f4e9524
Revert "drm/i915/bxt: Disable power well support"
|
9 years ago |
|
Imre Deak
|
adc7f04bfd
drm/i915/bxt: Add HW state verification for DDI PHY and CDCLK
|
9 years ago |
|
Imre Deak
|
d7d7c9ee69
drm/i915/bxt: Don't toggle power well 1 on-demand
|
9 years ago |
|
Imre Deak
|
443a93ac89
drm/i915/skl: Unexport skl_pw1_misc_io_init
|
9 years ago |
|
Imre Deak
|
bfcdabe888
drm/i915/gen9: Fix DMC/DC state asserts
|
9 years ago |
|
Imre Deak
|
1d963afae1
drm/i915/gen9: Make power well disabling synchronous
|
9 years ago |
|
Imre Deak
|
c6782b76d3
drm/i915/gen9: Reset secondary power well requests left on by DMC/KVMR
|
9 years ago |
|
Ville Syrjälä
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766078df43
drm/i915: Move vlv_init_display_clock_gating() to the display power well
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9 years ago |
 Joonas Lahtinen
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2d1fe07340
drm/i915: Do not use {HAS_*, IS_*, INTEL_INFO}(dev_priv->dev)
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9 years ago |
 Jani Nikula
|
4d1de97568
drm/i915/bxt: add dsi transcoders
|
9 years ago |
|
Jani Nikula
|
acad889f9e
drm/i915/bxt: add missing DSI power domain to power well 1
|
9 years ago |
|
Imre Deak
|
2abc525bf5
drm/i915/gen9: Fix DMC firmware initialization
|
9 years ago |
|
Imre Deak
|
5b773eb422
drm/i915/gen9: Remove state asserts when disabling DC states
|
9 years ago |
|
Imre Deak
|
66e2c4c39c
drm/i915/gen9: Disable DC states if power well support is disabled
|
9 years ago |
|
Imre Deak
|
a37baf3b83
drm/i915/gen9: Sanitize handling of allowed DC states
|
9 years ago |
|
Imre Deak
|
2622d79bd9
drm/i915/skl: Fix power domain suspend sequence
|
9 years ago |
 Chris Wilson
|
135dc79efb
drm/i915: Balance assert_rpm_wakelock_held() for !IS_ENABLED(CONFIG_PM)
|
9 years ago |
