 Linus Torvalds
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23b7776290
Merge branch 'sched-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
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10 years ago |
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Linus Torvalds
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6bc4c3ad36
Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
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10 years ago |
 Palik, Imre
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2c33645d36
perf/x86: Honor the architectural performance monitoring version
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10 years ago |
 Andi Kleen
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4b36f1a413
perf/x86: Add more Broadwell model numbers
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10 years ago |
 Yan, Zheng
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9c964efa43
perf/x86/intel: Drain the PEBS buffer during context switches
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10 years ago |
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Yan, Zheng
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3569c0d7c5
perf/x86/intel: Implement batched PEBS interrupt handling (large PEBS interrupt threshold)
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10 years ago |
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Yan, Zheng
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851559e35f
perf/x86/intel: Use the PEBS auto reload mechanism when possible
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10 years ago |
 Bartosz Golaszewski
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06931e6224
sched/topology: Rename topology_thread_cpumask() to topology_sibling_cpumask()
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10 years ago |
 Peter Zijlstra
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ba040653b4
perf/x86/intel: Simplify put_exclusive_constraints()
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10 years ago |
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Peter Zijlstra
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43ef205bde
perf/x86/intel: Remove intel_excl_states::init_state
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10 years ago |
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Peter Zijlstra
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1fe684e349
perf/x86/intel: Remove pointless tests
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10 years ago |
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Peter Zijlstra
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0c41e756b9
perf/x86/intel: Clean up intel_commit_scheduling() placement
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10 years ago |
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Peter Zijlstra
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17186ccda3
perf/x86/intel: Make WARN()ings consistent
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10 years ago |
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Peter Zijlstra
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aaf932e816
perf/x86/intel: Simplify the dynamic constraint code somewhat
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10 years ago |
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Peter Zijlstra
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b32ed7f5de
perf/x86/intel: Add lockdep assert
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10 years ago |
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Peter Zijlstra
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1c565833ac
perf/x86/intel: Correct local vs remote sibling state
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10 years ago |
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Peter Zijlstra
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cc1790cf54
perf/x86: Improve HT workaround GP counter constraint
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10 years ago |
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Peter Zijlstra
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b371b59431
perf/x86: Fix event/group validation
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10 years ago |
 Kan Liang
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6d37405635
perf/x86/intel: Fix SLM cache event list
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10 years ago |
 Jiri Olsa
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3b6e042188
perf/x86/intel: Add cpu_(prepare|starting|dying) for core_pmu
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10 years ago |
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Kan Liang
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78d504bcd7
perf/x86/intel: Add Broadwell support for the LBR callstack
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10 years ago |
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Andi Kleen
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1a78d93750
perf/x86/intel: Streamline LBR MSR handling in PMI
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10 years ago |
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Andi Kleen
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8882edf735
perf/x86/intel: Reset more state in PMU reset
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10 years ago |
 Stephane Eranian
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b37609c30e
perf/x86/intel: Make the HT bug workaround conditional on HT enabled
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10 years ago |
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Stephane Eranian
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c02cdbf60b
perf/x86/intel: Limit to half counters when the HT workaround is enabled, to avoid exclusive mode starvation
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10 years ago |
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Stephane Eranian
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a90738c2cb
perf/x86/intel: Fix intel_get_event_constraints() for dynamic constraints
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10 years ago |
 Maria Dimakopoulou
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93fcf72cc0
perf/x86/intel: Enforce HT bug workaround for SNB/IVB/HSW
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10 years ago |
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Maria Dimakopoulou
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e979121b1b
perf/x86/intel: Implement cross-HT corruption bug workaround
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10 years ago |
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Maria Dimakopoulou
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6f6539cad9
perf/x86/intel: Add cross-HT counter exclusion infrastructure
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10 years ago |
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Stephane Eranian
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79cba82244
perf/x86: Add 'index' param to get_event_constraint() callback
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10 years ago |
