 Maxime Ripard
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efb3184c08
clk: sun6i: Protect SDRAM gating bit
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11 years ago |
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Maxime Ripard
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2df73f40dc
clk: sun6i: Protect CPU clock
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11 years ago |
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Maxime Ripard
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134a6690a3
clk: sunxi: Rework clock protection code
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11 years ago |
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Maxime Ripard
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59cb10e32a
clk: sunxi: Move the GMAC clock to a file of its own
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11 years ago |
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Maxime Ripard
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ff01df28e5
clk: sunxi: Move the 24M oscillator to a file of its own
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11 years ago |
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Maxime Ripard
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2c6fba1038
clk: sunxi: Remove calls to clk_put
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11 years ago |
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Maxime Ripard
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e0e7943c55
clk: sunxi: Implement A31 USB clock
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11 years ago |
 Linus Torvalds
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1a5700bc2d
Merge tag 'clk-for-linus-3.16' of git://git.linaro.org/people/mike.turquette/linux into next
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11 years ago |
 Rob Herring
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83221923fc
clk: sunxi: fix function type for CLK_OF_DECLARE
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11 years ago |
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Rob Herring
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cb7d5f425f
clk: sunxi: avoid double DT matching
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11 years ago |
 Hans de Goede
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a97181adf1
clk: sunxi: Fixup clk_sunxi_mmc_phase_control to take a clk rather then a hw_clk
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11 years ago |
 Emilio López
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95713978b0
clk: sunxi: Implement MMC phase control
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11 years ago |
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Emilio López
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9ce71ca10f
clk: sunxi: fix thinko in comment
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11 years ago |
|
Emilio López
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2226013972
clk: sunxi: fix some calculations
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11 years ago |
|
Emilio López
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5a8ddf2682
clk: sunxi: fix A20 PLL4 calculation
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11 years ago |
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Maxime Ripard
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fd1b22f6fb
clk: sunxi: Add new clock compatibles
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11 years ago |
 Chen-Yu Tsai
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e4c6d6c11b
clk: sunxi: Add Allwinner A20/A31 GMAC clock unit
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11 years ago |
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Maxime Ripard
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92ef67c53a
clk: sunxi: Add support for PLL6 on the A31
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11 years ago |
 Roman Byshko
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5abdbf2f49
clk: sunxi: Add USB clock register defintions
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11 years ago |
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Hans de Goede
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cfb0086dca
clk: sunxi: Add support for USB clock-register reset bits
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11 years ago |
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Chen-Yu Tsai
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97e36b3ce3
clk: sunxi: get divs parent clock name from parent factor clock
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11 years ago |
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Chen-Yu Tsai
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667f542db5
clk: sunxi: add names for pll5, pll6 parent clocks to factors_data
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11 years ago |
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Chen-Yu Tsai
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f64111ebaf
clk: sunxi: add clock-output-names dt property support
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11 years ago |
|
Emilio López
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d1933689aa
clk: sunxi: fix overflow when setting up divided factors
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11 years ago |
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Chen-Yu Tsai
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6f86341726
clk: sunxi: Allwinner A20 output clock support
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11 years ago |
|
Emilio López
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76192dc887
clk: sunxi: support better factor DT nodes
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11 years ago |
|
Emilio López
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7551769a22
clk: sunxi: mod0 support
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11 years ago |
|
Emilio López
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d584c1331d
clk: sunxi: add PLL5 and PLL6 support
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11 years ago |
|
Emilio López
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5f4e0be3a7
clk: sunxi: make factors_clk_setup return the clock it registers
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11 years ago |
|
Emilio López
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d838ff33ec
clk: sunxi: add gating support to PLL1
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11 years ago |
