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@@ -32,7 +32,7 @@
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#define NETNEXT_VERSION "08"
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/* Information for net */
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-#define NET_VERSION "5"
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+#define NET_VERSION "6"
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#define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
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#define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
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@@ -2552,6 +2552,77 @@ static void r8152_aldps_en(struct r8152 *tp, bool enable)
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}
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}
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+static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
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+{
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+ ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
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+ ocp_reg_write(tp, OCP_EEE_DATA, reg);
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+ ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
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+}
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+
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+static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
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+{
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+ u16 data;
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+
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+ r8152_mmd_indirect(tp, dev, reg);
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+ data = ocp_reg_read(tp, OCP_EEE_DATA);
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+ ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
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+
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+ return data;
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+}
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+
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+static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
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+{
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+ r8152_mmd_indirect(tp, dev, reg);
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+ ocp_reg_write(tp, OCP_EEE_DATA, data);
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+ ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
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+}
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+
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+static void r8152_eee_en(struct r8152 *tp, bool enable)
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+{
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+ u16 config1, config2, config3;
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+ u32 ocp_data;
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+
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+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
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+ config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
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+ config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
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+ config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
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+
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+ if (enable) {
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+ ocp_data |= EEE_RX_EN | EEE_TX_EN;
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+ config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
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+ config1 |= sd_rise_time(1);
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+ config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
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+ config3 |= fast_snr(42);
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+ } else {
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+ ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
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+ config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
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+ RX_QUIET_EN);
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+ config1 |= sd_rise_time(7);
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+ config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
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+ config3 |= fast_snr(511);
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+ }
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+
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+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
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+ ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
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+ ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
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+ ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
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+}
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+
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+static void r8152b_enable_eee(struct r8152 *tp)
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+{
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+ r8152_eee_en(tp, true);
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+ r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
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+}
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+
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+static void r8152b_enable_fc(struct r8152 *tp)
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+{
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+ u16 anar;
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+
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+ anar = r8152_mdio_read(tp, MII_ADVERTISE);
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+ anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
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+ r8152_mdio_write(tp, MII_ADVERTISE, anar);
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+}
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+
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static void rtl8152_disable(struct r8152 *tp)
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{
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r8152_aldps_en(tp, false);
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@@ -2561,13 +2632,9 @@ static void rtl8152_disable(struct r8152 *tp)
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static void r8152b_hw_phy_cfg(struct r8152 *tp)
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{
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- u16 data;
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-
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- data = r8152_mdio_read(tp, MII_BMCR);
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- if (data & BMCR_PDOWN) {
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- data &= ~BMCR_PDOWN;
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- r8152_mdio_write(tp, MII_BMCR, data);
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- }
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+ r8152b_enable_eee(tp);
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+ r8152_aldps_en(tp, true);
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+ r8152b_enable_fc(tp);
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set_bit(PHY_RESET, &tp->flags);
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}
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@@ -2701,20 +2768,52 @@ static void r8152b_enter_oob(struct r8152 *tp)
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ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
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}
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+static void r8153_aldps_en(struct r8152 *tp, bool enable)
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+{
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+ u16 data;
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+
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+ data = ocp_reg_read(tp, OCP_POWER_CFG);
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+ if (enable) {
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+ data |= EN_ALDPS;
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+ ocp_reg_write(tp, OCP_POWER_CFG, data);
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+ } else {
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+ data &= ~EN_ALDPS;
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+ ocp_reg_write(tp, OCP_POWER_CFG, data);
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+ msleep(20);
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+ }
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+}
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+
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+static void r8153_eee_en(struct r8152 *tp, bool enable)
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+{
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+ u32 ocp_data;
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+ u16 config;
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+
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+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
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+ config = ocp_reg_read(tp, OCP_EEE_CFG);
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+
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+ if (enable) {
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+ ocp_data |= EEE_RX_EN | EEE_TX_EN;
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+ config |= EEE10_EN;
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+ } else {
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+ ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
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+ config &= ~EEE10_EN;
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+ }
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+
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+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
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+ ocp_reg_write(tp, OCP_EEE_CFG, config);
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+}
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+
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static void r8153_hw_phy_cfg(struct r8152 *tp)
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{
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u32 ocp_data;
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u16 data;
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- if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
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- tp->version == RTL_VER_05)
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- ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
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+ /* disable ALDPS before updating the PHY parameters */
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+ r8153_aldps_en(tp, false);
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- data = r8152_mdio_read(tp, MII_BMCR);
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- if (data & BMCR_PDOWN) {
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- data &= ~BMCR_PDOWN;
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- r8152_mdio_write(tp, MII_BMCR, data);
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- }
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+ /* disable EEE before updating the PHY parameters */
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+ r8153_eee_en(tp, false);
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+ ocp_reg_write(tp, OCP_EEE_ADV, 0);
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if (tp->version == RTL_VER_03) {
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data = ocp_reg_read(tp, OCP_EEE_CFG);
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@@ -2745,6 +2844,12 @@ static void r8153_hw_phy_cfg(struct r8152 *tp)
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sram_write(tp, SRAM_10M_AMP1, 0x00af);
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sram_write(tp, SRAM_10M_AMP2, 0x0208);
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+ r8153_eee_en(tp, true);
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+ ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
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+
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+ r8153_aldps_en(tp, true);
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+ r8152b_enable_fc(tp);
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+
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set_bit(PHY_RESET, &tp->flags);
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}
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@@ -2866,21 +2971,6 @@ static void r8153_enter_oob(struct r8152 *tp)
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ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
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}
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-static void r8153_aldps_en(struct r8152 *tp, bool enable)
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-{
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- u16 data;
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-
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- data = ocp_reg_read(tp, OCP_POWER_CFG);
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- if (enable) {
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- data |= EN_ALDPS;
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- ocp_reg_write(tp, OCP_POWER_CFG, data);
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- } else {
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- data &= ~EN_ALDPS;
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- ocp_reg_write(tp, OCP_POWER_CFG, data);
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- msleep(20);
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- }
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-}
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-
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static void rtl8153_disable(struct r8152 *tp)
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{
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r8153_aldps_en(tp, false);
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@@ -3246,103 +3336,6 @@ static int rtl8152_close(struct net_device *netdev)
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return res;
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}
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-static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
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-{
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- ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
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- ocp_reg_write(tp, OCP_EEE_DATA, reg);
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- ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
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-}
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-
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-static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
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-{
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- u16 data;
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-
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- r8152_mmd_indirect(tp, dev, reg);
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- data = ocp_reg_read(tp, OCP_EEE_DATA);
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- ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
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-
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- return data;
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-}
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-
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-static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
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-{
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- r8152_mmd_indirect(tp, dev, reg);
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- ocp_reg_write(tp, OCP_EEE_DATA, data);
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- ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
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-}
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-
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-static void r8152_eee_en(struct r8152 *tp, bool enable)
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-{
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- u16 config1, config2, config3;
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- u32 ocp_data;
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-
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- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
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- config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
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- config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
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- config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
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-
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- if (enable) {
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- ocp_data |= EEE_RX_EN | EEE_TX_EN;
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- config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
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- config1 |= sd_rise_time(1);
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- config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
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- config3 |= fast_snr(42);
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- } else {
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- ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
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- config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
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- RX_QUIET_EN);
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- config1 |= sd_rise_time(7);
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- config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
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- config3 |= fast_snr(511);
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- }
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-
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- ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
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- ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
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- ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
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- ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
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-}
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-
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-static void r8152b_enable_eee(struct r8152 *tp)
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-{
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- r8152_eee_en(tp, true);
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- r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
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-}
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-
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-static void r8153_eee_en(struct r8152 *tp, bool enable)
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-{
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- u32 ocp_data;
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- u16 config;
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-
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- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
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- config = ocp_reg_read(tp, OCP_EEE_CFG);
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-
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- if (enable) {
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- ocp_data |= EEE_RX_EN | EEE_TX_EN;
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- config |= EEE10_EN;
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- } else {
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- ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
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- config &= ~EEE10_EN;
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- }
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-
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- ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
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- ocp_reg_write(tp, OCP_EEE_CFG, config);
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-}
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-
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-static void r8153_enable_eee(struct r8152 *tp)
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-{
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- r8153_eee_en(tp, true);
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- ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
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-}
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-
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-static void r8152b_enable_fc(struct r8152 *tp)
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-{
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- u16 anar;
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-
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- anar = r8152_mdio_read(tp, MII_ADVERTISE);
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- anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
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- r8152_mdio_write(tp, MII_ADVERTISE, anar);
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-}
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-
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static void rtl_tally_reset(struct r8152 *tp)
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{
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u32 ocp_data;
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@@ -3355,10 +3348,17 @@ static void rtl_tally_reset(struct r8152 *tp)
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static void r8152b_init(struct r8152 *tp)
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{
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u32 ocp_data;
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+ u16 data;
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if (test_bit(RTL8152_UNPLUG, &tp->flags))
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return;
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+ data = r8152_mdio_read(tp, MII_BMCR);
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+ if (data & BMCR_PDOWN) {
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+ data &= ~BMCR_PDOWN;
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+ r8152_mdio_write(tp, MII_BMCR, data);
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+ }
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+
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r8152_aldps_en(tp, false);
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if (tp->version == RTL_VER_01) {
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@@ -3380,9 +3380,6 @@ static void r8152b_init(struct r8152 *tp)
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SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
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ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
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- r8152b_enable_eee(tp);
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- r8152_aldps_en(tp, true);
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- r8152b_enable_fc(tp);
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rtl_tally_reset(tp);
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/* enable rx aggregation */
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@@ -3394,12 +3391,12 @@ static void r8152b_init(struct r8152 *tp)
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static void r8153_init(struct r8152 *tp)
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{
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u32 ocp_data;
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+ u16 data;
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int i;
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if (test_bit(RTL8152_UNPLUG, &tp->flags))
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return;
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- r8153_aldps_en(tp, false);
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r8153_u1u2en(tp, false);
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for (i = 0; i < 500; i++) {
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@@ -3416,6 +3413,23 @@ static void r8153_init(struct r8152 *tp)
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msleep(20);
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}
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+ if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
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+ tp->version == RTL_VER_05)
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+ ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
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+
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+ data = r8152_mdio_read(tp, MII_BMCR);
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+ if (data & BMCR_PDOWN) {
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+ data &= ~BMCR_PDOWN;
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+ r8152_mdio_write(tp, MII_BMCR, data);
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+ }
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+
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+ for (i = 0; i < 500; i++) {
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+ ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
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+ if (ocp_data == PHY_STAT_LAN_ON)
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+ break;
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+ msleep(20);
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+ }
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+
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usb_disable_lpm(tp->udev);
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r8153_u2p3en(tp, false);
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@@ -3483,9 +3497,6 @@ static void r8153_init(struct r8152 *tp)
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ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
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ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
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- r8153_enable_eee(tp);
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- r8153_aldps_en(tp, true);
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- r8152b_enable_fc(tp);
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rtl_tally_reset(tp);
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r8153_u2p3en(tp, true);
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}
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