qeth_core_main.c 171 KB

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  1. /*
  2. * Copyright IBM Corp. 2007, 2009
  3. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  4. * Frank Pavlic <fpavlic@de.ibm.com>,
  5. * Thomas Spatzier <tspat@de.ibm.com>,
  6. * Frank Blaschka <frank.blaschka@de.ibm.com>
  7. */
  8. #define KMSG_COMPONENT "qeth"
  9. #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
  10. #include <linux/module.h>
  11. #include <linux/moduleparam.h>
  12. #include <linux/string.h>
  13. #include <linux/errno.h>
  14. #include <linux/kernel.h>
  15. #include <linux/ip.h>
  16. #include <linux/tcp.h>
  17. #include <linux/mii.h>
  18. #include <linux/kthread.h>
  19. #include <linux/slab.h>
  20. #include <net/iucv/af_iucv.h>
  21. #include <net/dsfield.h>
  22. #include <asm/ebcdic.h>
  23. #include <asm/chpid.h>
  24. #include <asm/io.h>
  25. #include <asm/sysinfo.h>
  26. #include <asm/compat.h>
  27. #include "qeth_core.h"
  28. struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
  29. /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
  30. /* N P A M L V H */
  31. [QETH_DBF_SETUP] = {"qeth_setup",
  32. 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
  33. [QETH_DBF_MSG] = {"qeth_msg", 8, 1, 11 * sizeof(long), 3,
  34. &debug_sprintf_view, NULL},
  35. [QETH_DBF_CTRL] = {"qeth_control",
  36. 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
  37. };
  38. EXPORT_SYMBOL_GPL(qeth_dbf);
  39. struct qeth_card_list_struct qeth_core_card_list;
  40. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  41. struct kmem_cache *qeth_core_header_cache;
  42. EXPORT_SYMBOL_GPL(qeth_core_header_cache);
  43. static struct kmem_cache *qeth_qdio_outbuf_cache;
  44. static struct device *qeth_core_root_dev;
  45. static unsigned int known_devices[][6] = QETH_MODELLIST_ARRAY;
  46. static struct lock_class_key qdio_out_skb_queue_key;
  47. static struct mutex qeth_mod_mutex;
  48. static void qeth_send_control_data_cb(struct qeth_channel *,
  49. struct qeth_cmd_buffer *);
  50. static int qeth_issue_next_read(struct qeth_card *);
  51. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  52. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  53. static void qeth_free_buffer_pool(struct qeth_card *);
  54. static int qeth_qdio_establish(struct qeth_card *);
  55. static void qeth_free_qdio_buffers(struct qeth_card *);
  56. static void qeth_notify_skbs(struct qeth_qdio_out_q *queue,
  57. struct qeth_qdio_out_buffer *buf,
  58. enum iucv_tx_notify notification);
  59. static void qeth_release_skbs(struct qeth_qdio_out_buffer *buf);
  60. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  61. struct qeth_qdio_out_buffer *buf,
  62. enum qeth_qdio_buffer_states newbufstate);
  63. static int qeth_init_qdio_out_buf(struct qeth_qdio_out_q *, int);
  64. struct workqueue_struct *qeth_wq;
  65. EXPORT_SYMBOL_GPL(qeth_wq);
  66. int qeth_card_hw_is_reachable(struct qeth_card *card)
  67. {
  68. return (card->state == CARD_STATE_SOFTSETUP) ||
  69. (card->state == CARD_STATE_UP);
  70. }
  71. EXPORT_SYMBOL_GPL(qeth_card_hw_is_reachable);
  72. static void qeth_close_dev_handler(struct work_struct *work)
  73. {
  74. struct qeth_card *card;
  75. card = container_of(work, struct qeth_card, close_dev_work);
  76. QETH_CARD_TEXT(card, 2, "cldevhdl");
  77. rtnl_lock();
  78. dev_close(card->dev);
  79. rtnl_unlock();
  80. ccwgroup_set_offline(card->gdev);
  81. }
  82. void qeth_close_dev(struct qeth_card *card)
  83. {
  84. QETH_CARD_TEXT(card, 2, "cldevsubm");
  85. queue_work(qeth_wq, &card->close_dev_work);
  86. }
  87. EXPORT_SYMBOL_GPL(qeth_close_dev);
  88. static inline const char *qeth_get_cardname(struct qeth_card *card)
  89. {
  90. if (card->info.guestlan) {
  91. switch (card->info.type) {
  92. case QETH_CARD_TYPE_OSD:
  93. return " Virtual NIC QDIO";
  94. case QETH_CARD_TYPE_IQD:
  95. return " Virtual NIC Hiper";
  96. case QETH_CARD_TYPE_OSM:
  97. return " Virtual NIC QDIO - OSM";
  98. case QETH_CARD_TYPE_OSX:
  99. return " Virtual NIC QDIO - OSX";
  100. default:
  101. return " unknown";
  102. }
  103. } else {
  104. switch (card->info.type) {
  105. case QETH_CARD_TYPE_OSD:
  106. return " OSD Express";
  107. case QETH_CARD_TYPE_IQD:
  108. return " HiperSockets";
  109. case QETH_CARD_TYPE_OSN:
  110. return " OSN QDIO";
  111. case QETH_CARD_TYPE_OSM:
  112. return " OSM QDIO";
  113. case QETH_CARD_TYPE_OSX:
  114. return " OSX QDIO";
  115. default:
  116. return " unknown";
  117. }
  118. }
  119. return " n/a";
  120. }
  121. /* max length to be returned: 14 */
  122. const char *qeth_get_cardname_short(struct qeth_card *card)
  123. {
  124. if (card->info.guestlan) {
  125. switch (card->info.type) {
  126. case QETH_CARD_TYPE_OSD:
  127. return "Virt.NIC QDIO";
  128. case QETH_CARD_TYPE_IQD:
  129. return "Virt.NIC Hiper";
  130. case QETH_CARD_TYPE_OSM:
  131. return "Virt.NIC OSM";
  132. case QETH_CARD_TYPE_OSX:
  133. return "Virt.NIC OSX";
  134. default:
  135. return "unknown";
  136. }
  137. } else {
  138. switch (card->info.type) {
  139. case QETH_CARD_TYPE_OSD:
  140. switch (card->info.link_type) {
  141. case QETH_LINK_TYPE_FAST_ETH:
  142. return "OSD_100";
  143. case QETH_LINK_TYPE_HSTR:
  144. return "HSTR";
  145. case QETH_LINK_TYPE_GBIT_ETH:
  146. return "OSD_1000";
  147. case QETH_LINK_TYPE_10GBIT_ETH:
  148. return "OSD_10GIG";
  149. case QETH_LINK_TYPE_LANE_ETH100:
  150. return "OSD_FE_LANE";
  151. case QETH_LINK_TYPE_LANE_TR:
  152. return "OSD_TR_LANE";
  153. case QETH_LINK_TYPE_LANE_ETH1000:
  154. return "OSD_GbE_LANE";
  155. case QETH_LINK_TYPE_LANE:
  156. return "OSD_ATM_LANE";
  157. default:
  158. return "OSD_Express";
  159. }
  160. case QETH_CARD_TYPE_IQD:
  161. return "HiperSockets";
  162. case QETH_CARD_TYPE_OSN:
  163. return "OSN";
  164. case QETH_CARD_TYPE_OSM:
  165. return "OSM_1000";
  166. case QETH_CARD_TYPE_OSX:
  167. return "OSX_10GIG";
  168. default:
  169. return "unknown";
  170. }
  171. }
  172. return "n/a";
  173. }
  174. void qeth_set_recovery_task(struct qeth_card *card)
  175. {
  176. card->recovery_task = current;
  177. }
  178. EXPORT_SYMBOL_GPL(qeth_set_recovery_task);
  179. void qeth_clear_recovery_task(struct qeth_card *card)
  180. {
  181. card->recovery_task = NULL;
  182. }
  183. EXPORT_SYMBOL_GPL(qeth_clear_recovery_task);
  184. static bool qeth_is_recovery_task(const struct qeth_card *card)
  185. {
  186. return card->recovery_task == current;
  187. }
  188. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  189. int clear_start_mask)
  190. {
  191. unsigned long flags;
  192. spin_lock_irqsave(&card->thread_mask_lock, flags);
  193. card->thread_allowed_mask = threads;
  194. if (clear_start_mask)
  195. card->thread_start_mask &= threads;
  196. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  197. wake_up(&card->wait_q);
  198. }
  199. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  200. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  201. {
  202. unsigned long flags;
  203. int rc = 0;
  204. spin_lock_irqsave(&card->thread_mask_lock, flags);
  205. rc = (card->thread_running_mask & threads);
  206. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  207. return rc;
  208. }
  209. EXPORT_SYMBOL_GPL(qeth_threads_running);
  210. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  211. {
  212. if (qeth_is_recovery_task(card))
  213. return 0;
  214. return wait_event_interruptible(card->wait_q,
  215. qeth_threads_running(card, threads) == 0);
  216. }
  217. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  218. void qeth_clear_working_pool_list(struct qeth_card *card)
  219. {
  220. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  221. QETH_CARD_TEXT(card, 5, "clwrklst");
  222. list_for_each_entry_safe(pool_entry, tmp,
  223. &card->qdio.in_buf_pool.entry_list, list){
  224. list_del(&pool_entry->list);
  225. }
  226. }
  227. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  228. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  229. {
  230. struct qeth_buffer_pool_entry *pool_entry;
  231. void *ptr;
  232. int i, j;
  233. QETH_CARD_TEXT(card, 5, "alocpool");
  234. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  235. pool_entry = kzalloc(sizeof(*pool_entry), GFP_KERNEL);
  236. if (!pool_entry) {
  237. qeth_free_buffer_pool(card);
  238. return -ENOMEM;
  239. }
  240. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  241. ptr = (void *) __get_free_page(GFP_KERNEL);
  242. if (!ptr) {
  243. while (j > 0)
  244. free_page((unsigned long)
  245. pool_entry->elements[--j]);
  246. kfree(pool_entry);
  247. qeth_free_buffer_pool(card);
  248. return -ENOMEM;
  249. }
  250. pool_entry->elements[j] = ptr;
  251. }
  252. list_add(&pool_entry->init_list,
  253. &card->qdio.init_pool.entry_list);
  254. }
  255. return 0;
  256. }
  257. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  258. {
  259. QETH_CARD_TEXT(card, 2, "realcbp");
  260. if ((card->state != CARD_STATE_DOWN) &&
  261. (card->state != CARD_STATE_RECOVER))
  262. return -EPERM;
  263. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  264. qeth_clear_working_pool_list(card);
  265. qeth_free_buffer_pool(card);
  266. card->qdio.in_buf_pool.buf_count = bufcnt;
  267. card->qdio.init_pool.buf_count = bufcnt;
  268. return qeth_alloc_buffer_pool(card);
  269. }
  270. EXPORT_SYMBOL_GPL(qeth_realloc_buffer_pool);
  271. static void qeth_free_qdio_queue(struct qeth_qdio_q *q)
  272. {
  273. if (!q)
  274. return;
  275. qdio_free_buffers(q->qdio_bufs, QDIO_MAX_BUFFERS_PER_Q);
  276. kfree(q);
  277. }
  278. static struct qeth_qdio_q *qeth_alloc_qdio_queue(void)
  279. {
  280. struct qeth_qdio_q *q = kzalloc(sizeof(*q), GFP_KERNEL);
  281. int i;
  282. if (!q)
  283. return NULL;
  284. if (qdio_alloc_buffers(q->qdio_bufs, QDIO_MAX_BUFFERS_PER_Q)) {
  285. kfree(q);
  286. return NULL;
  287. }
  288. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  289. q->bufs[i].buffer = q->qdio_bufs[i];
  290. QETH_DBF_HEX(SETUP, 2, &q, sizeof(void *));
  291. return q;
  292. }
  293. static inline int qeth_cq_init(struct qeth_card *card)
  294. {
  295. int rc;
  296. if (card->options.cq == QETH_CQ_ENABLED) {
  297. QETH_DBF_TEXT(SETUP, 2, "cqinit");
  298. qdio_reset_buffers(card->qdio.c_q->qdio_bufs,
  299. QDIO_MAX_BUFFERS_PER_Q);
  300. card->qdio.c_q->next_buf_to_init = 127;
  301. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT,
  302. card->qdio.no_in_queues - 1, 0,
  303. 127);
  304. if (rc) {
  305. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  306. goto out;
  307. }
  308. }
  309. rc = 0;
  310. out:
  311. return rc;
  312. }
  313. static inline int qeth_alloc_cq(struct qeth_card *card)
  314. {
  315. int rc;
  316. if (card->options.cq == QETH_CQ_ENABLED) {
  317. int i;
  318. struct qdio_outbuf_state *outbuf_states;
  319. QETH_DBF_TEXT(SETUP, 2, "cqon");
  320. card->qdio.c_q = qeth_alloc_qdio_queue();
  321. if (!card->qdio.c_q) {
  322. rc = -1;
  323. goto kmsg_out;
  324. }
  325. card->qdio.no_in_queues = 2;
  326. card->qdio.out_bufstates =
  327. kzalloc(card->qdio.no_out_queues *
  328. QDIO_MAX_BUFFERS_PER_Q *
  329. sizeof(struct qdio_outbuf_state), GFP_KERNEL);
  330. outbuf_states = card->qdio.out_bufstates;
  331. if (outbuf_states == NULL) {
  332. rc = -1;
  333. goto free_cq_out;
  334. }
  335. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  336. card->qdio.out_qs[i]->bufstates = outbuf_states;
  337. outbuf_states += QDIO_MAX_BUFFERS_PER_Q;
  338. }
  339. } else {
  340. QETH_DBF_TEXT(SETUP, 2, "nocq");
  341. card->qdio.c_q = NULL;
  342. card->qdio.no_in_queues = 1;
  343. }
  344. QETH_DBF_TEXT_(SETUP, 2, "iqc%d", card->qdio.no_in_queues);
  345. rc = 0;
  346. out:
  347. return rc;
  348. free_cq_out:
  349. qeth_free_qdio_queue(card->qdio.c_q);
  350. card->qdio.c_q = NULL;
  351. kmsg_out:
  352. dev_err(&card->gdev->dev, "Failed to create completion queue\n");
  353. goto out;
  354. }
  355. static inline void qeth_free_cq(struct qeth_card *card)
  356. {
  357. if (card->qdio.c_q) {
  358. --card->qdio.no_in_queues;
  359. qeth_free_qdio_queue(card->qdio.c_q);
  360. card->qdio.c_q = NULL;
  361. }
  362. kfree(card->qdio.out_bufstates);
  363. card->qdio.out_bufstates = NULL;
  364. }
  365. static inline enum iucv_tx_notify qeth_compute_cq_notification(int sbalf15,
  366. int delayed) {
  367. enum iucv_tx_notify n;
  368. switch (sbalf15) {
  369. case 0:
  370. n = delayed ? TX_NOTIFY_DELAYED_OK : TX_NOTIFY_OK;
  371. break;
  372. case 4:
  373. case 16:
  374. case 17:
  375. case 18:
  376. n = delayed ? TX_NOTIFY_DELAYED_UNREACHABLE :
  377. TX_NOTIFY_UNREACHABLE;
  378. break;
  379. default:
  380. n = delayed ? TX_NOTIFY_DELAYED_GENERALERROR :
  381. TX_NOTIFY_GENERALERROR;
  382. break;
  383. }
  384. return n;
  385. }
  386. static inline void qeth_cleanup_handled_pending(struct qeth_qdio_out_q *q,
  387. int bidx, int forced_cleanup)
  388. {
  389. if (q->card->options.cq != QETH_CQ_ENABLED)
  390. return;
  391. if (q->bufs[bidx]->next_pending != NULL) {
  392. struct qeth_qdio_out_buffer *head = q->bufs[bidx];
  393. struct qeth_qdio_out_buffer *c = q->bufs[bidx]->next_pending;
  394. while (c) {
  395. if (forced_cleanup ||
  396. atomic_read(&c->state) ==
  397. QETH_QDIO_BUF_HANDLED_DELAYED) {
  398. struct qeth_qdio_out_buffer *f = c;
  399. QETH_CARD_TEXT(f->q->card, 5, "fp");
  400. QETH_CARD_TEXT_(f->q->card, 5, "%lx", (long) f);
  401. /* release here to avoid interleaving between
  402. outbound tasklet and inbound tasklet
  403. regarding notifications and lifecycle */
  404. qeth_release_skbs(c);
  405. c = f->next_pending;
  406. WARN_ON_ONCE(head->next_pending != f);
  407. head->next_pending = c;
  408. kmem_cache_free(qeth_qdio_outbuf_cache, f);
  409. } else {
  410. head = c;
  411. c = c->next_pending;
  412. }
  413. }
  414. }
  415. if (forced_cleanup && (atomic_read(&(q->bufs[bidx]->state)) ==
  416. QETH_QDIO_BUF_HANDLED_DELAYED)) {
  417. /* for recovery situations */
  418. q->bufs[bidx]->aob = q->bufstates[bidx].aob;
  419. qeth_init_qdio_out_buf(q, bidx);
  420. QETH_CARD_TEXT(q->card, 2, "clprecov");
  421. }
  422. }
  423. static inline void qeth_qdio_handle_aob(struct qeth_card *card,
  424. unsigned long phys_aob_addr) {
  425. struct qaob *aob;
  426. struct qeth_qdio_out_buffer *buffer;
  427. enum iucv_tx_notify notification;
  428. aob = (struct qaob *) phys_to_virt(phys_aob_addr);
  429. QETH_CARD_TEXT(card, 5, "haob");
  430. QETH_CARD_TEXT_(card, 5, "%lx", phys_aob_addr);
  431. buffer = (struct qeth_qdio_out_buffer *) aob->user1;
  432. QETH_CARD_TEXT_(card, 5, "%lx", aob->user1);
  433. if (atomic_cmpxchg(&buffer->state, QETH_QDIO_BUF_PRIMED,
  434. QETH_QDIO_BUF_IN_CQ) == QETH_QDIO_BUF_PRIMED) {
  435. notification = TX_NOTIFY_OK;
  436. } else {
  437. WARN_ON_ONCE(atomic_read(&buffer->state) !=
  438. QETH_QDIO_BUF_PENDING);
  439. atomic_set(&buffer->state, QETH_QDIO_BUF_IN_CQ);
  440. notification = TX_NOTIFY_DELAYED_OK;
  441. }
  442. if (aob->aorc != 0) {
  443. QETH_CARD_TEXT_(card, 2, "aorc%02X", aob->aorc);
  444. notification = qeth_compute_cq_notification(aob->aorc, 1);
  445. }
  446. qeth_notify_skbs(buffer->q, buffer, notification);
  447. buffer->aob = NULL;
  448. qeth_clear_output_buffer(buffer->q, buffer,
  449. QETH_QDIO_BUF_HANDLED_DELAYED);
  450. /* from here on: do not touch buffer anymore */
  451. qdio_release_aob(aob);
  452. }
  453. static inline int qeth_is_cq(struct qeth_card *card, unsigned int queue)
  454. {
  455. return card->options.cq == QETH_CQ_ENABLED &&
  456. card->qdio.c_q != NULL &&
  457. queue != 0 &&
  458. queue == card->qdio.no_in_queues - 1;
  459. }
  460. static int qeth_issue_next_read(struct qeth_card *card)
  461. {
  462. int rc;
  463. struct qeth_cmd_buffer *iob;
  464. QETH_CARD_TEXT(card, 5, "issnxrd");
  465. if (card->read.state != CH_STATE_UP)
  466. return -EIO;
  467. iob = qeth_get_buffer(&card->read);
  468. if (!iob) {
  469. dev_warn(&card->gdev->dev, "The qeth device driver "
  470. "failed to recover an error on the device\n");
  471. QETH_DBF_MESSAGE(2, "%s issue_next_read failed: no iob "
  472. "available\n", dev_name(&card->gdev->dev));
  473. return -ENOMEM;
  474. }
  475. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  476. QETH_CARD_TEXT(card, 6, "noirqpnd");
  477. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  478. (addr_t) iob, 0, 0);
  479. if (rc) {
  480. QETH_DBF_MESSAGE(2, "%s error in starting next read ccw! "
  481. "rc=%i\n", dev_name(&card->gdev->dev), rc);
  482. atomic_set(&card->read.irq_pending, 0);
  483. card->read_or_write_problem = 1;
  484. qeth_schedule_recovery(card);
  485. wake_up(&card->wait_q);
  486. }
  487. return rc;
  488. }
  489. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  490. {
  491. struct qeth_reply *reply;
  492. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  493. if (reply) {
  494. atomic_set(&reply->refcnt, 1);
  495. atomic_set(&reply->received, 0);
  496. reply->card = card;
  497. }
  498. return reply;
  499. }
  500. static void qeth_get_reply(struct qeth_reply *reply)
  501. {
  502. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  503. atomic_inc(&reply->refcnt);
  504. }
  505. static void qeth_put_reply(struct qeth_reply *reply)
  506. {
  507. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  508. if (atomic_dec_and_test(&reply->refcnt))
  509. kfree(reply);
  510. }
  511. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
  512. struct qeth_card *card)
  513. {
  514. char *ipa_name;
  515. int com = cmd->hdr.command;
  516. ipa_name = qeth_get_ipa_cmd_name(com);
  517. if (rc)
  518. QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s/%s returned "
  519. "x%X \"%s\"\n",
  520. ipa_name, com, dev_name(&card->gdev->dev),
  521. QETH_CARD_IFNAME(card), rc,
  522. qeth_get_ipa_msg(rc));
  523. else
  524. QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s/%s succeeded\n",
  525. ipa_name, com, dev_name(&card->gdev->dev),
  526. QETH_CARD_IFNAME(card));
  527. }
  528. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  529. struct qeth_cmd_buffer *iob)
  530. {
  531. struct qeth_ipa_cmd *cmd = NULL;
  532. QETH_CARD_TEXT(card, 5, "chkipad");
  533. if (IS_IPA(iob->data)) {
  534. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  535. if (IS_IPA_REPLY(cmd)) {
  536. if (cmd->hdr.command != IPA_CMD_SETCCID &&
  537. cmd->hdr.command != IPA_CMD_DELCCID &&
  538. cmd->hdr.command != IPA_CMD_MODCCID &&
  539. cmd->hdr.command != IPA_CMD_SET_DIAG_ASS)
  540. qeth_issue_ipa_msg(cmd,
  541. cmd->hdr.return_code, card);
  542. return cmd;
  543. } else {
  544. switch (cmd->hdr.command) {
  545. case IPA_CMD_STOPLAN:
  546. if (cmd->hdr.return_code ==
  547. IPA_RC_VEPA_TO_VEB_TRANSITION) {
  548. dev_err(&card->gdev->dev,
  549. "Interface %s is down because the "
  550. "adjacent port is no longer in "
  551. "reflective relay mode\n",
  552. QETH_CARD_IFNAME(card));
  553. qeth_close_dev(card);
  554. } else {
  555. dev_warn(&card->gdev->dev,
  556. "The link for interface %s on CHPID"
  557. " 0x%X failed\n",
  558. QETH_CARD_IFNAME(card),
  559. card->info.chpid);
  560. qeth_issue_ipa_msg(cmd,
  561. cmd->hdr.return_code, card);
  562. }
  563. card->lan_online = 0;
  564. if (card->dev && netif_carrier_ok(card->dev))
  565. netif_carrier_off(card->dev);
  566. return NULL;
  567. case IPA_CMD_STARTLAN:
  568. dev_info(&card->gdev->dev,
  569. "The link for %s on CHPID 0x%X has"
  570. " been restored\n",
  571. QETH_CARD_IFNAME(card),
  572. card->info.chpid);
  573. netif_carrier_on(card->dev);
  574. card->lan_online = 1;
  575. if (card->info.hwtrap)
  576. card->info.hwtrap = 2;
  577. qeth_schedule_recovery(card);
  578. return NULL;
  579. case IPA_CMD_SETBRIDGEPORT_IQD:
  580. case IPA_CMD_SETBRIDGEPORT_OSA:
  581. case IPA_CMD_ADDRESS_CHANGE_NOTIF:
  582. if (card->discipline->control_event_handler
  583. (card, cmd))
  584. return cmd;
  585. else
  586. return NULL;
  587. case IPA_CMD_MODCCID:
  588. return cmd;
  589. case IPA_CMD_REGISTER_LOCAL_ADDR:
  590. QETH_CARD_TEXT(card, 3, "irla");
  591. break;
  592. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  593. QETH_CARD_TEXT(card, 3, "urla");
  594. break;
  595. default:
  596. QETH_DBF_MESSAGE(2, "Received data is IPA "
  597. "but not a reply!\n");
  598. break;
  599. }
  600. }
  601. }
  602. return cmd;
  603. }
  604. void qeth_clear_ipacmd_list(struct qeth_card *card)
  605. {
  606. struct qeth_reply *reply, *r;
  607. unsigned long flags;
  608. QETH_CARD_TEXT(card, 4, "clipalst");
  609. spin_lock_irqsave(&card->lock, flags);
  610. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  611. qeth_get_reply(reply);
  612. reply->rc = -EIO;
  613. atomic_inc(&reply->received);
  614. list_del_init(&reply->list);
  615. wake_up(&reply->wait_q);
  616. qeth_put_reply(reply);
  617. }
  618. spin_unlock_irqrestore(&card->lock, flags);
  619. atomic_set(&card->write.irq_pending, 0);
  620. }
  621. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  622. static int qeth_check_idx_response(struct qeth_card *card,
  623. unsigned char *buffer)
  624. {
  625. if (!buffer)
  626. return 0;
  627. QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
  628. if ((buffer[2] & 0xc0) == 0xc0) {
  629. QETH_DBF_MESSAGE(2, "received an IDX TERMINATE "
  630. "with cause code 0x%02x%s\n",
  631. buffer[4],
  632. ((buffer[4] == 0x22) ?
  633. " -- try another portname" : ""));
  634. QETH_CARD_TEXT(card, 2, "ckidxres");
  635. QETH_CARD_TEXT(card, 2, " idxterm");
  636. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  637. if (buffer[4] == 0xf6) {
  638. dev_err(&card->gdev->dev,
  639. "The qeth device is not configured "
  640. "for the OSI layer required by z/VM\n");
  641. return -EPERM;
  642. }
  643. return -EIO;
  644. }
  645. return 0;
  646. }
  647. static struct qeth_card *CARD_FROM_CDEV(struct ccw_device *cdev)
  648. {
  649. struct qeth_card *card = dev_get_drvdata(&((struct ccwgroup_device *)
  650. dev_get_drvdata(&cdev->dev))->dev);
  651. return card;
  652. }
  653. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  654. __u32 len)
  655. {
  656. struct qeth_card *card;
  657. card = CARD_FROM_CDEV(channel->ccwdev);
  658. QETH_CARD_TEXT(card, 4, "setupccw");
  659. if (channel == &card->read)
  660. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  661. else
  662. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  663. channel->ccw.count = len;
  664. channel->ccw.cda = (__u32) __pa(iob);
  665. }
  666. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  667. {
  668. __u8 index;
  669. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "getbuff");
  670. index = channel->io_buf_no;
  671. do {
  672. if (channel->iob[index].state == BUF_STATE_FREE) {
  673. channel->iob[index].state = BUF_STATE_LOCKED;
  674. channel->io_buf_no = (channel->io_buf_no + 1) %
  675. QETH_CMD_BUFFER_NO;
  676. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  677. return channel->iob + index;
  678. }
  679. index = (index + 1) % QETH_CMD_BUFFER_NO;
  680. } while (index != channel->io_buf_no);
  681. return NULL;
  682. }
  683. void qeth_release_buffer(struct qeth_channel *channel,
  684. struct qeth_cmd_buffer *iob)
  685. {
  686. unsigned long flags;
  687. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "relbuff");
  688. spin_lock_irqsave(&channel->iob_lock, flags);
  689. memset(iob->data, 0, QETH_BUFSIZE);
  690. iob->state = BUF_STATE_FREE;
  691. iob->callback = qeth_send_control_data_cb;
  692. iob->rc = 0;
  693. spin_unlock_irqrestore(&channel->iob_lock, flags);
  694. wake_up(&channel->wait_q);
  695. }
  696. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  697. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  698. {
  699. struct qeth_cmd_buffer *buffer = NULL;
  700. unsigned long flags;
  701. spin_lock_irqsave(&channel->iob_lock, flags);
  702. buffer = __qeth_get_buffer(channel);
  703. spin_unlock_irqrestore(&channel->iob_lock, flags);
  704. return buffer;
  705. }
  706. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  707. {
  708. struct qeth_cmd_buffer *buffer;
  709. wait_event(channel->wait_q,
  710. ((buffer = qeth_get_buffer(channel)) != NULL));
  711. return buffer;
  712. }
  713. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  714. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  715. {
  716. int cnt;
  717. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  718. qeth_release_buffer(channel, &channel->iob[cnt]);
  719. channel->buf_no = 0;
  720. channel->io_buf_no = 0;
  721. }
  722. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  723. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  724. struct qeth_cmd_buffer *iob)
  725. {
  726. struct qeth_card *card;
  727. struct qeth_reply *reply, *r;
  728. struct qeth_ipa_cmd *cmd;
  729. unsigned long flags;
  730. int keep_reply;
  731. int rc = 0;
  732. card = CARD_FROM_CDEV(channel->ccwdev);
  733. QETH_CARD_TEXT(card, 4, "sndctlcb");
  734. rc = qeth_check_idx_response(card, iob->data);
  735. switch (rc) {
  736. case 0:
  737. break;
  738. case -EIO:
  739. qeth_clear_ipacmd_list(card);
  740. qeth_schedule_recovery(card);
  741. /* fall through */
  742. default:
  743. goto out;
  744. }
  745. cmd = qeth_check_ipa_data(card, iob);
  746. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  747. goto out;
  748. /*in case of OSN : check if cmd is set */
  749. if (card->info.type == QETH_CARD_TYPE_OSN &&
  750. cmd &&
  751. cmd->hdr.command != IPA_CMD_STARTLAN &&
  752. card->osn_info.assist_cb != NULL) {
  753. card->osn_info.assist_cb(card->dev, cmd);
  754. goto out;
  755. }
  756. spin_lock_irqsave(&card->lock, flags);
  757. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  758. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  759. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  760. qeth_get_reply(reply);
  761. list_del_init(&reply->list);
  762. spin_unlock_irqrestore(&card->lock, flags);
  763. keep_reply = 0;
  764. if (reply->callback != NULL) {
  765. if (cmd) {
  766. reply->offset = (__u16)((char *)cmd -
  767. (char *)iob->data);
  768. keep_reply = reply->callback(card,
  769. reply,
  770. (unsigned long)cmd);
  771. } else
  772. keep_reply = reply->callback(card,
  773. reply,
  774. (unsigned long)iob);
  775. }
  776. if (cmd)
  777. reply->rc = (u16) cmd->hdr.return_code;
  778. else if (iob->rc)
  779. reply->rc = iob->rc;
  780. if (keep_reply) {
  781. spin_lock_irqsave(&card->lock, flags);
  782. list_add_tail(&reply->list,
  783. &card->cmd_waiter_list);
  784. spin_unlock_irqrestore(&card->lock, flags);
  785. } else {
  786. atomic_inc(&reply->received);
  787. wake_up(&reply->wait_q);
  788. }
  789. qeth_put_reply(reply);
  790. goto out;
  791. }
  792. }
  793. spin_unlock_irqrestore(&card->lock, flags);
  794. out:
  795. memcpy(&card->seqno.pdu_hdr_ack,
  796. QETH_PDU_HEADER_SEQ_NO(iob->data),
  797. QETH_SEQ_NO_LENGTH);
  798. qeth_release_buffer(channel, iob);
  799. }
  800. static int qeth_setup_channel(struct qeth_channel *channel)
  801. {
  802. int cnt;
  803. QETH_DBF_TEXT(SETUP, 2, "setupch");
  804. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  805. channel->iob[cnt].data =
  806. kzalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  807. if (channel->iob[cnt].data == NULL)
  808. break;
  809. channel->iob[cnt].state = BUF_STATE_FREE;
  810. channel->iob[cnt].channel = channel;
  811. channel->iob[cnt].callback = qeth_send_control_data_cb;
  812. channel->iob[cnt].rc = 0;
  813. }
  814. if (cnt < QETH_CMD_BUFFER_NO) {
  815. while (cnt-- > 0)
  816. kfree(channel->iob[cnt].data);
  817. return -ENOMEM;
  818. }
  819. channel->buf_no = 0;
  820. channel->io_buf_no = 0;
  821. atomic_set(&channel->irq_pending, 0);
  822. spin_lock_init(&channel->iob_lock);
  823. init_waitqueue_head(&channel->wait_q);
  824. return 0;
  825. }
  826. static int qeth_set_thread_start_bit(struct qeth_card *card,
  827. unsigned long thread)
  828. {
  829. unsigned long flags;
  830. spin_lock_irqsave(&card->thread_mask_lock, flags);
  831. if (!(card->thread_allowed_mask & thread) ||
  832. (card->thread_start_mask & thread)) {
  833. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  834. return -EPERM;
  835. }
  836. card->thread_start_mask |= thread;
  837. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  838. return 0;
  839. }
  840. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  841. {
  842. unsigned long flags;
  843. spin_lock_irqsave(&card->thread_mask_lock, flags);
  844. card->thread_start_mask &= ~thread;
  845. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  846. wake_up(&card->wait_q);
  847. }
  848. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  849. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  850. {
  851. unsigned long flags;
  852. spin_lock_irqsave(&card->thread_mask_lock, flags);
  853. card->thread_running_mask &= ~thread;
  854. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  855. wake_up(&card->wait_q);
  856. }
  857. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  858. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  859. {
  860. unsigned long flags;
  861. int rc = 0;
  862. spin_lock_irqsave(&card->thread_mask_lock, flags);
  863. if (card->thread_start_mask & thread) {
  864. if ((card->thread_allowed_mask & thread) &&
  865. !(card->thread_running_mask & thread)) {
  866. rc = 1;
  867. card->thread_start_mask &= ~thread;
  868. card->thread_running_mask |= thread;
  869. } else
  870. rc = -EPERM;
  871. }
  872. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  873. return rc;
  874. }
  875. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  876. {
  877. int rc = 0;
  878. wait_event(card->wait_q,
  879. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  880. return rc;
  881. }
  882. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  883. void qeth_schedule_recovery(struct qeth_card *card)
  884. {
  885. QETH_CARD_TEXT(card, 2, "startrec");
  886. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  887. schedule_work(&card->kernel_thread_starter);
  888. }
  889. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  890. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  891. {
  892. int dstat, cstat;
  893. char *sense;
  894. struct qeth_card *card;
  895. sense = (char *) irb->ecw;
  896. cstat = irb->scsw.cmd.cstat;
  897. dstat = irb->scsw.cmd.dstat;
  898. card = CARD_FROM_CDEV(cdev);
  899. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  900. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  901. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  902. QETH_CARD_TEXT(card, 2, "CGENCHK");
  903. dev_warn(&cdev->dev, "The qeth device driver "
  904. "failed to recover an error on the device\n");
  905. QETH_DBF_MESSAGE(2, "%s check on device dstat=x%x, cstat=x%x\n",
  906. dev_name(&cdev->dev), dstat, cstat);
  907. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  908. 16, 1, irb, 64, 1);
  909. return 1;
  910. }
  911. if (dstat & DEV_STAT_UNIT_CHECK) {
  912. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  913. SENSE_RESETTING_EVENT_FLAG) {
  914. QETH_CARD_TEXT(card, 2, "REVIND");
  915. return 1;
  916. }
  917. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  918. SENSE_COMMAND_REJECT_FLAG) {
  919. QETH_CARD_TEXT(card, 2, "CMDREJi");
  920. return 1;
  921. }
  922. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  923. QETH_CARD_TEXT(card, 2, "AFFE");
  924. return 1;
  925. }
  926. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  927. QETH_CARD_TEXT(card, 2, "ZEROSEN");
  928. return 0;
  929. }
  930. QETH_CARD_TEXT(card, 2, "DGENCHK");
  931. return 1;
  932. }
  933. return 0;
  934. }
  935. static long __qeth_check_irb_error(struct ccw_device *cdev,
  936. unsigned long intparm, struct irb *irb)
  937. {
  938. struct qeth_card *card;
  939. card = CARD_FROM_CDEV(cdev);
  940. if (!card || !IS_ERR(irb))
  941. return 0;
  942. switch (PTR_ERR(irb)) {
  943. case -EIO:
  944. QETH_DBF_MESSAGE(2, "%s i/o-error on device\n",
  945. dev_name(&cdev->dev));
  946. QETH_CARD_TEXT(card, 2, "ckirberr");
  947. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  948. break;
  949. case -ETIMEDOUT:
  950. dev_warn(&cdev->dev, "A hardware operation timed out"
  951. " on the device\n");
  952. QETH_CARD_TEXT(card, 2, "ckirberr");
  953. QETH_CARD_TEXT_(card, 2, " rc%d", -ETIMEDOUT);
  954. if (intparm == QETH_RCD_PARM) {
  955. if (card->data.ccwdev == cdev) {
  956. card->data.state = CH_STATE_DOWN;
  957. wake_up(&card->wait_q);
  958. }
  959. }
  960. break;
  961. default:
  962. QETH_DBF_MESSAGE(2, "%s unknown error %ld on device\n",
  963. dev_name(&cdev->dev), PTR_ERR(irb));
  964. QETH_CARD_TEXT(card, 2, "ckirberr");
  965. QETH_CARD_TEXT(card, 2, " rc???");
  966. }
  967. return PTR_ERR(irb);
  968. }
  969. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  970. struct irb *irb)
  971. {
  972. int rc;
  973. int cstat, dstat;
  974. struct qeth_cmd_buffer *buffer;
  975. struct qeth_channel *channel;
  976. struct qeth_card *card;
  977. struct qeth_cmd_buffer *iob;
  978. __u8 index;
  979. if (__qeth_check_irb_error(cdev, intparm, irb))
  980. return;
  981. cstat = irb->scsw.cmd.cstat;
  982. dstat = irb->scsw.cmd.dstat;
  983. card = CARD_FROM_CDEV(cdev);
  984. if (!card)
  985. return;
  986. QETH_CARD_TEXT(card, 5, "irq");
  987. if (card->read.ccwdev == cdev) {
  988. channel = &card->read;
  989. QETH_CARD_TEXT(card, 5, "read");
  990. } else if (card->write.ccwdev == cdev) {
  991. channel = &card->write;
  992. QETH_CARD_TEXT(card, 5, "write");
  993. } else {
  994. channel = &card->data;
  995. QETH_CARD_TEXT(card, 5, "data");
  996. }
  997. atomic_set(&channel->irq_pending, 0);
  998. if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
  999. channel->state = CH_STATE_STOPPED;
  1000. if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
  1001. channel->state = CH_STATE_HALTED;
  1002. /*let's wake up immediately on data channel*/
  1003. if ((channel == &card->data) && (intparm != 0) &&
  1004. (intparm != QETH_RCD_PARM))
  1005. goto out;
  1006. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  1007. QETH_CARD_TEXT(card, 6, "clrchpar");
  1008. /* we don't have to handle this further */
  1009. intparm = 0;
  1010. }
  1011. if (intparm == QETH_HALT_CHANNEL_PARM) {
  1012. QETH_CARD_TEXT(card, 6, "hltchpar");
  1013. /* we don't have to handle this further */
  1014. intparm = 0;
  1015. }
  1016. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  1017. (dstat & DEV_STAT_UNIT_CHECK) ||
  1018. (cstat)) {
  1019. if (irb->esw.esw0.erw.cons) {
  1020. dev_warn(&channel->ccwdev->dev,
  1021. "The qeth device driver failed to recover "
  1022. "an error on the device\n");
  1023. QETH_DBF_MESSAGE(2, "%s sense data available. cstat "
  1024. "0x%X dstat 0x%X\n",
  1025. dev_name(&channel->ccwdev->dev), cstat, dstat);
  1026. print_hex_dump(KERN_WARNING, "qeth: irb ",
  1027. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  1028. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  1029. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  1030. }
  1031. if (intparm == QETH_RCD_PARM) {
  1032. channel->state = CH_STATE_DOWN;
  1033. goto out;
  1034. }
  1035. rc = qeth_get_problem(cdev, irb);
  1036. if (rc) {
  1037. qeth_clear_ipacmd_list(card);
  1038. qeth_schedule_recovery(card);
  1039. goto out;
  1040. }
  1041. }
  1042. if (intparm == QETH_RCD_PARM) {
  1043. channel->state = CH_STATE_RCD_DONE;
  1044. goto out;
  1045. }
  1046. if (intparm) {
  1047. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  1048. buffer->state = BUF_STATE_PROCESSED;
  1049. }
  1050. if (channel == &card->data)
  1051. return;
  1052. if (channel == &card->read &&
  1053. channel->state == CH_STATE_UP)
  1054. qeth_issue_next_read(card);
  1055. iob = channel->iob;
  1056. index = channel->buf_no;
  1057. while (iob[index].state == BUF_STATE_PROCESSED) {
  1058. if (iob[index].callback != NULL)
  1059. iob[index].callback(channel, iob + index);
  1060. index = (index + 1) % QETH_CMD_BUFFER_NO;
  1061. }
  1062. channel->buf_no = index;
  1063. out:
  1064. wake_up(&card->wait_q);
  1065. return;
  1066. }
  1067. static void qeth_notify_skbs(struct qeth_qdio_out_q *q,
  1068. struct qeth_qdio_out_buffer *buf,
  1069. enum iucv_tx_notify notification)
  1070. {
  1071. struct sk_buff *skb;
  1072. if (skb_queue_empty(&buf->skb_list))
  1073. goto out;
  1074. skb = skb_peek(&buf->skb_list);
  1075. while (skb) {
  1076. QETH_CARD_TEXT_(q->card, 5, "skbn%d", notification);
  1077. QETH_CARD_TEXT_(q->card, 5, "%lx", (long) skb);
  1078. if (skb->protocol == ETH_P_AF_IUCV) {
  1079. if (skb->sk) {
  1080. struct iucv_sock *iucv = iucv_sk(skb->sk);
  1081. iucv->sk_txnotify(skb, notification);
  1082. }
  1083. }
  1084. if (skb_queue_is_last(&buf->skb_list, skb))
  1085. skb = NULL;
  1086. else
  1087. skb = skb_queue_next(&buf->skb_list, skb);
  1088. }
  1089. out:
  1090. return;
  1091. }
  1092. static void qeth_release_skbs(struct qeth_qdio_out_buffer *buf)
  1093. {
  1094. struct sk_buff *skb;
  1095. struct iucv_sock *iucv;
  1096. int notify_general_error = 0;
  1097. if (atomic_read(&buf->state) == QETH_QDIO_BUF_PENDING)
  1098. notify_general_error = 1;
  1099. /* release may never happen from within CQ tasklet scope */
  1100. WARN_ON_ONCE(atomic_read(&buf->state) == QETH_QDIO_BUF_IN_CQ);
  1101. skb = skb_dequeue(&buf->skb_list);
  1102. while (skb) {
  1103. QETH_CARD_TEXT(buf->q->card, 5, "skbr");
  1104. QETH_CARD_TEXT_(buf->q->card, 5, "%lx", (long) skb);
  1105. if (notify_general_error && skb->protocol == ETH_P_AF_IUCV) {
  1106. if (skb->sk) {
  1107. iucv = iucv_sk(skb->sk);
  1108. iucv->sk_txnotify(skb, TX_NOTIFY_GENERALERROR);
  1109. }
  1110. }
  1111. atomic_dec(&skb->users);
  1112. dev_kfree_skb_any(skb);
  1113. skb = skb_dequeue(&buf->skb_list);
  1114. }
  1115. }
  1116. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  1117. struct qeth_qdio_out_buffer *buf,
  1118. enum qeth_qdio_buffer_states newbufstate)
  1119. {
  1120. int i;
  1121. /* is PCI flag set on buffer? */
  1122. if (buf->buffer->element[0].sflags & SBAL_SFLAGS0_PCI_REQ)
  1123. atomic_dec(&queue->set_pci_flags_count);
  1124. if (newbufstate == QETH_QDIO_BUF_EMPTY) {
  1125. qeth_release_skbs(buf);
  1126. }
  1127. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  1128. if (buf->buffer->element[i].addr && buf->is_header[i])
  1129. kmem_cache_free(qeth_core_header_cache,
  1130. buf->buffer->element[i].addr);
  1131. buf->is_header[i] = 0;
  1132. buf->buffer->element[i].length = 0;
  1133. buf->buffer->element[i].addr = NULL;
  1134. buf->buffer->element[i].eflags = 0;
  1135. buf->buffer->element[i].sflags = 0;
  1136. }
  1137. buf->buffer->element[15].eflags = 0;
  1138. buf->buffer->element[15].sflags = 0;
  1139. buf->next_element_to_fill = 0;
  1140. atomic_set(&buf->state, newbufstate);
  1141. }
  1142. static void qeth_clear_outq_buffers(struct qeth_qdio_out_q *q, int free)
  1143. {
  1144. int j;
  1145. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1146. if (!q->bufs[j])
  1147. continue;
  1148. qeth_cleanup_handled_pending(q, j, 1);
  1149. qeth_clear_output_buffer(q, q->bufs[j], QETH_QDIO_BUF_EMPTY);
  1150. if (free) {
  1151. kmem_cache_free(qeth_qdio_outbuf_cache, q->bufs[j]);
  1152. q->bufs[j] = NULL;
  1153. }
  1154. }
  1155. }
  1156. void qeth_clear_qdio_buffers(struct qeth_card *card)
  1157. {
  1158. int i;
  1159. QETH_CARD_TEXT(card, 2, "clearqdbf");
  1160. /* clear outbound buffers to free skbs */
  1161. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1162. if (card->qdio.out_qs[i]) {
  1163. qeth_clear_outq_buffers(card->qdio.out_qs[i], 0);
  1164. }
  1165. }
  1166. }
  1167. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  1168. static void qeth_free_buffer_pool(struct qeth_card *card)
  1169. {
  1170. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  1171. int i = 0;
  1172. list_for_each_entry_safe(pool_entry, tmp,
  1173. &card->qdio.init_pool.entry_list, init_list){
  1174. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  1175. free_page((unsigned long)pool_entry->elements[i]);
  1176. list_del(&pool_entry->init_list);
  1177. kfree(pool_entry);
  1178. }
  1179. }
  1180. static void qeth_clean_channel(struct qeth_channel *channel)
  1181. {
  1182. int cnt;
  1183. QETH_DBF_TEXT(SETUP, 2, "freech");
  1184. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  1185. kfree(channel->iob[cnt].data);
  1186. }
  1187. static void qeth_set_single_write_queues(struct qeth_card *card)
  1188. {
  1189. if ((atomic_read(&card->qdio.state) != QETH_QDIO_UNINITIALIZED) &&
  1190. (card->qdio.no_out_queues == 4))
  1191. qeth_free_qdio_buffers(card);
  1192. card->qdio.no_out_queues = 1;
  1193. if (card->qdio.default_out_queue != 0)
  1194. dev_info(&card->gdev->dev, "Priority Queueing not supported\n");
  1195. card->qdio.default_out_queue = 0;
  1196. }
  1197. static void qeth_set_multiple_write_queues(struct qeth_card *card)
  1198. {
  1199. if ((atomic_read(&card->qdio.state) != QETH_QDIO_UNINITIALIZED) &&
  1200. (card->qdio.no_out_queues == 1)) {
  1201. qeth_free_qdio_buffers(card);
  1202. card->qdio.default_out_queue = 2;
  1203. }
  1204. card->qdio.no_out_queues = 4;
  1205. }
  1206. static void qeth_update_from_chp_desc(struct qeth_card *card)
  1207. {
  1208. struct ccw_device *ccwdev;
  1209. struct channel_path_desc *chp_dsc;
  1210. QETH_DBF_TEXT(SETUP, 2, "chp_desc");
  1211. ccwdev = card->data.ccwdev;
  1212. chp_dsc = ccw_device_get_chp_desc(ccwdev, 0);
  1213. if (!chp_dsc)
  1214. goto out;
  1215. card->info.func_level = 0x4100 + chp_dsc->desc;
  1216. if (card->info.type == QETH_CARD_TYPE_IQD)
  1217. goto out;
  1218. /* CHPP field bit 6 == 1 -> single queue */
  1219. if ((chp_dsc->chpp & 0x02) == 0x02)
  1220. qeth_set_single_write_queues(card);
  1221. else
  1222. qeth_set_multiple_write_queues(card);
  1223. out:
  1224. kfree(chp_dsc);
  1225. QETH_DBF_TEXT_(SETUP, 2, "nr:%x", card->qdio.no_out_queues);
  1226. QETH_DBF_TEXT_(SETUP, 2, "lvl:%02x", card->info.func_level);
  1227. }
  1228. static void qeth_init_qdio_info(struct qeth_card *card)
  1229. {
  1230. QETH_DBF_TEXT(SETUP, 4, "intqdinf");
  1231. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1232. /* inbound */
  1233. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1234. if (card->info.type == QETH_CARD_TYPE_IQD)
  1235. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_HSDEFAULT;
  1236. else
  1237. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  1238. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  1239. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  1240. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  1241. }
  1242. static void qeth_set_intial_options(struct qeth_card *card)
  1243. {
  1244. card->options.route4.type = NO_ROUTER;
  1245. card->options.route6.type = NO_ROUTER;
  1246. card->options.fake_broadcast = 0;
  1247. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  1248. card->options.performance_stats = 0;
  1249. card->options.rx_sg_cb = QETH_RX_SG_CB;
  1250. card->options.isolation = ISOLATION_MODE_NONE;
  1251. card->options.cq = QETH_CQ_DISABLED;
  1252. }
  1253. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  1254. {
  1255. unsigned long flags;
  1256. int rc = 0;
  1257. spin_lock_irqsave(&card->thread_mask_lock, flags);
  1258. QETH_CARD_TEXT_(card, 4, " %02x%02x%02x",
  1259. (u8) card->thread_start_mask,
  1260. (u8) card->thread_allowed_mask,
  1261. (u8) card->thread_running_mask);
  1262. rc = (card->thread_start_mask & thread);
  1263. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  1264. return rc;
  1265. }
  1266. static void qeth_start_kernel_thread(struct work_struct *work)
  1267. {
  1268. struct task_struct *ts;
  1269. struct qeth_card *card = container_of(work, struct qeth_card,
  1270. kernel_thread_starter);
  1271. QETH_CARD_TEXT(card , 2, "strthrd");
  1272. if (card->read.state != CH_STATE_UP &&
  1273. card->write.state != CH_STATE_UP)
  1274. return;
  1275. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD)) {
  1276. ts = kthread_run(card->discipline->recover, (void *)card,
  1277. "qeth_recover");
  1278. if (IS_ERR(ts)) {
  1279. qeth_clear_thread_start_bit(card, QETH_RECOVER_THREAD);
  1280. qeth_clear_thread_running_bit(card,
  1281. QETH_RECOVER_THREAD);
  1282. }
  1283. }
  1284. }
  1285. static void qeth_buffer_reclaim_work(struct work_struct *);
  1286. static int qeth_setup_card(struct qeth_card *card)
  1287. {
  1288. QETH_DBF_TEXT(SETUP, 2, "setupcrd");
  1289. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1290. card->read.state = CH_STATE_DOWN;
  1291. card->write.state = CH_STATE_DOWN;
  1292. card->data.state = CH_STATE_DOWN;
  1293. card->state = CARD_STATE_DOWN;
  1294. card->lan_online = 0;
  1295. card->read_or_write_problem = 0;
  1296. card->dev = NULL;
  1297. spin_lock_init(&card->vlanlock);
  1298. spin_lock_init(&card->mclock);
  1299. spin_lock_init(&card->lock);
  1300. spin_lock_init(&card->ip_lock);
  1301. spin_lock_init(&card->thread_mask_lock);
  1302. mutex_init(&card->conf_mutex);
  1303. mutex_init(&card->discipline_mutex);
  1304. card->thread_start_mask = 0;
  1305. card->thread_allowed_mask = 0;
  1306. card->thread_running_mask = 0;
  1307. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  1308. INIT_LIST_HEAD(&card->cmd_waiter_list);
  1309. init_waitqueue_head(&card->wait_q);
  1310. /* initial options */
  1311. qeth_set_intial_options(card);
  1312. /* IP address takeover */
  1313. INIT_LIST_HEAD(&card->ipato.entries);
  1314. card->ipato.enabled = 0;
  1315. card->ipato.invert4 = 0;
  1316. card->ipato.invert6 = 0;
  1317. /* init QDIO stuff */
  1318. qeth_init_qdio_info(card);
  1319. INIT_DELAYED_WORK(&card->buffer_reclaim_work, qeth_buffer_reclaim_work);
  1320. INIT_WORK(&card->close_dev_work, qeth_close_dev_handler);
  1321. return 0;
  1322. }
  1323. static void qeth_core_sl_print(struct seq_file *m, struct service_level *slr)
  1324. {
  1325. struct qeth_card *card = container_of(slr, struct qeth_card,
  1326. qeth_service_level);
  1327. if (card->info.mcl_level[0])
  1328. seq_printf(m, "qeth: %s firmware level %s\n",
  1329. CARD_BUS_ID(card), card->info.mcl_level);
  1330. }
  1331. static struct qeth_card *qeth_alloc_card(void)
  1332. {
  1333. struct qeth_card *card;
  1334. QETH_DBF_TEXT(SETUP, 2, "alloccrd");
  1335. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1336. if (!card)
  1337. goto out;
  1338. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1339. if (qeth_setup_channel(&card->read))
  1340. goto out_ip;
  1341. if (qeth_setup_channel(&card->write))
  1342. goto out_channel;
  1343. card->options.layer2 = -1;
  1344. card->qeth_service_level.seq_print = qeth_core_sl_print;
  1345. register_service_level(&card->qeth_service_level);
  1346. return card;
  1347. out_channel:
  1348. qeth_clean_channel(&card->read);
  1349. out_ip:
  1350. kfree(card);
  1351. out:
  1352. return NULL;
  1353. }
  1354. static int qeth_determine_card_type(struct qeth_card *card)
  1355. {
  1356. int i = 0;
  1357. QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
  1358. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1359. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1360. while (known_devices[i][QETH_DEV_MODEL_IND]) {
  1361. if ((CARD_RDEV(card)->id.dev_type ==
  1362. known_devices[i][QETH_DEV_TYPE_IND]) &&
  1363. (CARD_RDEV(card)->id.dev_model ==
  1364. known_devices[i][QETH_DEV_MODEL_IND])) {
  1365. card->info.type = known_devices[i][QETH_DEV_MODEL_IND];
  1366. card->qdio.no_out_queues =
  1367. known_devices[i][QETH_QUEUE_NO_IND];
  1368. card->qdio.no_in_queues = 1;
  1369. card->info.is_multicast_different =
  1370. known_devices[i][QETH_MULTICAST_IND];
  1371. qeth_update_from_chp_desc(card);
  1372. return 0;
  1373. }
  1374. i++;
  1375. }
  1376. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1377. dev_err(&card->gdev->dev, "The adapter hardware is of an "
  1378. "unknown type\n");
  1379. return -ENOENT;
  1380. }
  1381. static int qeth_clear_channel(struct qeth_channel *channel)
  1382. {
  1383. unsigned long flags;
  1384. struct qeth_card *card;
  1385. int rc;
  1386. card = CARD_FROM_CDEV(channel->ccwdev);
  1387. QETH_CARD_TEXT(card, 3, "clearch");
  1388. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1389. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1390. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1391. if (rc)
  1392. return rc;
  1393. rc = wait_event_interruptible_timeout(card->wait_q,
  1394. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1395. if (rc == -ERESTARTSYS)
  1396. return rc;
  1397. if (channel->state != CH_STATE_STOPPED)
  1398. return -ETIME;
  1399. channel->state = CH_STATE_DOWN;
  1400. return 0;
  1401. }
  1402. static int qeth_halt_channel(struct qeth_channel *channel)
  1403. {
  1404. unsigned long flags;
  1405. struct qeth_card *card;
  1406. int rc;
  1407. card = CARD_FROM_CDEV(channel->ccwdev);
  1408. QETH_CARD_TEXT(card, 3, "haltch");
  1409. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1410. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1411. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1412. if (rc)
  1413. return rc;
  1414. rc = wait_event_interruptible_timeout(card->wait_q,
  1415. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1416. if (rc == -ERESTARTSYS)
  1417. return rc;
  1418. if (channel->state != CH_STATE_HALTED)
  1419. return -ETIME;
  1420. return 0;
  1421. }
  1422. static int qeth_halt_channels(struct qeth_card *card)
  1423. {
  1424. int rc1 = 0, rc2 = 0, rc3 = 0;
  1425. QETH_CARD_TEXT(card, 3, "haltchs");
  1426. rc1 = qeth_halt_channel(&card->read);
  1427. rc2 = qeth_halt_channel(&card->write);
  1428. rc3 = qeth_halt_channel(&card->data);
  1429. if (rc1)
  1430. return rc1;
  1431. if (rc2)
  1432. return rc2;
  1433. return rc3;
  1434. }
  1435. static int qeth_clear_channels(struct qeth_card *card)
  1436. {
  1437. int rc1 = 0, rc2 = 0, rc3 = 0;
  1438. QETH_CARD_TEXT(card, 3, "clearchs");
  1439. rc1 = qeth_clear_channel(&card->read);
  1440. rc2 = qeth_clear_channel(&card->write);
  1441. rc3 = qeth_clear_channel(&card->data);
  1442. if (rc1)
  1443. return rc1;
  1444. if (rc2)
  1445. return rc2;
  1446. return rc3;
  1447. }
  1448. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1449. {
  1450. int rc = 0;
  1451. QETH_CARD_TEXT(card, 3, "clhacrd");
  1452. if (halt)
  1453. rc = qeth_halt_channels(card);
  1454. if (rc)
  1455. return rc;
  1456. return qeth_clear_channels(card);
  1457. }
  1458. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1459. {
  1460. int rc = 0;
  1461. QETH_CARD_TEXT(card, 3, "qdioclr");
  1462. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1463. QETH_QDIO_CLEANING)) {
  1464. case QETH_QDIO_ESTABLISHED:
  1465. if (card->info.type == QETH_CARD_TYPE_IQD)
  1466. rc = qdio_shutdown(CARD_DDEV(card),
  1467. QDIO_FLAG_CLEANUP_USING_HALT);
  1468. else
  1469. rc = qdio_shutdown(CARD_DDEV(card),
  1470. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1471. if (rc)
  1472. QETH_CARD_TEXT_(card, 3, "1err%d", rc);
  1473. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1474. break;
  1475. case QETH_QDIO_CLEANING:
  1476. return rc;
  1477. default:
  1478. break;
  1479. }
  1480. rc = qeth_clear_halt_card(card, use_halt);
  1481. if (rc)
  1482. QETH_CARD_TEXT_(card, 3, "2err%d", rc);
  1483. card->state = CARD_STATE_DOWN;
  1484. return rc;
  1485. }
  1486. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1487. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1488. int *length)
  1489. {
  1490. struct ciw *ciw;
  1491. char *rcd_buf;
  1492. int ret;
  1493. struct qeth_channel *channel = &card->data;
  1494. unsigned long flags;
  1495. /*
  1496. * scan for RCD command in extended SenseID data
  1497. */
  1498. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1499. if (!ciw || ciw->cmd == 0)
  1500. return -EOPNOTSUPP;
  1501. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1502. if (!rcd_buf)
  1503. return -ENOMEM;
  1504. channel->ccw.cmd_code = ciw->cmd;
  1505. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1506. channel->ccw.count = ciw->count;
  1507. channel->ccw.flags = CCW_FLAG_SLI;
  1508. channel->state = CH_STATE_RCD;
  1509. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1510. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1511. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1512. QETH_RCD_TIMEOUT);
  1513. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1514. if (!ret)
  1515. wait_event(card->wait_q,
  1516. (channel->state == CH_STATE_RCD_DONE ||
  1517. channel->state == CH_STATE_DOWN));
  1518. if (channel->state == CH_STATE_DOWN)
  1519. ret = -EIO;
  1520. else
  1521. channel->state = CH_STATE_DOWN;
  1522. if (ret) {
  1523. kfree(rcd_buf);
  1524. *buffer = NULL;
  1525. *length = 0;
  1526. } else {
  1527. *length = ciw->count;
  1528. *buffer = rcd_buf;
  1529. }
  1530. return ret;
  1531. }
  1532. static void qeth_configure_unitaddr(struct qeth_card *card, char *prcd)
  1533. {
  1534. QETH_DBF_TEXT(SETUP, 2, "cfgunit");
  1535. card->info.chpid = prcd[30];
  1536. card->info.unit_addr2 = prcd[31];
  1537. card->info.cula = prcd[63];
  1538. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1539. (prcd[0x11] == _ascebc['M']));
  1540. }
  1541. static void qeth_configure_blkt_default(struct qeth_card *card, char *prcd)
  1542. {
  1543. QETH_DBF_TEXT(SETUP, 2, "cfgblkt");
  1544. if (prcd[74] == 0xF0 && prcd[75] == 0xF0 &&
  1545. prcd[76] >= 0xF1 && prcd[76] <= 0xF4) {
  1546. card->info.blkt.time_total = 0;
  1547. card->info.blkt.inter_packet = 0;
  1548. card->info.blkt.inter_packet_jumbo = 0;
  1549. } else {
  1550. card->info.blkt.time_total = 250;
  1551. card->info.blkt.inter_packet = 5;
  1552. card->info.blkt.inter_packet_jumbo = 15;
  1553. }
  1554. }
  1555. static void qeth_init_tokens(struct qeth_card *card)
  1556. {
  1557. card->token.issuer_rm_w = 0x00010103UL;
  1558. card->token.cm_filter_w = 0x00010108UL;
  1559. card->token.cm_connection_w = 0x0001010aUL;
  1560. card->token.ulp_filter_w = 0x0001010bUL;
  1561. card->token.ulp_connection_w = 0x0001010dUL;
  1562. }
  1563. static void qeth_init_func_level(struct qeth_card *card)
  1564. {
  1565. switch (card->info.type) {
  1566. case QETH_CARD_TYPE_IQD:
  1567. card->info.func_level = QETH_IDX_FUNC_LEVEL_IQD;
  1568. break;
  1569. case QETH_CARD_TYPE_OSD:
  1570. case QETH_CARD_TYPE_OSN:
  1571. card->info.func_level = QETH_IDX_FUNC_LEVEL_OSD;
  1572. break;
  1573. default:
  1574. break;
  1575. }
  1576. }
  1577. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1578. void (*idx_reply_cb)(struct qeth_channel *,
  1579. struct qeth_cmd_buffer *))
  1580. {
  1581. struct qeth_cmd_buffer *iob;
  1582. unsigned long flags;
  1583. int rc;
  1584. struct qeth_card *card;
  1585. QETH_DBF_TEXT(SETUP, 2, "idxanswr");
  1586. card = CARD_FROM_CDEV(channel->ccwdev);
  1587. iob = qeth_get_buffer(channel);
  1588. if (!iob)
  1589. return -ENOMEM;
  1590. iob->callback = idx_reply_cb;
  1591. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1592. channel->ccw.count = QETH_BUFSIZE;
  1593. channel->ccw.cda = (__u32) __pa(iob->data);
  1594. wait_event(card->wait_q,
  1595. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1596. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1597. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1598. rc = ccw_device_start(channel->ccwdev,
  1599. &channel->ccw, (addr_t) iob, 0, 0);
  1600. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1601. if (rc) {
  1602. QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
  1603. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1604. atomic_set(&channel->irq_pending, 0);
  1605. wake_up(&card->wait_q);
  1606. return rc;
  1607. }
  1608. rc = wait_event_interruptible_timeout(card->wait_q,
  1609. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1610. if (rc == -ERESTARTSYS)
  1611. return rc;
  1612. if (channel->state != CH_STATE_UP) {
  1613. rc = -ETIME;
  1614. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1615. qeth_clear_cmd_buffers(channel);
  1616. } else
  1617. rc = 0;
  1618. return rc;
  1619. }
  1620. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1621. void (*idx_reply_cb)(struct qeth_channel *,
  1622. struct qeth_cmd_buffer *))
  1623. {
  1624. struct qeth_card *card;
  1625. struct qeth_cmd_buffer *iob;
  1626. unsigned long flags;
  1627. __u16 temp;
  1628. __u8 tmp;
  1629. int rc;
  1630. struct ccw_dev_id temp_devid;
  1631. card = CARD_FROM_CDEV(channel->ccwdev);
  1632. QETH_DBF_TEXT(SETUP, 2, "idxactch");
  1633. iob = qeth_get_buffer(channel);
  1634. if (!iob)
  1635. return -ENOMEM;
  1636. iob->callback = idx_reply_cb;
  1637. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1638. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1639. channel->ccw.cda = (__u32) __pa(iob->data);
  1640. if (channel == &card->write) {
  1641. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1642. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1643. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1644. card->seqno.trans_hdr++;
  1645. } else {
  1646. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1647. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1648. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1649. }
  1650. tmp = ((__u8)card->info.portno) | 0x80;
  1651. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1652. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1653. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1654. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1655. &card->info.func_level, sizeof(__u16));
  1656. ccw_device_get_id(CARD_DDEV(card), &temp_devid);
  1657. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
  1658. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1659. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1660. wait_event(card->wait_q,
  1661. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1662. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1663. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1664. rc = ccw_device_start(channel->ccwdev,
  1665. &channel->ccw, (addr_t) iob, 0, 0);
  1666. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1667. if (rc) {
  1668. QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
  1669. rc);
  1670. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1671. atomic_set(&channel->irq_pending, 0);
  1672. wake_up(&card->wait_q);
  1673. return rc;
  1674. }
  1675. rc = wait_event_interruptible_timeout(card->wait_q,
  1676. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1677. if (rc == -ERESTARTSYS)
  1678. return rc;
  1679. if (channel->state != CH_STATE_ACTIVATING) {
  1680. dev_warn(&channel->ccwdev->dev, "The qeth device driver"
  1681. " failed to recover an error on the device\n");
  1682. QETH_DBF_MESSAGE(2, "%s IDX activate timed out\n",
  1683. dev_name(&channel->ccwdev->dev));
  1684. QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
  1685. qeth_clear_cmd_buffers(channel);
  1686. return -ETIME;
  1687. }
  1688. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1689. }
  1690. static int qeth_peer_func_level(int level)
  1691. {
  1692. if ((level & 0xff) == 8)
  1693. return (level & 0xff) + 0x400;
  1694. if (((level >> 8) & 3) == 1)
  1695. return (level & 0xff) + 0x200;
  1696. return level;
  1697. }
  1698. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1699. struct qeth_cmd_buffer *iob)
  1700. {
  1701. struct qeth_card *card;
  1702. __u16 temp;
  1703. QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
  1704. if (channel->state == CH_STATE_DOWN) {
  1705. channel->state = CH_STATE_ACTIVATING;
  1706. goto out;
  1707. }
  1708. card = CARD_FROM_CDEV(channel->ccwdev);
  1709. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1710. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == QETH_IDX_ACT_ERR_EXCL)
  1711. dev_err(&card->write.ccwdev->dev,
  1712. "The adapter is used exclusively by another "
  1713. "host\n");
  1714. else
  1715. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel:"
  1716. " negative reply\n",
  1717. dev_name(&card->write.ccwdev->dev));
  1718. goto out;
  1719. }
  1720. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1721. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1722. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel: "
  1723. "function level mismatch (sent: 0x%x, received: "
  1724. "0x%x)\n", dev_name(&card->write.ccwdev->dev),
  1725. card->info.func_level, temp);
  1726. goto out;
  1727. }
  1728. channel->state = CH_STATE_UP;
  1729. out:
  1730. qeth_release_buffer(channel, iob);
  1731. }
  1732. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1733. struct qeth_cmd_buffer *iob)
  1734. {
  1735. struct qeth_card *card;
  1736. __u16 temp;
  1737. QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
  1738. if (channel->state == CH_STATE_DOWN) {
  1739. channel->state = CH_STATE_ACTIVATING;
  1740. goto out;
  1741. }
  1742. card = CARD_FROM_CDEV(channel->ccwdev);
  1743. if (qeth_check_idx_response(card, iob->data))
  1744. goto out;
  1745. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1746. switch (QETH_IDX_ACT_CAUSE_CODE(iob->data)) {
  1747. case QETH_IDX_ACT_ERR_EXCL:
  1748. dev_err(&card->write.ccwdev->dev,
  1749. "The adapter is used exclusively by another "
  1750. "host\n");
  1751. break;
  1752. case QETH_IDX_ACT_ERR_AUTH:
  1753. case QETH_IDX_ACT_ERR_AUTH_USER:
  1754. dev_err(&card->read.ccwdev->dev,
  1755. "Setting the device online failed because of "
  1756. "insufficient authorization\n");
  1757. break;
  1758. default:
  1759. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel:"
  1760. " negative reply\n",
  1761. dev_name(&card->read.ccwdev->dev));
  1762. }
  1763. QETH_CARD_TEXT_(card, 2, "idxread%c",
  1764. QETH_IDX_ACT_CAUSE_CODE(iob->data));
  1765. goto out;
  1766. }
  1767. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1768. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1769. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel: function "
  1770. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1771. dev_name(&card->read.ccwdev->dev),
  1772. card->info.func_level, temp);
  1773. goto out;
  1774. }
  1775. memcpy(&card->token.issuer_rm_r,
  1776. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1777. QETH_MPC_TOKEN_LENGTH);
  1778. memcpy(&card->info.mcl_level[0],
  1779. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1780. channel->state = CH_STATE_UP;
  1781. out:
  1782. qeth_release_buffer(channel, iob);
  1783. }
  1784. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1785. struct qeth_cmd_buffer *iob)
  1786. {
  1787. qeth_setup_ccw(&card->write, iob->data, len);
  1788. iob->callback = qeth_release_buffer;
  1789. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1790. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1791. card->seqno.trans_hdr++;
  1792. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1793. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1794. card->seqno.pdu_hdr++;
  1795. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1796. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1797. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1798. }
  1799. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1800. /**
  1801. * qeth_send_control_data() - send control command to the card
  1802. * @card: qeth_card structure pointer
  1803. * @len: size of the command buffer
  1804. * @iob: qeth_cmd_buffer pointer
  1805. * @reply_cb: callback function pointer
  1806. * @cb_card: pointer to the qeth_card structure
  1807. * @cb_reply: pointer to the qeth_reply structure
  1808. * @cb_cmd: pointer to the original iob for non-IPA
  1809. * commands, or to the qeth_ipa_cmd structure
  1810. * for the IPA commands.
  1811. * @reply_param: private pointer passed to the callback
  1812. *
  1813. * Returns the value of the `return_code' field of the response
  1814. * block returned from the hardware, or other error indication.
  1815. * Value of zero indicates successful execution of the command.
  1816. *
  1817. * Callback function gets called one or more times, with cb_cmd
  1818. * pointing to the response returned by the hardware. Callback
  1819. * function must return non-zero if more reply blocks are expected,
  1820. * and zero if the last or only reply block is received. Callback
  1821. * function can get the value of the reply_param pointer from the
  1822. * field 'param' of the structure qeth_reply.
  1823. */
  1824. int qeth_send_control_data(struct qeth_card *card, int len,
  1825. struct qeth_cmd_buffer *iob,
  1826. int (*reply_cb)(struct qeth_card *cb_card,
  1827. struct qeth_reply *cb_reply,
  1828. unsigned long cb_cmd),
  1829. void *reply_param)
  1830. {
  1831. int rc;
  1832. unsigned long flags;
  1833. struct qeth_reply *reply = NULL;
  1834. unsigned long timeout, event_timeout;
  1835. struct qeth_ipa_cmd *cmd;
  1836. QETH_CARD_TEXT(card, 2, "sendctl");
  1837. if (card->read_or_write_problem) {
  1838. qeth_release_buffer(iob->channel, iob);
  1839. return -EIO;
  1840. }
  1841. reply = qeth_alloc_reply(card);
  1842. if (!reply) {
  1843. return -ENOMEM;
  1844. }
  1845. reply->callback = reply_cb;
  1846. reply->param = reply_param;
  1847. if (card->state == CARD_STATE_DOWN)
  1848. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1849. else
  1850. reply->seqno = card->seqno.ipa++;
  1851. init_waitqueue_head(&reply->wait_q);
  1852. spin_lock_irqsave(&card->lock, flags);
  1853. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1854. spin_unlock_irqrestore(&card->lock, flags);
  1855. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1856. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1857. qeth_prepare_control_data(card, len, iob);
  1858. if (IS_IPA(iob->data))
  1859. event_timeout = QETH_IPA_TIMEOUT;
  1860. else
  1861. event_timeout = QETH_TIMEOUT;
  1862. timeout = jiffies + event_timeout;
  1863. QETH_CARD_TEXT(card, 6, "noirqpnd");
  1864. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1865. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1866. (addr_t) iob, 0, 0);
  1867. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1868. if (rc) {
  1869. QETH_DBF_MESSAGE(2, "%s qeth_send_control_data: "
  1870. "ccw_device_start rc = %i\n",
  1871. dev_name(&card->write.ccwdev->dev), rc);
  1872. QETH_CARD_TEXT_(card, 2, " err%d", rc);
  1873. spin_lock_irqsave(&card->lock, flags);
  1874. list_del_init(&reply->list);
  1875. qeth_put_reply(reply);
  1876. spin_unlock_irqrestore(&card->lock, flags);
  1877. qeth_release_buffer(iob->channel, iob);
  1878. atomic_set(&card->write.irq_pending, 0);
  1879. wake_up(&card->wait_q);
  1880. return rc;
  1881. }
  1882. /* we have only one long running ipassist, since we can ensure
  1883. process context of this command we can sleep */
  1884. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  1885. if ((cmd->hdr.command == IPA_CMD_SETIP) &&
  1886. (cmd->hdr.prot_version == QETH_PROT_IPV4)) {
  1887. if (!wait_event_timeout(reply->wait_q,
  1888. atomic_read(&reply->received), event_timeout))
  1889. goto time_err;
  1890. } else {
  1891. while (!atomic_read(&reply->received)) {
  1892. if (time_after(jiffies, timeout))
  1893. goto time_err;
  1894. cpu_relax();
  1895. }
  1896. }
  1897. if (reply->rc == -EIO)
  1898. goto error;
  1899. rc = reply->rc;
  1900. qeth_put_reply(reply);
  1901. return rc;
  1902. time_err:
  1903. reply->rc = -ETIME;
  1904. spin_lock_irqsave(&reply->card->lock, flags);
  1905. list_del_init(&reply->list);
  1906. spin_unlock_irqrestore(&reply->card->lock, flags);
  1907. atomic_inc(&reply->received);
  1908. error:
  1909. atomic_set(&card->write.irq_pending, 0);
  1910. qeth_release_buffer(iob->channel, iob);
  1911. card->write.buf_no = (card->write.buf_no + 1) % QETH_CMD_BUFFER_NO;
  1912. rc = reply->rc;
  1913. qeth_put_reply(reply);
  1914. return rc;
  1915. }
  1916. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1917. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1918. unsigned long data)
  1919. {
  1920. struct qeth_cmd_buffer *iob;
  1921. QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
  1922. iob = (struct qeth_cmd_buffer *) data;
  1923. memcpy(&card->token.cm_filter_r,
  1924. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1925. QETH_MPC_TOKEN_LENGTH);
  1926. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1927. return 0;
  1928. }
  1929. static int qeth_cm_enable(struct qeth_card *card)
  1930. {
  1931. int rc;
  1932. struct qeth_cmd_buffer *iob;
  1933. QETH_DBF_TEXT(SETUP, 2, "cmenable");
  1934. iob = qeth_wait_for_buffer(&card->write);
  1935. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1936. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1937. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1938. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1939. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1940. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1941. qeth_cm_enable_cb, NULL);
  1942. return rc;
  1943. }
  1944. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1945. unsigned long data)
  1946. {
  1947. struct qeth_cmd_buffer *iob;
  1948. QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
  1949. iob = (struct qeth_cmd_buffer *) data;
  1950. memcpy(&card->token.cm_connection_r,
  1951. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1952. QETH_MPC_TOKEN_LENGTH);
  1953. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1954. return 0;
  1955. }
  1956. static int qeth_cm_setup(struct qeth_card *card)
  1957. {
  1958. int rc;
  1959. struct qeth_cmd_buffer *iob;
  1960. QETH_DBF_TEXT(SETUP, 2, "cmsetup");
  1961. iob = qeth_wait_for_buffer(&card->write);
  1962. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1963. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1964. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1965. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1966. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1967. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1968. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1969. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1970. qeth_cm_setup_cb, NULL);
  1971. return rc;
  1972. }
  1973. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1974. {
  1975. switch (card->info.type) {
  1976. case QETH_CARD_TYPE_UNKNOWN:
  1977. return 1500;
  1978. case QETH_CARD_TYPE_IQD:
  1979. return card->info.max_mtu;
  1980. case QETH_CARD_TYPE_OSD:
  1981. switch (card->info.link_type) {
  1982. case QETH_LINK_TYPE_HSTR:
  1983. case QETH_LINK_TYPE_LANE_TR:
  1984. return 2000;
  1985. default:
  1986. return card->options.layer2 ? 1500 : 1492;
  1987. }
  1988. case QETH_CARD_TYPE_OSM:
  1989. case QETH_CARD_TYPE_OSX:
  1990. return card->options.layer2 ? 1500 : 1492;
  1991. default:
  1992. return 1500;
  1993. }
  1994. }
  1995. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1996. {
  1997. switch (framesize) {
  1998. case 0x4000:
  1999. return 8192;
  2000. case 0x6000:
  2001. return 16384;
  2002. case 0xa000:
  2003. return 32768;
  2004. case 0xffff:
  2005. return 57344;
  2006. default:
  2007. return 0;
  2008. }
  2009. }
  2010. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  2011. {
  2012. switch (card->info.type) {
  2013. case QETH_CARD_TYPE_OSD:
  2014. case QETH_CARD_TYPE_OSM:
  2015. case QETH_CARD_TYPE_OSX:
  2016. case QETH_CARD_TYPE_IQD:
  2017. return ((mtu >= 576) &&
  2018. (mtu <= card->info.max_mtu));
  2019. case QETH_CARD_TYPE_OSN:
  2020. case QETH_CARD_TYPE_UNKNOWN:
  2021. default:
  2022. return 1;
  2023. }
  2024. }
  2025. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  2026. unsigned long data)
  2027. {
  2028. __u16 mtu, framesize;
  2029. __u16 len;
  2030. __u8 link_type;
  2031. struct qeth_cmd_buffer *iob;
  2032. QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
  2033. iob = (struct qeth_cmd_buffer *) data;
  2034. memcpy(&card->token.ulp_filter_r,
  2035. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  2036. QETH_MPC_TOKEN_LENGTH);
  2037. if (card->info.type == QETH_CARD_TYPE_IQD) {
  2038. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  2039. mtu = qeth_get_mtu_outof_framesize(framesize);
  2040. if (!mtu) {
  2041. iob->rc = -EINVAL;
  2042. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  2043. return 0;
  2044. }
  2045. if (card->info.initial_mtu && (card->info.initial_mtu != mtu)) {
  2046. /* frame size has changed */
  2047. if (card->dev &&
  2048. ((card->dev->mtu == card->info.initial_mtu) ||
  2049. (card->dev->mtu > mtu)))
  2050. card->dev->mtu = mtu;
  2051. qeth_free_qdio_buffers(card);
  2052. }
  2053. card->info.initial_mtu = mtu;
  2054. card->info.max_mtu = mtu;
  2055. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  2056. } else {
  2057. card->info.max_mtu = *(__u16 *)QETH_ULP_ENABLE_RESP_MAX_MTU(
  2058. iob->data);
  2059. card->info.initial_mtu = min(card->info.max_mtu,
  2060. qeth_get_initial_mtu_for_card(card));
  2061. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  2062. }
  2063. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  2064. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  2065. memcpy(&link_type,
  2066. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  2067. card->info.link_type = link_type;
  2068. } else
  2069. card->info.link_type = 0;
  2070. QETH_DBF_TEXT_(SETUP, 2, "link%d", card->info.link_type);
  2071. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  2072. return 0;
  2073. }
  2074. static int qeth_ulp_enable(struct qeth_card *card)
  2075. {
  2076. int rc;
  2077. char prot_type;
  2078. struct qeth_cmd_buffer *iob;
  2079. /*FIXME: trace view callbacks*/
  2080. QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
  2081. iob = qeth_wait_for_buffer(&card->write);
  2082. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  2083. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  2084. (__u8) card->info.portno;
  2085. if (card->options.layer2)
  2086. if (card->info.type == QETH_CARD_TYPE_OSN)
  2087. prot_type = QETH_PROT_OSN2;
  2088. else
  2089. prot_type = QETH_PROT_LAYER2;
  2090. else
  2091. prot_type = QETH_PROT_TCPIP;
  2092. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  2093. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  2094. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  2095. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  2096. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  2097. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  2098. qeth_ulp_enable_cb, NULL);
  2099. return rc;
  2100. }
  2101. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  2102. unsigned long data)
  2103. {
  2104. struct qeth_cmd_buffer *iob;
  2105. QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
  2106. iob = (struct qeth_cmd_buffer *) data;
  2107. memcpy(&card->token.ulp_connection_r,
  2108. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  2109. QETH_MPC_TOKEN_LENGTH);
  2110. if (!strncmp("00S", QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  2111. 3)) {
  2112. QETH_DBF_TEXT(SETUP, 2, "olmlimit");
  2113. dev_err(&card->gdev->dev, "A connection could not be "
  2114. "established because of an OLM limit\n");
  2115. iob->rc = -EMLINK;
  2116. }
  2117. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  2118. return 0;
  2119. }
  2120. static int qeth_ulp_setup(struct qeth_card *card)
  2121. {
  2122. int rc;
  2123. __u16 temp;
  2124. struct qeth_cmd_buffer *iob;
  2125. struct ccw_dev_id dev_id;
  2126. QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
  2127. iob = qeth_wait_for_buffer(&card->write);
  2128. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  2129. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  2130. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  2131. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  2132. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  2133. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  2134. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  2135. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  2136. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  2137. temp = (card->info.cula << 8) + card->info.unit_addr2;
  2138. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  2139. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  2140. qeth_ulp_setup_cb, NULL);
  2141. return rc;
  2142. }
  2143. static int qeth_init_qdio_out_buf(struct qeth_qdio_out_q *q, int bidx)
  2144. {
  2145. int rc;
  2146. struct qeth_qdio_out_buffer *newbuf;
  2147. rc = 0;
  2148. newbuf = kmem_cache_zalloc(qeth_qdio_outbuf_cache, GFP_ATOMIC);
  2149. if (!newbuf) {
  2150. rc = -ENOMEM;
  2151. goto out;
  2152. }
  2153. newbuf->buffer = q->qdio_bufs[bidx];
  2154. skb_queue_head_init(&newbuf->skb_list);
  2155. lockdep_set_class(&newbuf->skb_list.lock, &qdio_out_skb_queue_key);
  2156. newbuf->q = q;
  2157. newbuf->aob = NULL;
  2158. newbuf->next_pending = q->bufs[bidx];
  2159. atomic_set(&newbuf->state, QETH_QDIO_BUF_EMPTY);
  2160. q->bufs[bidx] = newbuf;
  2161. if (q->bufstates) {
  2162. q->bufstates[bidx].user = newbuf;
  2163. QETH_CARD_TEXT_(q->card, 2, "nbs%d", bidx);
  2164. QETH_CARD_TEXT_(q->card, 2, "%lx", (long) newbuf);
  2165. QETH_CARD_TEXT_(q->card, 2, "%lx",
  2166. (long) newbuf->next_pending);
  2167. }
  2168. out:
  2169. return rc;
  2170. }
  2171. static void qeth_free_qdio_out_buf(struct qeth_qdio_out_q *q)
  2172. {
  2173. if (!q)
  2174. return;
  2175. qdio_free_buffers(q->qdio_bufs, QDIO_MAX_BUFFERS_PER_Q);
  2176. kfree(q);
  2177. }
  2178. static struct qeth_qdio_out_q *qeth_alloc_qdio_out_buf(void)
  2179. {
  2180. struct qeth_qdio_out_q *q = kzalloc(sizeof(*q), GFP_KERNEL);
  2181. if (!q)
  2182. return NULL;
  2183. if (qdio_alloc_buffers(q->qdio_bufs, QDIO_MAX_BUFFERS_PER_Q)) {
  2184. kfree(q);
  2185. return NULL;
  2186. }
  2187. return q;
  2188. }
  2189. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  2190. {
  2191. int i, j;
  2192. QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
  2193. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  2194. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  2195. return 0;
  2196. QETH_DBF_TEXT(SETUP, 2, "inq");
  2197. card->qdio.in_q = qeth_alloc_qdio_queue();
  2198. if (!card->qdio.in_q)
  2199. goto out_nomem;
  2200. /* inbound buffer pool */
  2201. if (qeth_alloc_buffer_pool(card))
  2202. goto out_freeinq;
  2203. /* outbound */
  2204. card->qdio.out_qs =
  2205. kzalloc(card->qdio.no_out_queues *
  2206. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  2207. if (!card->qdio.out_qs)
  2208. goto out_freepool;
  2209. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2210. card->qdio.out_qs[i] = qeth_alloc_qdio_out_buf();
  2211. if (!card->qdio.out_qs[i])
  2212. goto out_freeoutq;
  2213. QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
  2214. QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
  2215. card->qdio.out_qs[i]->queue_no = i;
  2216. /* give outbound qeth_qdio_buffers their qdio_buffers */
  2217. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2218. WARN_ON(card->qdio.out_qs[i]->bufs[j] != NULL);
  2219. if (qeth_init_qdio_out_buf(card->qdio.out_qs[i], j))
  2220. goto out_freeoutqbufs;
  2221. }
  2222. }
  2223. /* completion */
  2224. if (qeth_alloc_cq(card))
  2225. goto out_freeoutq;
  2226. return 0;
  2227. out_freeoutqbufs:
  2228. while (j > 0) {
  2229. --j;
  2230. kmem_cache_free(qeth_qdio_outbuf_cache,
  2231. card->qdio.out_qs[i]->bufs[j]);
  2232. card->qdio.out_qs[i]->bufs[j] = NULL;
  2233. }
  2234. out_freeoutq:
  2235. while (i > 0) {
  2236. qeth_free_qdio_out_buf(card->qdio.out_qs[--i]);
  2237. qeth_clear_outq_buffers(card->qdio.out_qs[i], 1);
  2238. }
  2239. kfree(card->qdio.out_qs);
  2240. card->qdio.out_qs = NULL;
  2241. out_freepool:
  2242. qeth_free_buffer_pool(card);
  2243. out_freeinq:
  2244. qeth_free_qdio_queue(card->qdio.in_q);
  2245. card->qdio.in_q = NULL;
  2246. out_nomem:
  2247. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  2248. return -ENOMEM;
  2249. }
  2250. static void qeth_free_qdio_buffers(struct qeth_card *card)
  2251. {
  2252. int i, j;
  2253. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  2254. QETH_QDIO_UNINITIALIZED)
  2255. return;
  2256. qeth_free_cq(card);
  2257. cancel_delayed_work_sync(&card->buffer_reclaim_work);
  2258. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2259. if (card->qdio.in_q->bufs[j].rx_skb)
  2260. dev_kfree_skb_any(card->qdio.in_q->bufs[j].rx_skb);
  2261. }
  2262. qeth_free_qdio_queue(card->qdio.in_q);
  2263. card->qdio.in_q = NULL;
  2264. /* inbound buffer pool */
  2265. qeth_free_buffer_pool(card);
  2266. /* free outbound qdio_qs */
  2267. if (card->qdio.out_qs) {
  2268. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2269. qeth_clear_outq_buffers(card->qdio.out_qs[i], 1);
  2270. qeth_free_qdio_out_buf(card->qdio.out_qs[i]);
  2271. }
  2272. kfree(card->qdio.out_qs);
  2273. card->qdio.out_qs = NULL;
  2274. }
  2275. }
  2276. static void qeth_create_qib_param_field(struct qeth_card *card,
  2277. char *param_field)
  2278. {
  2279. param_field[0] = _ascebc['P'];
  2280. param_field[1] = _ascebc['C'];
  2281. param_field[2] = _ascebc['I'];
  2282. param_field[3] = _ascebc['T'];
  2283. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  2284. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  2285. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  2286. }
  2287. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  2288. char *param_field)
  2289. {
  2290. param_field[16] = _ascebc['B'];
  2291. param_field[17] = _ascebc['L'];
  2292. param_field[18] = _ascebc['K'];
  2293. param_field[19] = _ascebc['T'];
  2294. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  2295. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  2296. *((unsigned int *) (&param_field[28])) =
  2297. card->info.blkt.inter_packet_jumbo;
  2298. }
  2299. static int qeth_qdio_activate(struct qeth_card *card)
  2300. {
  2301. QETH_DBF_TEXT(SETUP, 3, "qdioact");
  2302. return qdio_activate(CARD_DDEV(card));
  2303. }
  2304. static int qeth_dm_act(struct qeth_card *card)
  2305. {
  2306. int rc;
  2307. struct qeth_cmd_buffer *iob;
  2308. QETH_DBF_TEXT(SETUP, 2, "dmact");
  2309. iob = qeth_wait_for_buffer(&card->write);
  2310. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  2311. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  2312. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  2313. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  2314. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2315. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  2316. return rc;
  2317. }
  2318. static int qeth_mpc_initialize(struct qeth_card *card)
  2319. {
  2320. int rc;
  2321. QETH_DBF_TEXT(SETUP, 2, "mpcinit");
  2322. rc = qeth_issue_next_read(card);
  2323. if (rc) {
  2324. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2325. return rc;
  2326. }
  2327. rc = qeth_cm_enable(card);
  2328. if (rc) {
  2329. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  2330. goto out_qdio;
  2331. }
  2332. rc = qeth_cm_setup(card);
  2333. if (rc) {
  2334. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  2335. goto out_qdio;
  2336. }
  2337. rc = qeth_ulp_enable(card);
  2338. if (rc) {
  2339. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  2340. goto out_qdio;
  2341. }
  2342. rc = qeth_ulp_setup(card);
  2343. if (rc) {
  2344. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  2345. goto out_qdio;
  2346. }
  2347. rc = qeth_alloc_qdio_buffers(card);
  2348. if (rc) {
  2349. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  2350. goto out_qdio;
  2351. }
  2352. rc = qeth_qdio_establish(card);
  2353. if (rc) {
  2354. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  2355. qeth_free_qdio_buffers(card);
  2356. goto out_qdio;
  2357. }
  2358. rc = qeth_qdio_activate(card);
  2359. if (rc) {
  2360. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  2361. goto out_qdio;
  2362. }
  2363. rc = qeth_dm_act(card);
  2364. if (rc) {
  2365. QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
  2366. goto out_qdio;
  2367. }
  2368. return 0;
  2369. out_qdio:
  2370. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  2371. qdio_free(CARD_DDEV(card));
  2372. return rc;
  2373. }
  2374. void qeth_print_status_message(struct qeth_card *card)
  2375. {
  2376. switch (card->info.type) {
  2377. case QETH_CARD_TYPE_OSD:
  2378. case QETH_CARD_TYPE_OSM:
  2379. case QETH_CARD_TYPE_OSX:
  2380. /* VM will use a non-zero first character
  2381. * to indicate a HiperSockets like reporting
  2382. * of the level OSA sets the first character to zero
  2383. * */
  2384. if (!card->info.mcl_level[0]) {
  2385. sprintf(card->info.mcl_level, "%02x%02x",
  2386. card->info.mcl_level[2],
  2387. card->info.mcl_level[3]);
  2388. break;
  2389. }
  2390. /* fallthrough */
  2391. case QETH_CARD_TYPE_IQD:
  2392. if ((card->info.guestlan) ||
  2393. (card->info.mcl_level[0] & 0x80)) {
  2394. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  2395. card->info.mcl_level[0]];
  2396. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  2397. card->info.mcl_level[1]];
  2398. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  2399. card->info.mcl_level[2]];
  2400. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2401. card->info.mcl_level[3]];
  2402. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2403. }
  2404. break;
  2405. default:
  2406. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2407. }
  2408. dev_info(&card->gdev->dev,
  2409. "Device is a%s card%s%s%s\nwith link type %s.\n",
  2410. qeth_get_cardname(card),
  2411. (card->info.mcl_level[0]) ? " (level: " : "",
  2412. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2413. (card->info.mcl_level[0]) ? ")" : "",
  2414. qeth_get_cardname_short(card));
  2415. }
  2416. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2417. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2418. {
  2419. struct qeth_buffer_pool_entry *entry;
  2420. QETH_CARD_TEXT(card, 5, "inwrklst");
  2421. list_for_each_entry(entry,
  2422. &card->qdio.init_pool.entry_list, init_list) {
  2423. qeth_put_buffer_pool_entry(card, entry);
  2424. }
  2425. }
  2426. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2427. struct qeth_card *card)
  2428. {
  2429. struct list_head *plh;
  2430. struct qeth_buffer_pool_entry *entry;
  2431. int i, free;
  2432. struct page *page;
  2433. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2434. return NULL;
  2435. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2436. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2437. free = 1;
  2438. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2439. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2440. free = 0;
  2441. break;
  2442. }
  2443. }
  2444. if (free) {
  2445. list_del_init(&entry->list);
  2446. return entry;
  2447. }
  2448. }
  2449. /* no free buffer in pool so take first one and swap pages */
  2450. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2451. struct qeth_buffer_pool_entry, list);
  2452. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2453. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2454. page = alloc_page(GFP_ATOMIC);
  2455. if (!page) {
  2456. return NULL;
  2457. } else {
  2458. free_page((unsigned long)entry->elements[i]);
  2459. entry->elements[i] = page_address(page);
  2460. if (card->options.performance_stats)
  2461. card->perf_stats.sg_alloc_page_rx++;
  2462. }
  2463. }
  2464. }
  2465. list_del_init(&entry->list);
  2466. return entry;
  2467. }
  2468. static int qeth_init_input_buffer(struct qeth_card *card,
  2469. struct qeth_qdio_buffer *buf)
  2470. {
  2471. struct qeth_buffer_pool_entry *pool_entry;
  2472. int i;
  2473. if ((card->options.cq == QETH_CQ_ENABLED) && (!buf->rx_skb)) {
  2474. buf->rx_skb = dev_alloc_skb(QETH_RX_PULL_LEN + ETH_HLEN);
  2475. if (!buf->rx_skb)
  2476. return 1;
  2477. }
  2478. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2479. if (!pool_entry)
  2480. return 1;
  2481. /*
  2482. * since the buffer is accessed only from the input_tasklet
  2483. * there shouldn't be a need to synchronize; also, since we use
  2484. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2485. * buffers
  2486. */
  2487. buf->pool_entry = pool_entry;
  2488. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2489. buf->buffer->element[i].length = PAGE_SIZE;
  2490. buf->buffer->element[i].addr = pool_entry->elements[i];
  2491. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2492. buf->buffer->element[i].eflags = SBAL_EFLAGS_LAST_ENTRY;
  2493. else
  2494. buf->buffer->element[i].eflags = 0;
  2495. buf->buffer->element[i].sflags = 0;
  2496. }
  2497. return 0;
  2498. }
  2499. int qeth_init_qdio_queues(struct qeth_card *card)
  2500. {
  2501. int i, j;
  2502. int rc;
  2503. QETH_DBF_TEXT(SETUP, 2, "initqdqs");
  2504. /* inbound queue */
  2505. qdio_reset_buffers(card->qdio.in_q->qdio_bufs,
  2506. QDIO_MAX_BUFFERS_PER_Q);
  2507. qeth_initialize_working_pool_list(card);
  2508. /*give only as many buffers to hardware as we have buffer pool entries*/
  2509. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2510. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2511. card->qdio.in_q->next_buf_to_init =
  2512. card->qdio.in_buf_pool.buf_count - 1;
  2513. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2514. card->qdio.in_buf_pool.buf_count - 1);
  2515. if (rc) {
  2516. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2517. return rc;
  2518. }
  2519. /* completion */
  2520. rc = qeth_cq_init(card);
  2521. if (rc) {
  2522. return rc;
  2523. }
  2524. /* outbound queue */
  2525. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2526. qdio_reset_buffers(card->qdio.out_qs[i]->qdio_bufs,
  2527. QDIO_MAX_BUFFERS_PER_Q);
  2528. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2529. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2530. card->qdio.out_qs[i]->bufs[j],
  2531. QETH_QDIO_BUF_EMPTY);
  2532. }
  2533. card->qdio.out_qs[i]->card = card;
  2534. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2535. card->qdio.out_qs[i]->do_pack = 0;
  2536. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2537. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2538. atomic_set(&card->qdio.out_qs[i]->state,
  2539. QETH_OUT_Q_UNLOCKED);
  2540. }
  2541. return 0;
  2542. }
  2543. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2544. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2545. {
  2546. switch (link_type) {
  2547. case QETH_LINK_TYPE_HSTR:
  2548. return 2;
  2549. default:
  2550. return 1;
  2551. }
  2552. }
  2553. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2554. struct qeth_ipa_cmd *cmd, __u8 command,
  2555. enum qeth_prot_versions prot)
  2556. {
  2557. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2558. cmd->hdr.command = command;
  2559. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2560. cmd->hdr.seqno = card->seqno.ipa;
  2561. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2562. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2563. if (card->options.layer2)
  2564. cmd->hdr.prim_version_no = 2;
  2565. else
  2566. cmd->hdr.prim_version_no = 1;
  2567. cmd->hdr.param_count = 1;
  2568. cmd->hdr.prot_version = prot;
  2569. cmd->hdr.ipa_supported = 0;
  2570. cmd->hdr.ipa_enabled = 0;
  2571. }
  2572. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2573. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2574. {
  2575. struct qeth_cmd_buffer *iob;
  2576. struct qeth_ipa_cmd *cmd;
  2577. iob = qeth_get_buffer(&card->write);
  2578. if (iob) {
  2579. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2580. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2581. } else {
  2582. dev_warn(&card->gdev->dev,
  2583. "The qeth driver ran out of channel command buffers\n");
  2584. QETH_DBF_MESSAGE(1, "%s The qeth driver ran out of channel command buffers",
  2585. dev_name(&card->gdev->dev));
  2586. }
  2587. return iob;
  2588. }
  2589. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2590. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2591. char prot_type)
  2592. {
  2593. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2594. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2595. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2596. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2597. }
  2598. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2599. /**
  2600. * qeth_send_ipa_cmd() - send an IPA command
  2601. *
  2602. * See qeth_send_control_data() for explanation of the arguments.
  2603. */
  2604. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2605. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2606. unsigned long),
  2607. void *reply_param)
  2608. {
  2609. int rc;
  2610. char prot_type;
  2611. QETH_CARD_TEXT(card, 4, "sendipa");
  2612. if (card->options.layer2)
  2613. if (card->info.type == QETH_CARD_TYPE_OSN)
  2614. prot_type = QETH_PROT_OSN2;
  2615. else
  2616. prot_type = QETH_PROT_LAYER2;
  2617. else
  2618. prot_type = QETH_PROT_TCPIP;
  2619. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2620. rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
  2621. iob, reply_cb, reply_param);
  2622. if (rc == -ETIME) {
  2623. qeth_clear_ipacmd_list(card);
  2624. qeth_schedule_recovery(card);
  2625. }
  2626. return rc;
  2627. }
  2628. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2629. int qeth_send_startlan(struct qeth_card *card)
  2630. {
  2631. int rc;
  2632. struct qeth_cmd_buffer *iob;
  2633. QETH_DBF_TEXT(SETUP, 2, "strtlan");
  2634. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_STARTLAN, 0);
  2635. if (!iob)
  2636. return -ENOMEM;
  2637. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2638. return rc;
  2639. }
  2640. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2641. static int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2642. struct qeth_reply *reply, unsigned long data)
  2643. {
  2644. struct qeth_ipa_cmd *cmd;
  2645. QETH_CARD_TEXT(card, 4, "defadpcb");
  2646. cmd = (struct qeth_ipa_cmd *) data;
  2647. if (cmd->hdr.return_code == 0)
  2648. cmd->hdr.return_code =
  2649. cmd->data.setadapterparms.hdr.return_code;
  2650. return 0;
  2651. }
  2652. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2653. struct qeth_reply *reply, unsigned long data)
  2654. {
  2655. struct qeth_ipa_cmd *cmd;
  2656. QETH_CARD_TEXT(card, 3, "quyadpcb");
  2657. cmd = (struct qeth_ipa_cmd *) data;
  2658. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f) {
  2659. card->info.link_type =
  2660. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2661. QETH_DBF_TEXT_(SETUP, 2, "lnk %d", card->info.link_type);
  2662. }
  2663. card->options.adp.supported_funcs =
  2664. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2665. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2666. }
  2667. static struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2668. __u32 command, __u32 cmdlen)
  2669. {
  2670. struct qeth_cmd_buffer *iob;
  2671. struct qeth_ipa_cmd *cmd;
  2672. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2673. QETH_PROT_IPV4);
  2674. if (iob) {
  2675. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2676. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2677. cmd->data.setadapterparms.hdr.command_code = command;
  2678. cmd->data.setadapterparms.hdr.used_total = 1;
  2679. cmd->data.setadapterparms.hdr.seq_no = 1;
  2680. }
  2681. return iob;
  2682. }
  2683. int qeth_query_setadapterparms(struct qeth_card *card)
  2684. {
  2685. int rc;
  2686. struct qeth_cmd_buffer *iob;
  2687. QETH_CARD_TEXT(card, 3, "queryadp");
  2688. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2689. sizeof(struct qeth_ipacmd_setadpparms));
  2690. if (!iob)
  2691. return -ENOMEM;
  2692. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2693. return rc;
  2694. }
  2695. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2696. static int qeth_query_ipassists_cb(struct qeth_card *card,
  2697. struct qeth_reply *reply, unsigned long data)
  2698. {
  2699. struct qeth_ipa_cmd *cmd;
  2700. QETH_DBF_TEXT(SETUP, 2, "qipasscb");
  2701. cmd = (struct qeth_ipa_cmd *) data;
  2702. switch (cmd->hdr.return_code) {
  2703. case IPA_RC_NOTSUPP:
  2704. case IPA_RC_L2_UNSUPPORTED_CMD:
  2705. QETH_DBF_TEXT(SETUP, 2, "ipaunsup");
  2706. card->options.ipa4.supported_funcs |= IPA_SETADAPTERPARMS;
  2707. card->options.ipa6.supported_funcs |= IPA_SETADAPTERPARMS;
  2708. return -0;
  2709. default:
  2710. if (cmd->hdr.return_code) {
  2711. QETH_DBF_MESSAGE(1, "%s IPA_CMD_QIPASSIST: Unhandled "
  2712. "rc=%d\n",
  2713. dev_name(&card->gdev->dev),
  2714. cmd->hdr.return_code);
  2715. return 0;
  2716. }
  2717. }
  2718. if (cmd->hdr.prot_version == QETH_PROT_IPV4) {
  2719. card->options.ipa4.supported_funcs = cmd->hdr.ipa_supported;
  2720. card->options.ipa4.enabled_funcs = cmd->hdr.ipa_enabled;
  2721. } else if (cmd->hdr.prot_version == QETH_PROT_IPV6) {
  2722. card->options.ipa6.supported_funcs = cmd->hdr.ipa_supported;
  2723. card->options.ipa6.enabled_funcs = cmd->hdr.ipa_enabled;
  2724. } else
  2725. QETH_DBF_MESSAGE(1, "%s IPA_CMD_QIPASSIST: Flawed LIC detected"
  2726. "\n", dev_name(&card->gdev->dev));
  2727. return 0;
  2728. }
  2729. int qeth_query_ipassists(struct qeth_card *card, enum qeth_prot_versions prot)
  2730. {
  2731. int rc;
  2732. struct qeth_cmd_buffer *iob;
  2733. QETH_DBF_TEXT_(SETUP, 2, "qipassi%i", prot);
  2734. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_QIPASSIST, prot);
  2735. if (!iob)
  2736. return -ENOMEM;
  2737. rc = qeth_send_ipa_cmd(card, iob, qeth_query_ipassists_cb, NULL);
  2738. return rc;
  2739. }
  2740. EXPORT_SYMBOL_GPL(qeth_query_ipassists);
  2741. static int qeth_query_switch_attributes_cb(struct qeth_card *card,
  2742. struct qeth_reply *reply, unsigned long data)
  2743. {
  2744. struct qeth_ipa_cmd *cmd;
  2745. struct qeth_switch_info *sw_info;
  2746. struct qeth_query_switch_attributes *attrs;
  2747. QETH_CARD_TEXT(card, 2, "qswiatcb");
  2748. cmd = (struct qeth_ipa_cmd *) data;
  2749. sw_info = (struct qeth_switch_info *)reply->param;
  2750. if (cmd->data.setadapterparms.hdr.return_code == 0) {
  2751. attrs = &cmd->data.setadapterparms.data.query_switch_attributes;
  2752. sw_info->capabilities = attrs->capabilities;
  2753. sw_info->settings = attrs->settings;
  2754. QETH_CARD_TEXT_(card, 2, "%04x%04x", sw_info->capabilities,
  2755. sw_info->settings);
  2756. }
  2757. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  2758. return 0;
  2759. }
  2760. int qeth_query_switch_attributes(struct qeth_card *card,
  2761. struct qeth_switch_info *sw_info)
  2762. {
  2763. struct qeth_cmd_buffer *iob;
  2764. QETH_CARD_TEXT(card, 2, "qswiattr");
  2765. if (!qeth_adp_supported(card, IPA_SETADP_QUERY_SWITCH_ATTRIBUTES))
  2766. return -EOPNOTSUPP;
  2767. if (!netif_carrier_ok(card->dev))
  2768. return -ENOMEDIUM;
  2769. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_SWITCH_ATTRIBUTES,
  2770. sizeof(struct qeth_ipacmd_setadpparms_hdr));
  2771. if (!iob)
  2772. return -ENOMEM;
  2773. return qeth_send_ipa_cmd(card, iob,
  2774. qeth_query_switch_attributes_cb, sw_info);
  2775. }
  2776. EXPORT_SYMBOL_GPL(qeth_query_switch_attributes);
  2777. static int qeth_query_setdiagass_cb(struct qeth_card *card,
  2778. struct qeth_reply *reply, unsigned long data)
  2779. {
  2780. struct qeth_ipa_cmd *cmd;
  2781. __u16 rc;
  2782. cmd = (struct qeth_ipa_cmd *)data;
  2783. rc = cmd->hdr.return_code;
  2784. if (rc)
  2785. QETH_CARD_TEXT_(card, 2, "diagq:%x", rc);
  2786. else
  2787. card->info.diagass_support = cmd->data.diagass.ext;
  2788. return 0;
  2789. }
  2790. static int qeth_query_setdiagass(struct qeth_card *card)
  2791. {
  2792. struct qeth_cmd_buffer *iob;
  2793. struct qeth_ipa_cmd *cmd;
  2794. QETH_DBF_TEXT(SETUP, 2, "qdiagass");
  2795. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SET_DIAG_ASS, 0);
  2796. if (!iob)
  2797. return -ENOMEM;
  2798. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2799. cmd->data.diagass.subcmd_len = 16;
  2800. cmd->data.diagass.subcmd = QETH_DIAGS_CMD_QUERY;
  2801. return qeth_send_ipa_cmd(card, iob, qeth_query_setdiagass_cb, NULL);
  2802. }
  2803. static void qeth_get_trap_id(struct qeth_card *card, struct qeth_trap_id *tid)
  2804. {
  2805. unsigned long info = get_zeroed_page(GFP_KERNEL);
  2806. struct sysinfo_2_2_2 *info222 = (struct sysinfo_2_2_2 *)info;
  2807. struct sysinfo_3_2_2 *info322 = (struct sysinfo_3_2_2 *)info;
  2808. struct ccw_dev_id ccwid;
  2809. int level;
  2810. tid->chpid = card->info.chpid;
  2811. ccw_device_get_id(CARD_RDEV(card), &ccwid);
  2812. tid->ssid = ccwid.ssid;
  2813. tid->devno = ccwid.devno;
  2814. if (!info)
  2815. return;
  2816. level = stsi(NULL, 0, 0, 0);
  2817. if ((level >= 2) && (stsi(info222, 2, 2, 2) == 0))
  2818. tid->lparnr = info222->lpar_number;
  2819. if ((level >= 3) && (stsi(info322, 3, 2, 2) == 0)) {
  2820. EBCASC(info322->vm[0].name, sizeof(info322->vm[0].name));
  2821. memcpy(tid->vmname, info322->vm[0].name, sizeof(tid->vmname));
  2822. }
  2823. free_page(info);
  2824. return;
  2825. }
  2826. static int qeth_hw_trap_cb(struct qeth_card *card,
  2827. struct qeth_reply *reply, unsigned long data)
  2828. {
  2829. struct qeth_ipa_cmd *cmd;
  2830. __u16 rc;
  2831. cmd = (struct qeth_ipa_cmd *)data;
  2832. rc = cmd->hdr.return_code;
  2833. if (rc)
  2834. QETH_CARD_TEXT_(card, 2, "trapc:%x", rc);
  2835. return 0;
  2836. }
  2837. int qeth_hw_trap(struct qeth_card *card, enum qeth_diags_trap_action action)
  2838. {
  2839. struct qeth_cmd_buffer *iob;
  2840. struct qeth_ipa_cmd *cmd;
  2841. QETH_DBF_TEXT(SETUP, 2, "diagtrap");
  2842. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SET_DIAG_ASS, 0);
  2843. if (!iob)
  2844. return -ENOMEM;
  2845. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2846. cmd->data.diagass.subcmd_len = 80;
  2847. cmd->data.diagass.subcmd = QETH_DIAGS_CMD_TRAP;
  2848. cmd->data.diagass.type = 1;
  2849. cmd->data.diagass.action = action;
  2850. switch (action) {
  2851. case QETH_DIAGS_TRAP_ARM:
  2852. cmd->data.diagass.options = 0x0003;
  2853. cmd->data.diagass.ext = 0x00010000 +
  2854. sizeof(struct qeth_trap_id);
  2855. qeth_get_trap_id(card,
  2856. (struct qeth_trap_id *)cmd->data.diagass.cdata);
  2857. break;
  2858. case QETH_DIAGS_TRAP_DISARM:
  2859. cmd->data.diagass.options = 0x0001;
  2860. break;
  2861. case QETH_DIAGS_TRAP_CAPTURE:
  2862. break;
  2863. }
  2864. return qeth_send_ipa_cmd(card, iob, qeth_hw_trap_cb, NULL);
  2865. }
  2866. EXPORT_SYMBOL_GPL(qeth_hw_trap);
  2867. int qeth_check_qdio_errors(struct qeth_card *card, struct qdio_buffer *buf,
  2868. unsigned int qdio_error, const char *dbftext)
  2869. {
  2870. if (qdio_error) {
  2871. QETH_CARD_TEXT(card, 2, dbftext);
  2872. QETH_CARD_TEXT_(card, 2, " F15=%02X",
  2873. buf->element[15].sflags);
  2874. QETH_CARD_TEXT_(card, 2, " F14=%02X",
  2875. buf->element[14].sflags);
  2876. QETH_CARD_TEXT_(card, 2, " qerr=%X", qdio_error);
  2877. if ((buf->element[15].sflags) == 0x12) {
  2878. card->stats.rx_dropped++;
  2879. return 0;
  2880. } else
  2881. return 1;
  2882. }
  2883. return 0;
  2884. }
  2885. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2886. static void qeth_buffer_reclaim_work(struct work_struct *work)
  2887. {
  2888. struct qeth_card *card = container_of(work, struct qeth_card,
  2889. buffer_reclaim_work.work);
  2890. QETH_CARD_TEXT_(card, 2, "brw:%x", card->reclaim_index);
  2891. qeth_queue_input_buffer(card, card->reclaim_index);
  2892. }
  2893. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2894. {
  2895. struct qeth_qdio_q *queue = card->qdio.in_q;
  2896. struct list_head *lh;
  2897. int count;
  2898. int i;
  2899. int rc;
  2900. int newcount = 0;
  2901. count = (index < queue->next_buf_to_init)?
  2902. card->qdio.in_buf_pool.buf_count -
  2903. (queue->next_buf_to_init - index) :
  2904. card->qdio.in_buf_pool.buf_count -
  2905. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2906. /* only requeue at a certain threshold to avoid SIGAs */
  2907. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2908. for (i = queue->next_buf_to_init;
  2909. i < queue->next_buf_to_init + count; ++i) {
  2910. if (qeth_init_input_buffer(card,
  2911. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2912. break;
  2913. } else {
  2914. newcount++;
  2915. }
  2916. }
  2917. if (newcount < count) {
  2918. /* we are in memory shortage so we switch back to
  2919. traditional skb allocation and drop packages */
  2920. atomic_set(&card->force_alloc_skb, 3);
  2921. count = newcount;
  2922. } else {
  2923. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2924. }
  2925. if (!count) {
  2926. i = 0;
  2927. list_for_each(lh, &card->qdio.in_buf_pool.entry_list)
  2928. i++;
  2929. if (i == card->qdio.in_buf_pool.buf_count) {
  2930. QETH_CARD_TEXT(card, 2, "qsarbw");
  2931. card->reclaim_index = index;
  2932. schedule_delayed_work(
  2933. &card->buffer_reclaim_work,
  2934. QETH_RECLAIM_WORK_TIME);
  2935. }
  2936. return;
  2937. }
  2938. /*
  2939. * according to old code it should be avoided to requeue all
  2940. * 128 buffers in order to benefit from PCI avoidance.
  2941. * this function keeps at least one buffer (the buffer at
  2942. * 'index') un-requeued -> this buffer is the first buffer that
  2943. * will be requeued the next time
  2944. */
  2945. if (card->options.performance_stats) {
  2946. card->perf_stats.inbound_do_qdio_cnt++;
  2947. card->perf_stats.inbound_do_qdio_start_time =
  2948. qeth_get_micros();
  2949. }
  2950. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
  2951. queue->next_buf_to_init, count);
  2952. if (card->options.performance_stats)
  2953. card->perf_stats.inbound_do_qdio_time +=
  2954. qeth_get_micros() -
  2955. card->perf_stats.inbound_do_qdio_start_time;
  2956. if (rc) {
  2957. QETH_CARD_TEXT(card, 2, "qinberr");
  2958. }
  2959. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2960. QDIO_MAX_BUFFERS_PER_Q;
  2961. }
  2962. }
  2963. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2964. static int qeth_handle_send_error(struct qeth_card *card,
  2965. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
  2966. {
  2967. int sbalf15 = buffer->buffer->element[15].sflags;
  2968. QETH_CARD_TEXT(card, 6, "hdsnderr");
  2969. if (card->info.type == QETH_CARD_TYPE_IQD) {
  2970. if (sbalf15 == 0) {
  2971. qdio_err = 0;
  2972. } else {
  2973. qdio_err = 1;
  2974. }
  2975. }
  2976. qeth_check_qdio_errors(card, buffer->buffer, qdio_err, "qouterr");
  2977. if (!qdio_err)
  2978. return QETH_SEND_ERROR_NONE;
  2979. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2980. return QETH_SEND_ERROR_RETRY;
  2981. QETH_CARD_TEXT(card, 1, "lnkfail");
  2982. QETH_CARD_TEXT_(card, 1, "%04x %02x",
  2983. (u16)qdio_err, (u8)sbalf15);
  2984. return QETH_SEND_ERROR_LINK_FAILURE;
  2985. }
  2986. /*
  2987. * Switched to packing state if the number of used buffers on a queue
  2988. * reaches a certain limit.
  2989. */
  2990. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2991. {
  2992. if (!queue->do_pack) {
  2993. if (atomic_read(&queue->used_buffers)
  2994. >= QETH_HIGH_WATERMARK_PACK){
  2995. /* switch non-PACKING -> PACKING */
  2996. QETH_CARD_TEXT(queue->card, 6, "np->pack");
  2997. if (queue->card->options.performance_stats)
  2998. queue->card->perf_stats.sc_dp_p++;
  2999. queue->do_pack = 1;
  3000. }
  3001. }
  3002. }
  3003. /*
  3004. * Switches from packing to non-packing mode. If there is a packing
  3005. * buffer on the queue this buffer will be prepared to be flushed.
  3006. * In that case 1 is returned to inform the caller. If no buffer
  3007. * has to be flushed, zero is returned.
  3008. */
  3009. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  3010. {
  3011. struct qeth_qdio_out_buffer *buffer;
  3012. int flush_count = 0;
  3013. if (queue->do_pack) {
  3014. if (atomic_read(&queue->used_buffers)
  3015. <= QETH_LOW_WATERMARK_PACK) {
  3016. /* switch PACKING -> non-PACKING */
  3017. QETH_CARD_TEXT(queue->card, 6, "pack->np");
  3018. if (queue->card->options.performance_stats)
  3019. queue->card->perf_stats.sc_p_dp++;
  3020. queue->do_pack = 0;
  3021. /* flush packing buffers */
  3022. buffer = queue->bufs[queue->next_buf_to_fill];
  3023. if ((atomic_read(&buffer->state) ==
  3024. QETH_QDIO_BUF_EMPTY) &&
  3025. (buffer->next_element_to_fill > 0)) {
  3026. atomic_set(&buffer->state,
  3027. QETH_QDIO_BUF_PRIMED);
  3028. flush_count++;
  3029. queue->next_buf_to_fill =
  3030. (queue->next_buf_to_fill + 1) %
  3031. QDIO_MAX_BUFFERS_PER_Q;
  3032. }
  3033. }
  3034. }
  3035. return flush_count;
  3036. }
  3037. /*
  3038. * Called to flush a packing buffer if no more pci flags are on the queue.
  3039. * Checks if there is a packing buffer and prepares it to be flushed.
  3040. * In that case returns 1, otherwise zero.
  3041. */
  3042. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  3043. {
  3044. struct qeth_qdio_out_buffer *buffer;
  3045. buffer = queue->bufs[queue->next_buf_to_fill];
  3046. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  3047. (buffer->next_element_to_fill > 0)) {
  3048. /* it's a packing buffer */
  3049. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  3050. queue->next_buf_to_fill =
  3051. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  3052. return 1;
  3053. }
  3054. return 0;
  3055. }
  3056. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
  3057. int count)
  3058. {
  3059. struct qeth_qdio_out_buffer *buf;
  3060. int rc;
  3061. int i;
  3062. unsigned int qdio_flags;
  3063. for (i = index; i < index + count; ++i) {
  3064. int bidx = i % QDIO_MAX_BUFFERS_PER_Q;
  3065. buf = queue->bufs[bidx];
  3066. buf->buffer->element[buf->next_element_to_fill - 1].eflags |=
  3067. SBAL_EFLAGS_LAST_ENTRY;
  3068. if (queue->bufstates)
  3069. queue->bufstates[bidx].user = buf;
  3070. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  3071. continue;
  3072. if (!queue->do_pack) {
  3073. if ((atomic_read(&queue->used_buffers) >=
  3074. (QETH_HIGH_WATERMARK_PACK -
  3075. QETH_WATERMARK_PACK_FUZZ)) &&
  3076. !atomic_read(&queue->set_pci_flags_count)) {
  3077. /* it's likely that we'll go to packing
  3078. * mode soon */
  3079. atomic_inc(&queue->set_pci_flags_count);
  3080. buf->buffer->element[0].sflags |= SBAL_SFLAGS0_PCI_REQ;
  3081. }
  3082. } else {
  3083. if (!atomic_read(&queue->set_pci_flags_count)) {
  3084. /*
  3085. * there's no outstanding PCI any more, so we
  3086. * have to request a PCI to be sure the the PCI
  3087. * will wake at some time in the future then we
  3088. * can flush packed buffers that might still be
  3089. * hanging around, which can happen if no
  3090. * further send was requested by the stack
  3091. */
  3092. atomic_inc(&queue->set_pci_flags_count);
  3093. buf->buffer->element[0].sflags |= SBAL_SFLAGS0_PCI_REQ;
  3094. }
  3095. }
  3096. }
  3097. netif_trans_update(queue->card->dev);
  3098. if (queue->card->options.performance_stats) {
  3099. queue->card->perf_stats.outbound_do_qdio_cnt++;
  3100. queue->card->perf_stats.outbound_do_qdio_start_time =
  3101. qeth_get_micros();
  3102. }
  3103. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  3104. if (atomic_read(&queue->set_pci_flags_count))
  3105. qdio_flags |= QDIO_FLAG_PCI_OUT;
  3106. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  3107. queue->queue_no, index, count);
  3108. if (queue->card->options.performance_stats)
  3109. queue->card->perf_stats.outbound_do_qdio_time +=
  3110. qeth_get_micros() -
  3111. queue->card->perf_stats.outbound_do_qdio_start_time;
  3112. atomic_add(count, &queue->used_buffers);
  3113. if (rc) {
  3114. queue->card->stats.tx_errors += count;
  3115. /* ignore temporary SIGA errors without busy condition */
  3116. if (rc == -ENOBUFS)
  3117. return;
  3118. QETH_CARD_TEXT(queue->card, 2, "flushbuf");
  3119. QETH_CARD_TEXT_(queue->card, 2, " q%d", queue->queue_no);
  3120. QETH_CARD_TEXT_(queue->card, 2, " idx%d", index);
  3121. QETH_CARD_TEXT_(queue->card, 2, " c%d", count);
  3122. QETH_CARD_TEXT_(queue->card, 2, " err%d", rc);
  3123. /* this must not happen under normal circumstances. if it
  3124. * happens something is really wrong -> recover */
  3125. qeth_schedule_recovery(queue->card);
  3126. return;
  3127. }
  3128. if (queue->card->options.performance_stats)
  3129. queue->card->perf_stats.bufs_sent += count;
  3130. }
  3131. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  3132. {
  3133. int index;
  3134. int flush_cnt = 0;
  3135. int q_was_packing = 0;
  3136. /*
  3137. * check if weed have to switch to non-packing mode or if
  3138. * we have to get a pci flag out on the queue
  3139. */
  3140. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  3141. !atomic_read(&queue->set_pci_flags_count)) {
  3142. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  3143. QETH_OUT_Q_UNLOCKED) {
  3144. /*
  3145. * If we get in here, there was no action in
  3146. * do_send_packet. So, we check if there is a
  3147. * packing buffer to be flushed here.
  3148. */
  3149. netif_stop_queue(queue->card->dev);
  3150. index = queue->next_buf_to_fill;
  3151. q_was_packing = queue->do_pack;
  3152. /* queue->do_pack may change */
  3153. barrier();
  3154. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  3155. if (!flush_cnt &&
  3156. !atomic_read(&queue->set_pci_flags_count))
  3157. flush_cnt +=
  3158. qeth_flush_buffers_on_no_pci(queue);
  3159. if (queue->card->options.performance_stats &&
  3160. q_was_packing)
  3161. queue->card->perf_stats.bufs_sent_pack +=
  3162. flush_cnt;
  3163. if (flush_cnt)
  3164. qeth_flush_buffers(queue, index, flush_cnt);
  3165. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3166. }
  3167. }
  3168. }
  3169. void qeth_qdio_start_poll(struct ccw_device *ccwdev, int queue,
  3170. unsigned long card_ptr)
  3171. {
  3172. struct qeth_card *card = (struct qeth_card *)card_ptr;
  3173. if (card->dev && (card->dev->flags & IFF_UP))
  3174. napi_schedule(&card->napi);
  3175. }
  3176. EXPORT_SYMBOL_GPL(qeth_qdio_start_poll);
  3177. int qeth_configure_cq(struct qeth_card *card, enum qeth_cq cq)
  3178. {
  3179. int rc;
  3180. if (card->options.cq == QETH_CQ_NOTAVAILABLE) {
  3181. rc = -1;
  3182. goto out;
  3183. } else {
  3184. if (card->options.cq == cq) {
  3185. rc = 0;
  3186. goto out;
  3187. }
  3188. if (card->state != CARD_STATE_DOWN &&
  3189. card->state != CARD_STATE_RECOVER) {
  3190. rc = -1;
  3191. goto out;
  3192. }
  3193. qeth_free_qdio_buffers(card);
  3194. card->options.cq = cq;
  3195. rc = 0;
  3196. }
  3197. out:
  3198. return rc;
  3199. }
  3200. EXPORT_SYMBOL_GPL(qeth_configure_cq);
  3201. static void qeth_qdio_cq_handler(struct qeth_card *card,
  3202. unsigned int qdio_err,
  3203. unsigned int queue, int first_element, int count) {
  3204. struct qeth_qdio_q *cq = card->qdio.c_q;
  3205. int i;
  3206. int rc;
  3207. if (!qeth_is_cq(card, queue))
  3208. goto out;
  3209. QETH_CARD_TEXT_(card, 5, "qcqhe%d", first_element);
  3210. QETH_CARD_TEXT_(card, 5, "qcqhc%d", count);
  3211. QETH_CARD_TEXT_(card, 5, "qcqherr%d", qdio_err);
  3212. if (qdio_err) {
  3213. netif_stop_queue(card->dev);
  3214. qeth_schedule_recovery(card);
  3215. goto out;
  3216. }
  3217. if (card->options.performance_stats) {
  3218. card->perf_stats.cq_cnt++;
  3219. card->perf_stats.cq_start_time = qeth_get_micros();
  3220. }
  3221. for (i = first_element; i < first_element + count; ++i) {
  3222. int bidx = i % QDIO_MAX_BUFFERS_PER_Q;
  3223. struct qdio_buffer *buffer = cq->qdio_bufs[bidx];
  3224. int e;
  3225. e = 0;
  3226. while ((e < QDIO_MAX_ELEMENTS_PER_BUFFER) &&
  3227. buffer->element[e].addr) {
  3228. unsigned long phys_aob_addr;
  3229. phys_aob_addr = (unsigned long) buffer->element[e].addr;
  3230. qeth_qdio_handle_aob(card, phys_aob_addr);
  3231. buffer->element[e].addr = NULL;
  3232. buffer->element[e].eflags = 0;
  3233. buffer->element[e].sflags = 0;
  3234. buffer->element[e].length = 0;
  3235. ++e;
  3236. }
  3237. buffer->element[15].eflags = 0;
  3238. buffer->element[15].sflags = 0;
  3239. }
  3240. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, queue,
  3241. card->qdio.c_q->next_buf_to_init,
  3242. count);
  3243. if (rc) {
  3244. dev_warn(&card->gdev->dev,
  3245. "QDIO reported an error, rc=%i\n", rc);
  3246. QETH_CARD_TEXT(card, 2, "qcqherr");
  3247. }
  3248. card->qdio.c_q->next_buf_to_init = (card->qdio.c_q->next_buf_to_init
  3249. + count) % QDIO_MAX_BUFFERS_PER_Q;
  3250. netif_wake_queue(card->dev);
  3251. if (card->options.performance_stats) {
  3252. int delta_t = qeth_get_micros();
  3253. delta_t -= card->perf_stats.cq_start_time;
  3254. card->perf_stats.cq_time += delta_t;
  3255. }
  3256. out:
  3257. return;
  3258. }
  3259. void qeth_qdio_input_handler(struct ccw_device *ccwdev, unsigned int qdio_err,
  3260. unsigned int queue, int first_elem, int count,
  3261. unsigned long card_ptr)
  3262. {
  3263. struct qeth_card *card = (struct qeth_card *)card_ptr;
  3264. QETH_CARD_TEXT_(card, 2, "qihq%d", queue);
  3265. QETH_CARD_TEXT_(card, 2, "qiec%d", qdio_err);
  3266. if (qeth_is_cq(card, queue))
  3267. qeth_qdio_cq_handler(card, qdio_err, queue, first_elem, count);
  3268. else if (qdio_err)
  3269. qeth_schedule_recovery(card);
  3270. }
  3271. EXPORT_SYMBOL_GPL(qeth_qdio_input_handler);
  3272. void qeth_qdio_output_handler(struct ccw_device *ccwdev,
  3273. unsigned int qdio_error, int __queue, int first_element,
  3274. int count, unsigned long card_ptr)
  3275. {
  3276. struct qeth_card *card = (struct qeth_card *) card_ptr;
  3277. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  3278. struct qeth_qdio_out_buffer *buffer;
  3279. int i;
  3280. QETH_CARD_TEXT(card, 6, "qdouhdl");
  3281. if (qdio_error & QDIO_ERROR_FATAL) {
  3282. QETH_CARD_TEXT(card, 2, "achkcond");
  3283. netif_stop_queue(card->dev);
  3284. qeth_schedule_recovery(card);
  3285. return;
  3286. }
  3287. if (card->options.performance_stats) {
  3288. card->perf_stats.outbound_handler_cnt++;
  3289. card->perf_stats.outbound_handler_start_time =
  3290. qeth_get_micros();
  3291. }
  3292. for (i = first_element; i < (first_element + count); ++i) {
  3293. int bidx = i % QDIO_MAX_BUFFERS_PER_Q;
  3294. buffer = queue->bufs[bidx];
  3295. qeth_handle_send_error(card, buffer, qdio_error);
  3296. if (queue->bufstates &&
  3297. (queue->bufstates[bidx].flags &
  3298. QDIO_OUTBUF_STATE_FLAG_PENDING) != 0) {
  3299. WARN_ON_ONCE(card->options.cq != QETH_CQ_ENABLED);
  3300. if (atomic_cmpxchg(&buffer->state,
  3301. QETH_QDIO_BUF_PRIMED,
  3302. QETH_QDIO_BUF_PENDING) ==
  3303. QETH_QDIO_BUF_PRIMED) {
  3304. qeth_notify_skbs(queue, buffer,
  3305. TX_NOTIFY_PENDING);
  3306. }
  3307. buffer->aob = queue->bufstates[bidx].aob;
  3308. QETH_CARD_TEXT_(queue->card, 5, "pel%d", bidx);
  3309. QETH_CARD_TEXT(queue->card, 5, "aob");
  3310. QETH_CARD_TEXT_(queue->card, 5, "%lx",
  3311. virt_to_phys(buffer->aob));
  3312. if (qeth_init_qdio_out_buf(queue, bidx)) {
  3313. QETH_CARD_TEXT(card, 2, "outofbuf");
  3314. qeth_schedule_recovery(card);
  3315. }
  3316. } else {
  3317. if (card->options.cq == QETH_CQ_ENABLED) {
  3318. enum iucv_tx_notify n;
  3319. n = qeth_compute_cq_notification(
  3320. buffer->buffer->element[15].sflags, 0);
  3321. qeth_notify_skbs(queue, buffer, n);
  3322. }
  3323. qeth_clear_output_buffer(queue, buffer,
  3324. QETH_QDIO_BUF_EMPTY);
  3325. }
  3326. qeth_cleanup_handled_pending(queue, bidx, 0);
  3327. }
  3328. atomic_sub(count, &queue->used_buffers);
  3329. /* check if we need to do something on this outbound queue */
  3330. if (card->info.type != QETH_CARD_TYPE_IQD)
  3331. qeth_check_outbound_queue(queue);
  3332. netif_wake_queue(queue->card->dev);
  3333. if (card->options.performance_stats)
  3334. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  3335. card->perf_stats.outbound_handler_start_time;
  3336. }
  3337. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  3338. /* We cannot use outbound queue 3 for unicast packets on HiperSockets */
  3339. static inline int qeth_cut_iqd_prio(struct qeth_card *card, int queue_num)
  3340. {
  3341. if ((card->info.type == QETH_CARD_TYPE_IQD) && (queue_num == 3))
  3342. return 2;
  3343. return queue_num;
  3344. }
  3345. /**
  3346. * Note: Function assumes that we have 4 outbound queues.
  3347. */
  3348. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  3349. int ipv, int cast_type)
  3350. {
  3351. __be16 *tci;
  3352. u8 tos;
  3353. if (cast_type && card->info.is_multicast_different)
  3354. return card->info.is_multicast_different &
  3355. (card->qdio.no_out_queues - 1);
  3356. switch (card->qdio.do_prio_queueing) {
  3357. case QETH_PRIO_Q_ING_TOS:
  3358. case QETH_PRIO_Q_ING_PREC:
  3359. switch (ipv) {
  3360. case 4:
  3361. tos = ipv4_get_dsfield(ip_hdr(skb));
  3362. break;
  3363. case 6:
  3364. tos = ipv6_get_dsfield(ipv6_hdr(skb));
  3365. break;
  3366. default:
  3367. return card->qdio.default_out_queue;
  3368. }
  3369. if (card->qdio.do_prio_queueing == QETH_PRIO_Q_ING_PREC)
  3370. return qeth_cut_iqd_prio(card, ~tos >> 6 & 3);
  3371. if (tos & IPTOS_MINCOST)
  3372. return qeth_cut_iqd_prio(card, 3);
  3373. if (tos & IPTOS_RELIABILITY)
  3374. return 2;
  3375. if (tos & IPTOS_THROUGHPUT)
  3376. return 1;
  3377. if (tos & IPTOS_LOWDELAY)
  3378. return 0;
  3379. break;
  3380. case QETH_PRIO_Q_ING_SKB:
  3381. if (skb->priority > 5)
  3382. return 0;
  3383. return qeth_cut_iqd_prio(card, ~skb->priority >> 1 & 3);
  3384. case QETH_PRIO_Q_ING_VLAN:
  3385. tci = &((struct ethhdr *)skb->data)->h_proto;
  3386. if (*tci == ETH_P_8021Q)
  3387. return qeth_cut_iqd_prio(card, ~*(tci + 1) >>
  3388. (VLAN_PRIO_SHIFT + 1) & 3);
  3389. break;
  3390. default:
  3391. break;
  3392. }
  3393. return card->qdio.default_out_queue;
  3394. }
  3395. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  3396. /**
  3397. * qeth_get_elements_for_frags() - find number of SBALEs for skb frags.
  3398. * @skb: SKB address
  3399. *
  3400. * Returns the number of pages, and thus QDIO buffer elements, needed to cover
  3401. * fragmented part of the SKB. Returns zero for linear SKB.
  3402. */
  3403. int qeth_get_elements_for_frags(struct sk_buff *skb)
  3404. {
  3405. int cnt, elements = 0;
  3406. for (cnt = 0; cnt < skb_shinfo(skb)->nr_frags; cnt++) {
  3407. struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[cnt];
  3408. elements += qeth_get_elements_for_range(
  3409. (addr_t)skb_frag_address(frag),
  3410. (addr_t)skb_frag_address(frag) + skb_frag_size(frag));
  3411. }
  3412. return elements;
  3413. }
  3414. EXPORT_SYMBOL_GPL(qeth_get_elements_for_frags);
  3415. /**
  3416. * qeth_get_elements_no() - find number of SBALEs for skb data, inc. frags.
  3417. * @card: qeth card structure, to check max. elems.
  3418. * @skb: SKB address
  3419. * @extra_elems: extra elems needed, to check against max.
  3420. *
  3421. * Returns the number of pages, and thus QDIO buffer elements, needed to cover
  3422. * skb data, including linear part and fragments. Checks if the result plus
  3423. * extra_elems fits under the limit for the card. Returns 0 if it does not.
  3424. * Note: extra_elems is not included in the returned result.
  3425. */
  3426. int qeth_get_elements_no(struct qeth_card *card,
  3427. struct sk_buff *skb, int extra_elems)
  3428. {
  3429. int elements = qeth_get_elements_for_range(
  3430. (addr_t)skb->data,
  3431. (addr_t)skb->data + skb_headlen(skb)) +
  3432. qeth_get_elements_for_frags(skb);
  3433. if ((elements + extra_elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  3434. QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
  3435. "(Number=%d / Length=%d). Discarded.\n",
  3436. elements + extra_elems, skb->len);
  3437. return 0;
  3438. }
  3439. return elements;
  3440. }
  3441. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  3442. int qeth_hdr_chk_and_bounce(struct sk_buff *skb, struct qeth_hdr **hdr, int len)
  3443. {
  3444. int hroom, inpage, rest;
  3445. if (((unsigned long)skb->data & PAGE_MASK) !=
  3446. (((unsigned long)skb->data + len - 1) & PAGE_MASK)) {
  3447. hroom = skb_headroom(skb);
  3448. inpage = PAGE_SIZE - ((unsigned long) skb->data % PAGE_SIZE);
  3449. rest = len - inpage;
  3450. if (rest > hroom)
  3451. return 1;
  3452. memmove(skb->data - rest, skb->data, skb_headlen(skb));
  3453. skb->data -= rest;
  3454. skb->tail -= rest;
  3455. *hdr = (struct qeth_hdr *)skb->data;
  3456. QETH_DBF_MESSAGE(2, "skb bounce len: %d rest: %d\n", len, rest);
  3457. }
  3458. return 0;
  3459. }
  3460. EXPORT_SYMBOL_GPL(qeth_hdr_chk_and_bounce);
  3461. static inline void __qeth_fill_buffer(struct sk_buff *skb,
  3462. struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,
  3463. int offset)
  3464. {
  3465. int length = skb_headlen(skb);
  3466. int length_here;
  3467. int element;
  3468. char *data;
  3469. int first_lap, cnt;
  3470. struct skb_frag_struct *frag;
  3471. element = *next_element_to_fill;
  3472. data = skb->data;
  3473. first_lap = (is_tso == 0 ? 1 : 0);
  3474. if (offset >= 0) {
  3475. data = skb->data + offset;
  3476. length -= offset;
  3477. first_lap = 0;
  3478. }
  3479. while (length > 0) {
  3480. /* length_here is the remaining amount of data in this page */
  3481. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  3482. if (length < length_here)
  3483. length_here = length;
  3484. buffer->element[element].addr = data;
  3485. buffer->element[element].length = length_here;
  3486. length -= length_here;
  3487. if (!length) {
  3488. if (first_lap)
  3489. if (skb_shinfo(skb)->nr_frags)
  3490. buffer->element[element].eflags =
  3491. SBAL_EFLAGS_FIRST_FRAG;
  3492. else
  3493. buffer->element[element].eflags = 0;
  3494. else
  3495. buffer->element[element].eflags =
  3496. SBAL_EFLAGS_MIDDLE_FRAG;
  3497. } else {
  3498. if (first_lap)
  3499. buffer->element[element].eflags =
  3500. SBAL_EFLAGS_FIRST_FRAG;
  3501. else
  3502. buffer->element[element].eflags =
  3503. SBAL_EFLAGS_MIDDLE_FRAG;
  3504. }
  3505. data += length_here;
  3506. element++;
  3507. first_lap = 0;
  3508. }
  3509. for (cnt = 0; cnt < skb_shinfo(skb)->nr_frags; cnt++) {
  3510. frag = &skb_shinfo(skb)->frags[cnt];
  3511. data = (char *)page_to_phys(skb_frag_page(frag)) +
  3512. frag->page_offset;
  3513. length = frag->size;
  3514. while (length > 0) {
  3515. length_here = PAGE_SIZE -
  3516. ((unsigned long) data % PAGE_SIZE);
  3517. if (length < length_here)
  3518. length_here = length;
  3519. buffer->element[element].addr = data;
  3520. buffer->element[element].length = length_here;
  3521. buffer->element[element].eflags =
  3522. SBAL_EFLAGS_MIDDLE_FRAG;
  3523. length -= length_here;
  3524. data += length_here;
  3525. element++;
  3526. }
  3527. }
  3528. if (buffer->element[element - 1].eflags)
  3529. buffer->element[element - 1].eflags = SBAL_EFLAGS_LAST_FRAG;
  3530. *next_element_to_fill = element;
  3531. }
  3532. static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  3533. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb,
  3534. struct qeth_hdr *hdr, int offset, int hd_len)
  3535. {
  3536. struct qdio_buffer *buffer;
  3537. int flush_cnt = 0, hdr_len, large_send = 0;
  3538. buffer = buf->buffer;
  3539. atomic_inc(&skb->users);
  3540. skb_queue_tail(&buf->skb_list, skb);
  3541. /*check first on TSO ....*/
  3542. if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  3543. int element = buf->next_element_to_fill;
  3544. hdr_len = sizeof(struct qeth_hdr_tso) +
  3545. ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len;
  3546. /*fill first buffer entry only with header information */
  3547. buffer->element[element].addr = skb->data;
  3548. buffer->element[element].length = hdr_len;
  3549. buffer->element[element].eflags = SBAL_EFLAGS_FIRST_FRAG;
  3550. buf->next_element_to_fill++;
  3551. skb->data += hdr_len;
  3552. skb->len -= hdr_len;
  3553. large_send = 1;
  3554. }
  3555. if (offset >= 0) {
  3556. int element = buf->next_element_to_fill;
  3557. buffer->element[element].addr = hdr;
  3558. buffer->element[element].length = sizeof(struct qeth_hdr) +
  3559. hd_len;
  3560. buffer->element[element].eflags = SBAL_EFLAGS_FIRST_FRAG;
  3561. buf->is_header[element] = 1;
  3562. buf->next_element_to_fill++;
  3563. }
  3564. __qeth_fill_buffer(skb, buffer, large_send,
  3565. (int *)&buf->next_element_to_fill, offset);
  3566. if (!queue->do_pack) {
  3567. QETH_CARD_TEXT(queue->card, 6, "fillbfnp");
  3568. /* set state to PRIMED -> will be flushed */
  3569. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  3570. flush_cnt = 1;
  3571. } else {
  3572. QETH_CARD_TEXT(queue->card, 6, "fillbfpa");
  3573. if (queue->card->options.performance_stats)
  3574. queue->card->perf_stats.skbs_sent_pack++;
  3575. if (buf->next_element_to_fill >=
  3576. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  3577. /*
  3578. * packed buffer if full -> set state PRIMED
  3579. * -> will be flushed
  3580. */
  3581. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  3582. flush_cnt = 1;
  3583. }
  3584. }
  3585. return flush_cnt;
  3586. }
  3587. int qeth_do_send_packet_fast(struct qeth_card *card,
  3588. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  3589. struct qeth_hdr *hdr, int elements_needed,
  3590. int offset, int hd_len)
  3591. {
  3592. struct qeth_qdio_out_buffer *buffer;
  3593. int index;
  3594. /* spin until we get the queue ... */
  3595. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  3596. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  3597. /* ... now we've got the queue */
  3598. index = queue->next_buf_to_fill;
  3599. buffer = queue->bufs[queue->next_buf_to_fill];
  3600. /*
  3601. * check if buffer is empty to make sure that we do not 'overtake'
  3602. * ourselves and try to fill a buffer that is already primed
  3603. */
  3604. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  3605. goto out;
  3606. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  3607. QDIO_MAX_BUFFERS_PER_Q;
  3608. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3609. qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len);
  3610. qeth_flush_buffers(queue, index, 1);
  3611. return 0;
  3612. out:
  3613. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3614. return -EBUSY;
  3615. }
  3616. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  3617. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  3618. struct sk_buff *skb, struct qeth_hdr *hdr,
  3619. int elements_needed)
  3620. {
  3621. struct qeth_qdio_out_buffer *buffer;
  3622. int start_index;
  3623. int flush_count = 0;
  3624. int do_pack = 0;
  3625. int tmp;
  3626. int rc = 0;
  3627. /* spin until we get the queue ... */
  3628. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  3629. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  3630. start_index = queue->next_buf_to_fill;
  3631. buffer = queue->bufs[queue->next_buf_to_fill];
  3632. /*
  3633. * check if buffer is empty to make sure that we do not 'overtake'
  3634. * ourselves and try to fill a buffer that is already primed
  3635. */
  3636. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  3637. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3638. return -EBUSY;
  3639. }
  3640. /* check if we need to switch packing state of this queue */
  3641. qeth_switch_to_packing_if_needed(queue);
  3642. if (queue->do_pack) {
  3643. do_pack = 1;
  3644. /* does packet fit in current buffer? */
  3645. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  3646. buffer->next_element_to_fill) < elements_needed) {
  3647. /* ... no -> set state PRIMED */
  3648. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  3649. flush_count++;
  3650. queue->next_buf_to_fill =
  3651. (queue->next_buf_to_fill + 1) %
  3652. QDIO_MAX_BUFFERS_PER_Q;
  3653. buffer = queue->bufs[queue->next_buf_to_fill];
  3654. /* we did a step forward, so check buffer state
  3655. * again */
  3656. if (atomic_read(&buffer->state) !=
  3657. QETH_QDIO_BUF_EMPTY) {
  3658. qeth_flush_buffers(queue, start_index,
  3659. flush_count);
  3660. atomic_set(&queue->state,
  3661. QETH_OUT_Q_UNLOCKED);
  3662. return -EBUSY;
  3663. }
  3664. }
  3665. }
  3666. tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0);
  3667. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  3668. QDIO_MAX_BUFFERS_PER_Q;
  3669. flush_count += tmp;
  3670. if (flush_count)
  3671. qeth_flush_buffers(queue, start_index, flush_count);
  3672. else if (!atomic_read(&queue->set_pci_flags_count))
  3673. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  3674. /*
  3675. * queue->state will go from LOCKED -> UNLOCKED or from
  3676. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  3677. * (switch packing state or flush buffer to get another pci flag out).
  3678. * In that case we will enter this loop
  3679. */
  3680. while (atomic_dec_return(&queue->state)) {
  3681. flush_count = 0;
  3682. start_index = queue->next_buf_to_fill;
  3683. /* check if we can go back to non-packing state */
  3684. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  3685. /*
  3686. * check if we need to flush a packing buffer to get a pci
  3687. * flag out on the queue
  3688. */
  3689. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  3690. flush_count += qeth_flush_buffers_on_no_pci(queue);
  3691. if (flush_count)
  3692. qeth_flush_buffers(queue, start_index, flush_count);
  3693. }
  3694. /* at this point the queue is UNLOCKED again */
  3695. if (queue->card->options.performance_stats && do_pack)
  3696. queue->card->perf_stats.bufs_sent_pack += flush_count;
  3697. return rc;
  3698. }
  3699. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  3700. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  3701. struct qeth_reply *reply, unsigned long data)
  3702. {
  3703. struct qeth_ipa_cmd *cmd;
  3704. struct qeth_ipacmd_setadpparms *setparms;
  3705. QETH_CARD_TEXT(card, 4, "prmadpcb");
  3706. cmd = (struct qeth_ipa_cmd *) data;
  3707. setparms = &(cmd->data.setadapterparms);
  3708. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  3709. if (cmd->hdr.return_code) {
  3710. QETH_CARD_TEXT_(card, 4, "prmrc%x", cmd->hdr.return_code);
  3711. setparms->data.mode = SET_PROMISC_MODE_OFF;
  3712. }
  3713. card->info.promisc_mode = setparms->data.mode;
  3714. return 0;
  3715. }
  3716. void qeth_setadp_promisc_mode(struct qeth_card *card)
  3717. {
  3718. enum qeth_ipa_promisc_modes mode;
  3719. struct net_device *dev = card->dev;
  3720. struct qeth_cmd_buffer *iob;
  3721. struct qeth_ipa_cmd *cmd;
  3722. QETH_CARD_TEXT(card, 4, "setprom");
  3723. if (((dev->flags & IFF_PROMISC) &&
  3724. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  3725. (!(dev->flags & IFF_PROMISC) &&
  3726. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  3727. return;
  3728. mode = SET_PROMISC_MODE_OFF;
  3729. if (dev->flags & IFF_PROMISC)
  3730. mode = SET_PROMISC_MODE_ON;
  3731. QETH_CARD_TEXT_(card, 4, "mode:%x", mode);
  3732. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  3733. sizeof(struct qeth_ipacmd_setadpparms_hdr) + 8);
  3734. if (!iob)
  3735. return;
  3736. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  3737. cmd->data.setadapterparms.data.mode = mode;
  3738. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  3739. }
  3740. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  3741. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  3742. {
  3743. struct qeth_card *card;
  3744. char dbf_text[15];
  3745. card = dev->ml_priv;
  3746. QETH_CARD_TEXT(card, 4, "chgmtu");
  3747. sprintf(dbf_text, "%8x", new_mtu);
  3748. QETH_CARD_TEXT(card, 4, dbf_text);
  3749. if (new_mtu < 64)
  3750. return -EINVAL;
  3751. if (new_mtu > 65535)
  3752. return -EINVAL;
  3753. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  3754. (!qeth_mtu_is_valid(card, new_mtu)))
  3755. return -EINVAL;
  3756. dev->mtu = new_mtu;
  3757. return 0;
  3758. }
  3759. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  3760. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  3761. {
  3762. struct qeth_card *card;
  3763. card = dev->ml_priv;
  3764. QETH_CARD_TEXT(card, 5, "getstat");
  3765. return &card->stats;
  3766. }
  3767. EXPORT_SYMBOL_GPL(qeth_get_stats);
  3768. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  3769. struct qeth_reply *reply, unsigned long data)
  3770. {
  3771. struct qeth_ipa_cmd *cmd;
  3772. QETH_CARD_TEXT(card, 4, "chgmaccb");
  3773. cmd = (struct qeth_ipa_cmd *) data;
  3774. if (!card->options.layer2 ||
  3775. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  3776. memcpy(card->dev->dev_addr,
  3777. &cmd->data.setadapterparms.data.change_addr.addr,
  3778. OSA_ADDR_LEN);
  3779. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  3780. }
  3781. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3782. return 0;
  3783. }
  3784. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3785. {
  3786. int rc;
  3787. struct qeth_cmd_buffer *iob;
  3788. struct qeth_ipa_cmd *cmd;
  3789. QETH_CARD_TEXT(card, 4, "chgmac");
  3790. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3791. sizeof(struct qeth_ipacmd_setadpparms_hdr) +
  3792. sizeof(struct qeth_change_addr));
  3793. if (!iob)
  3794. return -ENOMEM;
  3795. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3796. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3797. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3798. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3799. card->dev->dev_addr, OSA_ADDR_LEN);
  3800. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3801. NULL);
  3802. return rc;
  3803. }
  3804. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3805. static int qeth_setadpparms_set_access_ctrl_cb(struct qeth_card *card,
  3806. struct qeth_reply *reply, unsigned long data)
  3807. {
  3808. struct qeth_ipa_cmd *cmd;
  3809. struct qeth_set_access_ctrl *access_ctrl_req;
  3810. int fallback = *(int *)reply->param;
  3811. QETH_CARD_TEXT(card, 4, "setaccb");
  3812. cmd = (struct qeth_ipa_cmd *) data;
  3813. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3814. QETH_DBF_TEXT_(SETUP, 2, "setaccb");
  3815. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3816. QETH_DBF_TEXT_(SETUP, 2, "rc=%d",
  3817. cmd->data.setadapterparms.hdr.return_code);
  3818. if (cmd->data.setadapterparms.hdr.return_code !=
  3819. SET_ACCESS_CTRL_RC_SUCCESS)
  3820. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_CTRL(%s,%d)==%d\n",
  3821. card->gdev->dev.kobj.name,
  3822. access_ctrl_req->subcmd_code,
  3823. cmd->data.setadapterparms.hdr.return_code);
  3824. switch (cmd->data.setadapterparms.hdr.return_code) {
  3825. case SET_ACCESS_CTRL_RC_SUCCESS:
  3826. if (card->options.isolation == ISOLATION_MODE_NONE) {
  3827. dev_info(&card->gdev->dev,
  3828. "QDIO data connection isolation is deactivated\n");
  3829. } else {
  3830. dev_info(&card->gdev->dev,
  3831. "QDIO data connection isolation is activated\n");
  3832. }
  3833. break;
  3834. case SET_ACCESS_CTRL_RC_ALREADY_NOT_ISOLATED:
  3835. QETH_DBF_MESSAGE(2, "%s QDIO data connection isolation already "
  3836. "deactivated\n", dev_name(&card->gdev->dev));
  3837. if (fallback)
  3838. card->options.isolation = card->options.prev_isolation;
  3839. break;
  3840. case SET_ACCESS_CTRL_RC_ALREADY_ISOLATED:
  3841. QETH_DBF_MESSAGE(2, "%s QDIO data connection isolation already"
  3842. " activated\n", dev_name(&card->gdev->dev));
  3843. if (fallback)
  3844. card->options.isolation = card->options.prev_isolation;
  3845. break;
  3846. case SET_ACCESS_CTRL_RC_NOT_SUPPORTED:
  3847. dev_err(&card->gdev->dev, "Adapter does not "
  3848. "support QDIO data connection isolation\n");
  3849. break;
  3850. case SET_ACCESS_CTRL_RC_NONE_SHARED_ADAPTER:
  3851. dev_err(&card->gdev->dev,
  3852. "Adapter is dedicated. "
  3853. "QDIO data connection isolation not supported\n");
  3854. if (fallback)
  3855. card->options.isolation = card->options.prev_isolation;
  3856. break;
  3857. case SET_ACCESS_CTRL_RC_ACTIVE_CHECKSUM_OFF:
  3858. dev_err(&card->gdev->dev,
  3859. "TSO does not permit QDIO data connection isolation\n");
  3860. if (fallback)
  3861. card->options.isolation = card->options.prev_isolation;
  3862. break;
  3863. case SET_ACCESS_CTRL_RC_REFLREL_UNSUPPORTED:
  3864. dev_err(&card->gdev->dev, "The adjacent switch port does not "
  3865. "support reflective relay mode\n");
  3866. if (fallback)
  3867. card->options.isolation = card->options.prev_isolation;
  3868. break;
  3869. case SET_ACCESS_CTRL_RC_REFLREL_FAILED:
  3870. dev_err(&card->gdev->dev, "The reflective relay mode cannot be "
  3871. "enabled at the adjacent switch port");
  3872. if (fallback)
  3873. card->options.isolation = card->options.prev_isolation;
  3874. break;
  3875. case SET_ACCESS_CTRL_RC_REFLREL_DEACT_FAILED:
  3876. dev_warn(&card->gdev->dev, "Turning off reflective relay mode "
  3877. "at the adjacent switch failed\n");
  3878. break;
  3879. default:
  3880. /* this should never happen */
  3881. if (fallback)
  3882. card->options.isolation = card->options.prev_isolation;
  3883. break;
  3884. }
  3885. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3886. return 0;
  3887. }
  3888. static int qeth_setadpparms_set_access_ctrl(struct qeth_card *card,
  3889. enum qeth_ipa_isolation_modes isolation, int fallback)
  3890. {
  3891. int rc;
  3892. struct qeth_cmd_buffer *iob;
  3893. struct qeth_ipa_cmd *cmd;
  3894. struct qeth_set_access_ctrl *access_ctrl_req;
  3895. QETH_CARD_TEXT(card, 4, "setacctl");
  3896. QETH_DBF_TEXT_(SETUP, 2, "setacctl");
  3897. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3898. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_ACCESS_CONTROL,
  3899. sizeof(struct qeth_ipacmd_setadpparms_hdr) +
  3900. sizeof(struct qeth_set_access_ctrl));
  3901. if (!iob)
  3902. return -ENOMEM;
  3903. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3904. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3905. access_ctrl_req->subcmd_code = isolation;
  3906. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_set_access_ctrl_cb,
  3907. &fallback);
  3908. QETH_DBF_TEXT_(SETUP, 2, "rc=%d", rc);
  3909. return rc;
  3910. }
  3911. int qeth_set_access_ctrl_online(struct qeth_card *card, int fallback)
  3912. {
  3913. int rc = 0;
  3914. QETH_CARD_TEXT(card, 4, "setactlo");
  3915. if ((card->info.type == QETH_CARD_TYPE_OSD ||
  3916. card->info.type == QETH_CARD_TYPE_OSX) &&
  3917. qeth_adp_supported(card, IPA_SETADP_SET_ACCESS_CONTROL)) {
  3918. rc = qeth_setadpparms_set_access_ctrl(card,
  3919. card->options.isolation, fallback);
  3920. if (rc) {
  3921. QETH_DBF_MESSAGE(3,
  3922. "IPA(SET_ACCESS_CTRL,%s,%d) sent failed\n",
  3923. card->gdev->dev.kobj.name,
  3924. rc);
  3925. rc = -EOPNOTSUPP;
  3926. }
  3927. } else if (card->options.isolation != ISOLATION_MODE_NONE) {
  3928. card->options.isolation = ISOLATION_MODE_NONE;
  3929. dev_err(&card->gdev->dev, "Adapter does not "
  3930. "support QDIO data connection isolation\n");
  3931. rc = -EOPNOTSUPP;
  3932. }
  3933. return rc;
  3934. }
  3935. EXPORT_SYMBOL_GPL(qeth_set_access_ctrl_online);
  3936. void qeth_tx_timeout(struct net_device *dev)
  3937. {
  3938. struct qeth_card *card;
  3939. card = dev->ml_priv;
  3940. QETH_CARD_TEXT(card, 4, "txtimeo");
  3941. card->stats.tx_errors++;
  3942. qeth_schedule_recovery(card);
  3943. }
  3944. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3945. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3946. {
  3947. struct qeth_card *card = dev->ml_priv;
  3948. int rc = 0;
  3949. switch (regnum) {
  3950. case MII_BMCR: /* Basic mode control register */
  3951. rc = BMCR_FULLDPLX;
  3952. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3953. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3954. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3955. rc |= BMCR_SPEED100;
  3956. break;
  3957. case MII_BMSR: /* Basic mode status register */
  3958. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3959. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3960. BMSR_100BASE4;
  3961. break;
  3962. case MII_PHYSID1: /* PHYS ID 1 */
  3963. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3964. dev->dev_addr[2];
  3965. rc = (rc >> 5) & 0xFFFF;
  3966. break;
  3967. case MII_PHYSID2: /* PHYS ID 2 */
  3968. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3969. break;
  3970. case MII_ADVERTISE: /* Advertisement control reg */
  3971. rc = ADVERTISE_ALL;
  3972. break;
  3973. case MII_LPA: /* Link partner ability reg */
  3974. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3975. LPA_100BASE4 | LPA_LPACK;
  3976. break;
  3977. case MII_EXPANSION: /* Expansion register */
  3978. break;
  3979. case MII_DCOUNTER: /* disconnect counter */
  3980. break;
  3981. case MII_FCSCOUNTER: /* false carrier counter */
  3982. break;
  3983. case MII_NWAYTEST: /* N-way auto-neg test register */
  3984. break;
  3985. case MII_RERRCOUNTER: /* rx error counter */
  3986. rc = card->stats.rx_errors;
  3987. break;
  3988. case MII_SREVISION: /* silicon revision */
  3989. break;
  3990. case MII_RESV1: /* reserved 1 */
  3991. break;
  3992. case MII_LBRERROR: /* loopback, rx, bypass error */
  3993. break;
  3994. case MII_PHYADDR: /* physical address */
  3995. break;
  3996. case MII_RESV2: /* reserved 2 */
  3997. break;
  3998. case MII_TPISTATUS: /* TPI status for 10mbps */
  3999. break;
  4000. case MII_NCONFIG: /* network interface config */
  4001. break;
  4002. default:
  4003. break;
  4004. }
  4005. return rc;
  4006. }
  4007. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  4008. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  4009. struct qeth_cmd_buffer *iob, int len,
  4010. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  4011. unsigned long),
  4012. void *reply_param)
  4013. {
  4014. u16 s1, s2;
  4015. QETH_CARD_TEXT(card, 4, "sendsnmp");
  4016. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  4017. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  4018. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  4019. /* adjust PDU length fields in IPA_PDU_HEADER */
  4020. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  4021. s2 = (u32) len;
  4022. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  4023. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  4024. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  4025. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  4026. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  4027. reply_cb, reply_param);
  4028. }
  4029. static int qeth_snmp_command_cb(struct qeth_card *card,
  4030. struct qeth_reply *reply, unsigned long sdata)
  4031. {
  4032. struct qeth_ipa_cmd *cmd;
  4033. struct qeth_arp_query_info *qinfo;
  4034. struct qeth_snmp_cmd *snmp;
  4035. unsigned char *data;
  4036. __u16 data_len;
  4037. QETH_CARD_TEXT(card, 3, "snpcmdcb");
  4038. cmd = (struct qeth_ipa_cmd *) sdata;
  4039. data = (unsigned char *)((char *)cmd - reply->offset);
  4040. qinfo = (struct qeth_arp_query_info *) reply->param;
  4041. snmp = &cmd->data.setadapterparms.data.snmp;
  4042. if (cmd->hdr.return_code) {
  4043. QETH_CARD_TEXT_(card, 4, "scer1%x", cmd->hdr.return_code);
  4044. return 0;
  4045. }
  4046. if (cmd->data.setadapterparms.hdr.return_code) {
  4047. cmd->hdr.return_code =
  4048. cmd->data.setadapterparms.hdr.return_code;
  4049. QETH_CARD_TEXT_(card, 4, "scer2%x", cmd->hdr.return_code);
  4050. return 0;
  4051. }
  4052. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  4053. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  4054. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  4055. else
  4056. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  4057. /* check if there is enough room in userspace */
  4058. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  4059. QETH_CARD_TEXT_(card, 4, "scer3%i", -ENOMEM);
  4060. cmd->hdr.return_code = IPA_RC_ENOMEM;
  4061. return 0;
  4062. }
  4063. QETH_CARD_TEXT_(card, 4, "snore%i",
  4064. cmd->data.setadapterparms.hdr.used_total);
  4065. QETH_CARD_TEXT_(card, 4, "sseqn%i",
  4066. cmd->data.setadapterparms.hdr.seq_no);
  4067. /*copy entries to user buffer*/
  4068. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  4069. memcpy(qinfo->udata + qinfo->udata_offset,
  4070. (char *)snmp,
  4071. data_len + offsetof(struct qeth_snmp_cmd, data));
  4072. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  4073. } else {
  4074. memcpy(qinfo->udata + qinfo->udata_offset,
  4075. (char *)&snmp->request, data_len);
  4076. }
  4077. qinfo->udata_offset += data_len;
  4078. /* check if all replies received ... */
  4079. QETH_CARD_TEXT_(card, 4, "srtot%i",
  4080. cmd->data.setadapterparms.hdr.used_total);
  4081. QETH_CARD_TEXT_(card, 4, "srseq%i",
  4082. cmd->data.setadapterparms.hdr.seq_no);
  4083. if (cmd->data.setadapterparms.hdr.seq_no <
  4084. cmd->data.setadapterparms.hdr.used_total)
  4085. return 1;
  4086. return 0;
  4087. }
  4088. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  4089. {
  4090. struct qeth_cmd_buffer *iob;
  4091. struct qeth_ipa_cmd *cmd;
  4092. struct qeth_snmp_ureq *ureq;
  4093. unsigned int req_len;
  4094. struct qeth_arp_query_info qinfo = {0, };
  4095. int rc = 0;
  4096. QETH_CARD_TEXT(card, 3, "snmpcmd");
  4097. if (card->info.guestlan)
  4098. return -EOPNOTSUPP;
  4099. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  4100. (!card->options.layer2)) {
  4101. return -EOPNOTSUPP;
  4102. }
  4103. /* skip 4 bytes (data_len struct member) to get req_len */
  4104. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  4105. return -EFAULT;
  4106. if (req_len > (QETH_BUFSIZE - IPA_PDU_HEADER_SIZE -
  4107. sizeof(struct qeth_ipacmd_hdr) -
  4108. sizeof(struct qeth_ipacmd_setadpparms_hdr)))
  4109. return -EINVAL;
  4110. ureq = memdup_user(udata, req_len + sizeof(struct qeth_snmp_ureq_hdr));
  4111. if (IS_ERR(ureq)) {
  4112. QETH_CARD_TEXT(card, 2, "snmpnome");
  4113. return PTR_ERR(ureq);
  4114. }
  4115. qinfo.udata_len = ureq->hdr.data_len;
  4116. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  4117. if (!qinfo.udata) {
  4118. kfree(ureq);
  4119. return -ENOMEM;
  4120. }
  4121. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  4122. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  4123. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  4124. if (!iob) {
  4125. rc = -ENOMEM;
  4126. goto out;
  4127. }
  4128. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  4129. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  4130. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  4131. qeth_snmp_command_cb, (void *)&qinfo);
  4132. if (rc)
  4133. QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
  4134. QETH_CARD_IFNAME(card), rc);
  4135. else {
  4136. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  4137. rc = -EFAULT;
  4138. }
  4139. out:
  4140. kfree(ureq);
  4141. kfree(qinfo.udata);
  4142. return rc;
  4143. }
  4144. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  4145. static int qeth_setadpparms_query_oat_cb(struct qeth_card *card,
  4146. struct qeth_reply *reply, unsigned long data)
  4147. {
  4148. struct qeth_ipa_cmd *cmd;
  4149. struct qeth_qoat_priv *priv;
  4150. char *resdata;
  4151. int resdatalen;
  4152. QETH_CARD_TEXT(card, 3, "qoatcb");
  4153. cmd = (struct qeth_ipa_cmd *)data;
  4154. priv = (struct qeth_qoat_priv *)reply->param;
  4155. resdatalen = cmd->data.setadapterparms.hdr.cmdlength;
  4156. resdata = (char *)data + 28;
  4157. if (resdatalen > (priv->buffer_len - priv->response_len)) {
  4158. cmd->hdr.return_code = IPA_RC_FFFF;
  4159. return 0;
  4160. }
  4161. memcpy((priv->buffer + priv->response_len), resdata,
  4162. resdatalen);
  4163. priv->response_len += resdatalen;
  4164. if (cmd->data.setadapterparms.hdr.seq_no <
  4165. cmd->data.setadapterparms.hdr.used_total)
  4166. return 1;
  4167. return 0;
  4168. }
  4169. int qeth_query_oat_command(struct qeth_card *card, char __user *udata)
  4170. {
  4171. int rc = 0;
  4172. struct qeth_cmd_buffer *iob;
  4173. struct qeth_ipa_cmd *cmd;
  4174. struct qeth_query_oat *oat_req;
  4175. struct qeth_query_oat_data oat_data;
  4176. struct qeth_qoat_priv priv;
  4177. void __user *tmp;
  4178. QETH_CARD_TEXT(card, 3, "qoatcmd");
  4179. if (!qeth_adp_supported(card, IPA_SETADP_QUERY_OAT)) {
  4180. rc = -EOPNOTSUPP;
  4181. goto out;
  4182. }
  4183. if (copy_from_user(&oat_data, udata,
  4184. sizeof(struct qeth_query_oat_data))) {
  4185. rc = -EFAULT;
  4186. goto out;
  4187. }
  4188. priv.buffer_len = oat_data.buffer_len;
  4189. priv.response_len = 0;
  4190. priv.buffer = kzalloc(oat_data.buffer_len, GFP_KERNEL);
  4191. if (!priv.buffer) {
  4192. rc = -ENOMEM;
  4193. goto out;
  4194. }
  4195. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_OAT,
  4196. sizeof(struct qeth_ipacmd_setadpparms_hdr) +
  4197. sizeof(struct qeth_query_oat));
  4198. if (!iob) {
  4199. rc = -ENOMEM;
  4200. goto out_free;
  4201. }
  4202. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  4203. oat_req = &cmd->data.setadapterparms.data.query_oat;
  4204. oat_req->subcmd_code = oat_data.command;
  4205. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_query_oat_cb,
  4206. &priv);
  4207. if (!rc) {
  4208. if (is_compat_task())
  4209. tmp = compat_ptr(oat_data.ptr);
  4210. else
  4211. tmp = (void __user *)(unsigned long)oat_data.ptr;
  4212. if (copy_to_user(tmp, priv.buffer,
  4213. priv.response_len)) {
  4214. rc = -EFAULT;
  4215. goto out_free;
  4216. }
  4217. oat_data.response_len = priv.response_len;
  4218. if (copy_to_user(udata, &oat_data,
  4219. sizeof(struct qeth_query_oat_data)))
  4220. rc = -EFAULT;
  4221. } else
  4222. if (rc == IPA_RC_FFFF)
  4223. rc = -EFAULT;
  4224. out_free:
  4225. kfree(priv.buffer);
  4226. out:
  4227. return rc;
  4228. }
  4229. EXPORT_SYMBOL_GPL(qeth_query_oat_command);
  4230. static int qeth_query_card_info_cb(struct qeth_card *card,
  4231. struct qeth_reply *reply, unsigned long data)
  4232. {
  4233. struct qeth_ipa_cmd *cmd;
  4234. struct qeth_query_card_info *card_info;
  4235. struct carrier_info *carrier_info;
  4236. QETH_CARD_TEXT(card, 2, "qcrdincb");
  4237. carrier_info = (struct carrier_info *)reply->param;
  4238. cmd = (struct qeth_ipa_cmd *)data;
  4239. card_info = &cmd->data.setadapterparms.data.card_info;
  4240. if (cmd->data.setadapterparms.hdr.return_code == 0) {
  4241. carrier_info->card_type = card_info->card_type;
  4242. carrier_info->port_mode = card_info->port_mode;
  4243. carrier_info->port_speed = card_info->port_speed;
  4244. }
  4245. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  4246. return 0;
  4247. }
  4248. static int qeth_query_card_info(struct qeth_card *card,
  4249. struct carrier_info *carrier_info)
  4250. {
  4251. struct qeth_cmd_buffer *iob;
  4252. QETH_CARD_TEXT(card, 2, "qcrdinfo");
  4253. if (!qeth_adp_supported(card, IPA_SETADP_QUERY_CARD_INFO))
  4254. return -EOPNOTSUPP;
  4255. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_CARD_INFO,
  4256. sizeof(struct qeth_ipacmd_setadpparms_hdr));
  4257. if (!iob)
  4258. return -ENOMEM;
  4259. return qeth_send_ipa_cmd(card, iob, qeth_query_card_info_cb,
  4260. (void *)carrier_info);
  4261. }
  4262. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  4263. {
  4264. switch (card->info.type) {
  4265. case QETH_CARD_TYPE_IQD:
  4266. return 2;
  4267. default:
  4268. return 0;
  4269. }
  4270. }
  4271. static void qeth_determine_capabilities(struct qeth_card *card)
  4272. {
  4273. int rc;
  4274. int length;
  4275. char *prcd;
  4276. struct ccw_device *ddev;
  4277. int ddev_offline = 0;
  4278. QETH_DBF_TEXT(SETUP, 2, "detcapab");
  4279. ddev = CARD_DDEV(card);
  4280. if (!ddev->online) {
  4281. ddev_offline = 1;
  4282. rc = ccw_device_set_online(ddev);
  4283. if (rc) {
  4284. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  4285. goto out;
  4286. }
  4287. }
  4288. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  4289. if (rc) {
  4290. QETH_DBF_MESSAGE(2, "%s qeth_read_conf_data returned %i\n",
  4291. dev_name(&card->gdev->dev), rc);
  4292. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  4293. goto out_offline;
  4294. }
  4295. qeth_configure_unitaddr(card, prcd);
  4296. if (ddev_offline)
  4297. qeth_configure_blkt_default(card, prcd);
  4298. kfree(prcd);
  4299. rc = qdio_get_ssqd_desc(ddev, &card->ssqd);
  4300. if (rc)
  4301. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  4302. QETH_DBF_TEXT_(SETUP, 2, "qfmt%d", card->ssqd.qfmt);
  4303. QETH_DBF_TEXT_(SETUP, 2, "%d", card->ssqd.qdioac1);
  4304. QETH_DBF_TEXT_(SETUP, 2, "%d", card->ssqd.qdioac3);
  4305. QETH_DBF_TEXT_(SETUP, 2, "icnt%d", card->ssqd.icnt);
  4306. if (!((card->ssqd.qfmt != QDIO_IQDIO_QFMT) ||
  4307. ((card->ssqd.qdioac1 & CHSC_AC1_INITIATE_INPUTQ) == 0) ||
  4308. ((card->ssqd.qdioac3 & CHSC_AC3_FORMAT2_CQ_AVAILABLE) == 0))) {
  4309. dev_info(&card->gdev->dev,
  4310. "Completion Queueing supported\n");
  4311. } else {
  4312. card->options.cq = QETH_CQ_NOTAVAILABLE;
  4313. }
  4314. out_offline:
  4315. if (ddev_offline == 1)
  4316. ccw_device_set_offline(ddev);
  4317. out:
  4318. return;
  4319. }
  4320. static inline void qeth_qdio_establish_cq(struct qeth_card *card,
  4321. struct qdio_buffer **in_sbal_ptrs,
  4322. void (**queue_start_poll) (struct ccw_device *, int, unsigned long)) {
  4323. int i;
  4324. if (card->options.cq == QETH_CQ_ENABLED) {
  4325. int offset = QDIO_MAX_BUFFERS_PER_Q *
  4326. (card->qdio.no_in_queues - 1);
  4327. i = QDIO_MAX_BUFFERS_PER_Q * (card->qdio.no_in_queues - 1);
  4328. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i) {
  4329. in_sbal_ptrs[offset + i] = (struct qdio_buffer *)
  4330. virt_to_phys(card->qdio.c_q->bufs[i].buffer);
  4331. }
  4332. queue_start_poll[card->qdio.no_in_queues - 1] = NULL;
  4333. }
  4334. }
  4335. static int qeth_qdio_establish(struct qeth_card *card)
  4336. {
  4337. struct qdio_initialize init_data;
  4338. char *qib_param_field;
  4339. struct qdio_buffer **in_sbal_ptrs;
  4340. void (**queue_start_poll) (struct ccw_device *, int, unsigned long);
  4341. struct qdio_buffer **out_sbal_ptrs;
  4342. int i, j, k;
  4343. int rc = 0;
  4344. QETH_DBF_TEXT(SETUP, 2, "qdioest");
  4345. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  4346. GFP_KERNEL);
  4347. if (!qib_param_field) {
  4348. rc = -ENOMEM;
  4349. goto out_free_nothing;
  4350. }
  4351. qeth_create_qib_param_field(card, qib_param_field);
  4352. qeth_create_qib_param_field_blkt(card, qib_param_field);
  4353. in_sbal_ptrs = kzalloc(card->qdio.no_in_queues *
  4354. QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  4355. GFP_KERNEL);
  4356. if (!in_sbal_ptrs) {
  4357. rc = -ENOMEM;
  4358. goto out_free_qib_param;
  4359. }
  4360. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i) {
  4361. in_sbal_ptrs[i] = (struct qdio_buffer *)
  4362. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  4363. }
  4364. queue_start_poll = kzalloc(sizeof(void *) * card->qdio.no_in_queues,
  4365. GFP_KERNEL);
  4366. if (!queue_start_poll) {
  4367. rc = -ENOMEM;
  4368. goto out_free_in_sbals;
  4369. }
  4370. for (i = 0; i < card->qdio.no_in_queues; ++i)
  4371. queue_start_poll[i] = card->discipline->start_poll;
  4372. qeth_qdio_establish_cq(card, in_sbal_ptrs, queue_start_poll);
  4373. out_sbal_ptrs =
  4374. kzalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  4375. sizeof(void *), GFP_KERNEL);
  4376. if (!out_sbal_ptrs) {
  4377. rc = -ENOMEM;
  4378. goto out_free_queue_start_poll;
  4379. }
  4380. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  4381. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  4382. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  4383. card->qdio.out_qs[i]->bufs[j]->buffer);
  4384. }
  4385. memset(&init_data, 0, sizeof(struct qdio_initialize));
  4386. init_data.cdev = CARD_DDEV(card);
  4387. init_data.q_format = qeth_get_qdio_q_format(card);
  4388. init_data.qib_param_field_format = 0;
  4389. init_data.qib_param_field = qib_param_field;
  4390. init_data.no_input_qs = card->qdio.no_in_queues;
  4391. init_data.no_output_qs = card->qdio.no_out_queues;
  4392. init_data.input_handler = card->discipline->input_handler;
  4393. init_data.output_handler = card->discipline->output_handler;
  4394. init_data.queue_start_poll_array = queue_start_poll;
  4395. init_data.int_parm = (unsigned long) card;
  4396. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  4397. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  4398. init_data.output_sbal_state_array = card->qdio.out_bufstates;
  4399. init_data.scan_threshold =
  4400. (card->info.type == QETH_CARD_TYPE_IQD) ? 1 : 32;
  4401. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  4402. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  4403. rc = qdio_allocate(&init_data);
  4404. if (rc) {
  4405. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  4406. goto out;
  4407. }
  4408. rc = qdio_establish(&init_data);
  4409. if (rc) {
  4410. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  4411. qdio_free(CARD_DDEV(card));
  4412. }
  4413. }
  4414. switch (card->options.cq) {
  4415. case QETH_CQ_ENABLED:
  4416. dev_info(&card->gdev->dev, "Completion Queue support enabled");
  4417. break;
  4418. case QETH_CQ_DISABLED:
  4419. dev_info(&card->gdev->dev, "Completion Queue support disabled");
  4420. break;
  4421. default:
  4422. break;
  4423. }
  4424. out:
  4425. kfree(out_sbal_ptrs);
  4426. out_free_queue_start_poll:
  4427. kfree(queue_start_poll);
  4428. out_free_in_sbals:
  4429. kfree(in_sbal_ptrs);
  4430. out_free_qib_param:
  4431. kfree(qib_param_field);
  4432. out_free_nothing:
  4433. return rc;
  4434. }
  4435. static void qeth_core_free_card(struct qeth_card *card)
  4436. {
  4437. QETH_DBF_TEXT(SETUP, 2, "freecrd");
  4438. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  4439. qeth_clean_channel(&card->read);
  4440. qeth_clean_channel(&card->write);
  4441. if (card->dev)
  4442. free_netdev(card->dev);
  4443. qeth_free_qdio_buffers(card);
  4444. unregister_service_level(&card->qeth_service_level);
  4445. kfree(card);
  4446. }
  4447. void qeth_trace_features(struct qeth_card *card)
  4448. {
  4449. QETH_CARD_TEXT(card, 2, "features");
  4450. QETH_CARD_HEX(card, 2, &card->options.ipa4, sizeof(card->options.ipa4));
  4451. QETH_CARD_HEX(card, 2, &card->options.ipa6, sizeof(card->options.ipa6));
  4452. QETH_CARD_HEX(card, 2, &card->options.adp, sizeof(card->options.adp));
  4453. QETH_CARD_HEX(card, 2, &card->info.diagass_support,
  4454. sizeof(card->info.diagass_support));
  4455. }
  4456. EXPORT_SYMBOL_GPL(qeth_trace_features);
  4457. static struct ccw_device_id qeth_ids[] = {
  4458. {CCW_DEVICE_DEVTYPE(0x1731, 0x01, 0x1732, 0x01),
  4459. .driver_info = QETH_CARD_TYPE_OSD},
  4460. {CCW_DEVICE_DEVTYPE(0x1731, 0x05, 0x1732, 0x05),
  4461. .driver_info = QETH_CARD_TYPE_IQD},
  4462. {CCW_DEVICE_DEVTYPE(0x1731, 0x06, 0x1732, 0x06),
  4463. .driver_info = QETH_CARD_TYPE_OSN},
  4464. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x03),
  4465. .driver_info = QETH_CARD_TYPE_OSM},
  4466. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x02),
  4467. .driver_info = QETH_CARD_TYPE_OSX},
  4468. {},
  4469. };
  4470. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  4471. static struct ccw_driver qeth_ccw_driver = {
  4472. .driver = {
  4473. .owner = THIS_MODULE,
  4474. .name = "qeth",
  4475. },
  4476. .ids = qeth_ids,
  4477. .probe = ccwgroup_probe_ccwdev,
  4478. .remove = ccwgroup_remove_ccwdev,
  4479. };
  4480. int qeth_core_hardsetup_card(struct qeth_card *card)
  4481. {
  4482. int retries = 3;
  4483. int rc;
  4484. QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
  4485. atomic_set(&card->force_alloc_skb, 0);
  4486. qeth_update_from_chp_desc(card);
  4487. retry:
  4488. if (retries < 3)
  4489. QETH_DBF_MESSAGE(2, "%s Retrying to do IDX activates.\n",
  4490. dev_name(&card->gdev->dev));
  4491. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  4492. ccw_device_set_offline(CARD_DDEV(card));
  4493. ccw_device_set_offline(CARD_WDEV(card));
  4494. ccw_device_set_offline(CARD_RDEV(card));
  4495. qdio_free(CARD_DDEV(card));
  4496. rc = ccw_device_set_online(CARD_RDEV(card));
  4497. if (rc)
  4498. goto retriable;
  4499. rc = ccw_device_set_online(CARD_WDEV(card));
  4500. if (rc)
  4501. goto retriable;
  4502. rc = ccw_device_set_online(CARD_DDEV(card));
  4503. if (rc)
  4504. goto retriable;
  4505. retriable:
  4506. if (rc == -ERESTARTSYS) {
  4507. QETH_DBF_TEXT(SETUP, 2, "break1");
  4508. return rc;
  4509. } else if (rc) {
  4510. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  4511. if (--retries < 0)
  4512. goto out;
  4513. else
  4514. goto retry;
  4515. }
  4516. qeth_determine_capabilities(card);
  4517. qeth_init_tokens(card);
  4518. qeth_init_func_level(card);
  4519. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  4520. if (rc == -ERESTARTSYS) {
  4521. QETH_DBF_TEXT(SETUP, 2, "break2");
  4522. return rc;
  4523. } else if (rc) {
  4524. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  4525. if (--retries < 0)
  4526. goto out;
  4527. else
  4528. goto retry;
  4529. }
  4530. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  4531. if (rc == -ERESTARTSYS) {
  4532. QETH_DBF_TEXT(SETUP, 2, "break3");
  4533. return rc;
  4534. } else if (rc) {
  4535. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  4536. if (--retries < 0)
  4537. goto out;
  4538. else
  4539. goto retry;
  4540. }
  4541. card->read_or_write_problem = 0;
  4542. rc = qeth_mpc_initialize(card);
  4543. if (rc) {
  4544. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  4545. goto out;
  4546. }
  4547. card->options.ipa4.supported_funcs = 0;
  4548. card->options.ipa6.supported_funcs = 0;
  4549. card->options.adp.supported_funcs = 0;
  4550. card->options.sbp.supported_funcs = 0;
  4551. card->info.diagass_support = 0;
  4552. rc = qeth_query_ipassists(card, QETH_PROT_IPV4);
  4553. if (rc == -ENOMEM)
  4554. goto out;
  4555. if (qeth_is_supported(card, IPA_SETADAPTERPARMS)) {
  4556. rc = qeth_query_setadapterparms(card);
  4557. if (rc < 0) {
  4558. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  4559. goto out;
  4560. }
  4561. }
  4562. if (qeth_adp_supported(card, IPA_SETADP_SET_DIAG_ASSIST)) {
  4563. rc = qeth_query_setdiagass(card);
  4564. if (rc < 0) {
  4565. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  4566. goto out;
  4567. }
  4568. }
  4569. return 0;
  4570. out:
  4571. dev_warn(&card->gdev->dev, "The qeth device driver failed to recover "
  4572. "an error on the device\n");
  4573. QETH_DBF_MESSAGE(2, "%s Initialization in hardsetup failed! rc=%d\n",
  4574. dev_name(&card->gdev->dev), rc);
  4575. return rc;
  4576. }
  4577. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  4578. static inline int qeth_create_skb_frag(struct qeth_qdio_buffer *qethbuffer,
  4579. struct qdio_buffer_element *element,
  4580. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  4581. {
  4582. struct page *page = virt_to_page(element->addr);
  4583. if (*pskb == NULL) {
  4584. if (qethbuffer->rx_skb) {
  4585. /* only if qeth_card.options.cq == QETH_CQ_ENABLED */
  4586. *pskb = qethbuffer->rx_skb;
  4587. qethbuffer->rx_skb = NULL;
  4588. } else {
  4589. *pskb = dev_alloc_skb(QETH_RX_PULL_LEN + ETH_HLEN);
  4590. if (!(*pskb))
  4591. return -ENOMEM;
  4592. }
  4593. skb_reserve(*pskb, ETH_HLEN);
  4594. if (data_len <= QETH_RX_PULL_LEN) {
  4595. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  4596. data_len);
  4597. } else {
  4598. get_page(page);
  4599. memcpy(skb_put(*pskb, QETH_RX_PULL_LEN),
  4600. element->addr + offset, QETH_RX_PULL_LEN);
  4601. skb_fill_page_desc(*pskb, *pfrag, page,
  4602. offset + QETH_RX_PULL_LEN,
  4603. data_len - QETH_RX_PULL_LEN);
  4604. (*pskb)->data_len += data_len - QETH_RX_PULL_LEN;
  4605. (*pskb)->len += data_len - QETH_RX_PULL_LEN;
  4606. (*pskb)->truesize += data_len - QETH_RX_PULL_LEN;
  4607. (*pfrag)++;
  4608. }
  4609. } else {
  4610. get_page(page);
  4611. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  4612. (*pskb)->data_len += data_len;
  4613. (*pskb)->len += data_len;
  4614. (*pskb)->truesize += data_len;
  4615. (*pfrag)++;
  4616. }
  4617. return 0;
  4618. }
  4619. static inline int qeth_is_last_sbale(struct qdio_buffer_element *sbale)
  4620. {
  4621. return (sbale->eflags & SBAL_EFLAGS_LAST_ENTRY);
  4622. }
  4623. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  4624. struct qeth_qdio_buffer *qethbuffer,
  4625. struct qdio_buffer_element **__element, int *__offset,
  4626. struct qeth_hdr **hdr)
  4627. {
  4628. struct qdio_buffer_element *element = *__element;
  4629. struct qdio_buffer *buffer = qethbuffer->buffer;
  4630. int offset = *__offset;
  4631. struct sk_buff *skb = NULL;
  4632. int skb_len = 0;
  4633. void *data_ptr;
  4634. int data_len;
  4635. int headroom = 0;
  4636. int use_rx_sg = 0;
  4637. int frag = 0;
  4638. /* qeth_hdr must not cross element boundaries */
  4639. if (element->length < offset + sizeof(struct qeth_hdr)) {
  4640. if (qeth_is_last_sbale(element))
  4641. return NULL;
  4642. element++;
  4643. offset = 0;
  4644. if (element->length < sizeof(struct qeth_hdr))
  4645. return NULL;
  4646. }
  4647. *hdr = element->addr + offset;
  4648. offset += sizeof(struct qeth_hdr);
  4649. switch ((*hdr)->hdr.l2.id) {
  4650. case QETH_HEADER_TYPE_LAYER2:
  4651. skb_len = (*hdr)->hdr.l2.pkt_length;
  4652. break;
  4653. case QETH_HEADER_TYPE_LAYER3:
  4654. skb_len = (*hdr)->hdr.l3.length;
  4655. headroom = ETH_HLEN;
  4656. break;
  4657. case QETH_HEADER_TYPE_OSN:
  4658. skb_len = (*hdr)->hdr.osn.pdu_length;
  4659. headroom = sizeof(struct qeth_hdr);
  4660. break;
  4661. default:
  4662. break;
  4663. }
  4664. if (!skb_len)
  4665. return NULL;
  4666. if (((skb_len >= card->options.rx_sg_cb) &&
  4667. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  4668. (!atomic_read(&card->force_alloc_skb))) ||
  4669. (card->options.cq == QETH_CQ_ENABLED)) {
  4670. use_rx_sg = 1;
  4671. } else {
  4672. skb = dev_alloc_skb(skb_len + headroom);
  4673. if (!skb)
  4674. goto no_mem;
  4675. if (headroom)
  4676. skb_reserve(skb, headroom);
  4677. }
  4678. data_ptr = element->addr + offset;
  4679. while (skb_len) {
  4680. data_len = min(skb_len, (int)(element->length - offset));
  4681. if (data_len) {
  4682. if (use_rx_sg) {
  4683. if (qeth_create_skb_frag(qethbuffer, element,
  4684. &skb, offset, &frag, data_len))
  4685. goto no_mem;
  4686. } else {
  4687. memcpy(skb_put(skb, data_len), data_ptr,
  4688. data_len);
  4689. }
  4690. }
  4691. skb_len -= data_len;
  4692. if (skb_len) {
  4693. if (qeth_is_last_sbale(element)) {
  4694. QETH_CARD_TEXT(card, 4, "unexeob");
  4695. QETH_CARD_HEX(card, 2, buffer, sizeof(void *));
  4696. dev_kfree_skb_any(skb);
  4697. card->stats.rx_errors++;
  4698. return NULL;
  4699. }
  4700. element++;
  4701. offset = 0;
  4702. data_ptr = element->addr;
  4703. } else {
  4704. offset += data_len;
  4705. }
  4706. }
  4707. *__element = element;
  4708. *__offset = offset;
  4709. if (use_rx_sg && card->options.performance_stats) {
  4710. card->perf_stats.sg_skbs_rx++;
  4711. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  4712. }
  4713. return skb;
  4714. no_mem:
  4715. if (net_ratelimit()) {
  4716. QETH_CARD_TEXT(card, 2, "noskbmem");
  4717. }
  4718. card->stats.rx_dropped++;
  4719. return NULL;
  4720. }
  4721. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  4722. int qeth_setassparms_cb(struct qeth_card *card,
  4723. struct qeth_reply *reply, unsigned long data)
  4724. {
  4725. struct qeth_ipa_cmd *cmd;
  4726. QETH_CARD_TEXT(card, 4, "defadpcb");
  4727. cmd = (struct qeth_ipa_cmd *) data;
  4728. if (cmd->hdr.return_code == 0) {
  4729. cmd->hdr.return_code = cmd->data.setassparms.hdr.return_code;
  4730. if (cmd->hdr.prot_version == QETH_PROT_IPV4)
  4731. card->options.ipa4.enabled_funcs = cmd->hdr.ipa_enabled;
  4732. if (cmd->hdr.prot_version == QETH_PROT_IPV6)
  4733. card->options.ipa6.enabled_funcs = cmd->hdr.ipa_enabled;
  4734. }
  4735. if (cmd->data.setassparms.hdr.assist_no == IPA_INBOUND_CHECKSUM &&
  4736. cmd->data.setassparms.hdr.command_code == IPA_CMD_ASS_START) {
  4737. card->info.csum_mask = cmd->data.setassparms.data.flags_32bit;
  4738. QETH_CARD_TEXT_(card, 3, "csum:%d", card->info.csum_mask);
  4739. }
  4740. if (cmd->data.setassparms.hdr.assist_no == IPA_OUTBOUND_CHECKSUM &&
  4741. cmd->data.setassparms.hdr.command_code == IPA_CMD_ASS_START) {
  4742. card->info.tx_csum_mask =
  4743. cmd->data.setassparms.data.flags_32bit;
  4744. QETH_CARD_TEXT_(card, 3, "tcsu:%d", card->info.tx_csum_mask);
  4745. }
  4746. return 0;
  4747. }
  4748. EXPORT_SYMBOL_GPL(qeth_setassparms_cb);
  4749. struct qeth_cmd_buffer *qeth_get_setassparms_cmd(struct qeth_card *card,
  4750. enum qeth_ipa_funcs ipa_func,
  4751. __u16 cmd_code, __u16 len,
  4752. enum qeth_prot_versions prot)
  4753. {
  4754. struct qeth_cmd_buffer *iob;
  4755. struct qeth_ipa_cmd *cmd;
  4756. QETH_CARD_TEXT(card, 4, "getasscm");
  4757. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETASSPARMS, prot);
  4758. if (iob) {
  4759. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  4760. cmd->data.setassparms.hdr.assist_no = ipa_func;
  4761. cmd->data.setassparms.hdr.length = 8 + len;
  4762. cmd->data.setassparms.hdr.command_code = cmd_code;
  4763. cmd->data.setassparms.hdr.return_code = 0;
  4764. cmd->data.setassparms.hdr.seq_no = 0;
  4765. }
  4766. return iob;
  4767. }
  4768. EXPORT_SYMBOL_GPL(qeth_get_setassparms_cmd);
  4769. int qeth_send_setassparms(struct qeth_card *card,
  4770. struct qeth_cmd_buffer *iob, __u16 len, long data,
  4771. int (*reply_cb)(struct qeth_card *,
  4772. struct qeth_reply *, unsigned long),
  4773. void *reply_param)
  4774. {
  4775. int rc;
  4776. struct qeth_ipa_cmd *cmd;
  4777. QETH_CARD_TEXT(card, 4, "sendassp");
  4778. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  4779. if (len <= sizeof(__u32))
  4780. cmd->data.setassparms.data.flags_32bit = (__u32) data;
  4781. else /* (len > sizeof(__u32)) */
  4782. memcpy(&cmd->data.setassparms.data, (void *) data, len);
  4783. rc = qeth_send_ipa_cmd(card, iob, reply_cb, reply_param);
  4784. return rc;
  4785. }
  4786. EXPORT_SYMBOL_GPL(qeth_send_setassparms);
  4787. int qeth_send_simple_setassparms(struct qeth_card *card,
  4788. enum qeth_ipa_funcs ipa_func,
  4789. __u16 cmd_code, long data)
  4790. {
  4791. int rc;
  4792. int length = 0;
  4793. struct qeth_cmd_buffer *iob;
  4794. QETH_CARD_TEXT(card, 4, "simassp4");
  4795. if (data)
  4796. length = sizeof(__u32);
  4797. iob = qeth_get_setassparms_cmd(card, ipa_func, cmd_code,
  4798. length, QETH_PROT_IPV4);
  4799. if (!iob)
  4800. return -ENOMEM;
  4801. rc = qeth_send_setassparms(card, iob, length, data,
  4802. qeth_setassparms_cb, NULL);
  4803. return rc;
  4804. }
  4805. EXPORT_SYMBOL_GPL(qeth_send_simple_setassparms);
  4806. static void qeth_unregister_dbf_views(void)
  4807. {
  4808. int x;
  4809. for (x = 0; x < QETH_DBF_INFOS; x++) {
  4810. debug_unregister(qeth_dbf[x].id);
  4811. qeth_dbf[x].id = NULL;
  4812. }
  4813. }
  4814. void qeth_dbf_longtext(debug_info_t *id, int level, char *fmt, ...)
  4815. {
  4816. char dbf_txt_buf[32];
  4817. va_list args;
  4818. if (!debug_level_enabled(id, level))
  4819. return;
  4820. va_start(args, fmt);
  4821. vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
  4822. va_end(args);
  4823. debug_text_event(id, level, dbf_txt_buf);
  4824. }
  4825. EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
  4826. static int qeth_register_dbf_views(void)
  4827. {
  4828. int ret;
  4829. int x;
  4830. for (x = 0; x < QETH_DBF_INFOS; x++) {
  4831. /* register the areas */
  4832. qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
  4833. qeth_dbf[x].pages,
  4834. qeth_dbf[x].areas,
  4835. qeth_dbf[x].len);
  4836. if (qeth_dbf[x].id == NULL) {
  4837. qeth_unregister_dbf_views();
  4838. return -ENOMEM;
  4839. }
  4840. /* register a view */
  4841. ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
  4842. if (ret) {
  4843. qeth_unregister_dbf_views();
  4844. return ret;
  4845. }
  4846. /* set a passing level */
  4847. debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
  4848. }
  4849. return 0;
  4850. }
  4851. int qeth_core_load_discipline(struct qeth_card *card,
  4852. enum qeth_discipline_id discipline)
  4853. {
  4854. int rc = 0;
  4855. mutex_lock(&qeth_mod_mutex);
  4856. switch (discipline) {
  4857. case QETH_DISCIPLINE_LAYER3:
  4858. card->discipline = try_then_request_module(
  4859. symbol_get(qeth_l3_discipline), "qeth_l3");
  4860. break;
  4861. case QETH_DISCIPLINE_LAYER2:
  4862. card->discipline = try_then_request_module(
  4863. symbol_get(qeth_l2_discipline), "qeth_l2");
  4864. break;
  4865. }
  4866. if (!card->discipline) {
  4867. dev_err(&card->gdev->dev, "There is no kernel module to "
  4868. "support discipline %d\n", discipline);
  4869. rc = -EINVAL;
  4870. }
  4871. mutex_unlock(&qeth_mod_mutex);
  4872. return rc;
  4873. }
  4874. void qeth_core_free_discipline(struct qeth_card *card)
  4875. {
  4876. if (card->options.layer2)
  4877. symbol_put(qeth_l2_discipline);
  4878. else
  4879. symbol_put(qeth_l3_discipline);
  4880. card->discipline = NULL;
  4881. }
  4882. static const struct device_type qeth_generic_devtype = {
  4883. .name = "qeth_generic",
  4884. .groups = qeth_generic_attr_groups,
  4885. };
  4886. static const struct device_type qeth_osn_devtype = {
  4887. .name = "qeth_osn",
  4888. .groups = qeth_osn_attr_groups,
  4889. };
  4890. #define DBF_NAME_LEN 20
  4891. struct qeth_dbf_entry {
  4892. char dbf_name[DBF_NAME_LEN];
  4893. debug_info_t *dbf_info;
  4894. struct list_head dbf_list;
  4895. };
  4896. static LIST_HEAD(qeth_dbf_list);
  4897. static DEFINE_MUTEX(qeth_dbf_list_mutex);
  4898. static debug_info_t *qeth_get_dbf_entry(char *name)
  4899. {
  4900. struct qeth_dbf_entry *entry;
  4901. debug_info_t *rc = NULL;
  4902. mutex_lock(&qeth_dbf_list_mutex);
  4903. list_for_each_entry(entry, &qeth_dbf_list, dbf_list) {
  4904. if (strcmp(entry->dbf_name, name) == 0) {
  4905. rc = entry->dbf_info;
  4906. break;
  4907. }
  4908. }
  4909. mutex_unlock(&qeth_dbf_list_mutex);
  4910. return rc;
  4911. }
  4912. static int qeth_add_dbf_entry(struct qeth_card *card, char *name)
  4913. {
  4914. struct qeth_dbf_entry *new_entry;
  4915. card->debug = debug_register(name, 2, 1, 8);
  4916. if (!card->debug) {
  4917. QETH_DBF_TEXT_(SETUP, 2, "%s", "qcdbf");
  4918. goto err;
  4919. }
  4920. if (debug_register_view(card->debug, &debug_hex_ascii_view))
  4921. goto err_dbg;
  4922. new_entry = kzalloc(sizeof(struct qeth_dbf_entry), GFP_KERNEL);
  4923. if (!new_entry)
  4924. goto err_dbg;
  4925. strncpy(new_entry->dbf_name, name, DBF_NAME_LEN);
  4926. new_entry->dbf_info = card->debug;
  4927. mutex_lock(&qeth_dbf_list_mutex);
  4928. list_add(&new_entry->dbf_list, &qeth_dbf_list);
  4929. mutex_unlock(&qeth_dbf_list_mutex);
  4930. return 0;
  4931. err_dbg:
  4932. debug_unregister(card->debug);
  4933. err:
  4934. return -ENOMEM;
  4935. }
  4936. static void qeth_clear_dbf_list(void)
  4937. {
  4938. struct qeth_dbf_entry *entry, *tmp;
  4939. mutex_lock(&qeth_dbf_list_mutex);
  4940. list_for_each_entry_safe(entry, tmp, &qeth_dbf_list, dbf_list) {
  4941. list_del(&entry->dbf_list);
  4942. debug_unregister(entry->dbf_info);
  4943. kfree(entry);
  4944. }
  4945. mutex_unlock(&qeth_dbf_list_mutex);
  4946. }
  4947. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  4948. {
  4949. struct qeth_card *card;
  4950. struct device *dev;
  4951. int rc;
  4952. unsigned long flags;
  4953. char dbf_name[DBF_NAME_LEN];
  4954. QETH_DBF_TEXT(SETUP, 2, "probedev");
  4955. dev = &gdev->dev;
  4956. if (!get_device(dev))
  4957. return -ENODEV;
  4958. QETH_DBF_TEXT_(SETUP, 2, "%s", dev_name(&gdev->dev));
  4959. card = qeth_alloc_card();
  4960. if (!card) {
  4961. QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
  4962. rc = -ENOMEM;
  4963. goto err_dev;
  4964. }
  4965. snprintf(dbf_name, sizeof(dbf_name), "qeth_card_%s",
  4966. dev_name(&gdev->dev));
  4967. card->debug = qeth_get_dbf_entry(dbf_name);
  4968. if (!card->debug) {
  4969. rc = qeth_add_dbf_entry(card, dbf_name);
  4970. if (rc)
  4971. goto err_card;
  4972. }
  4973. card->read.ccwdev = gdev->cdev[0];
  4974. card->write.ccwdev = gdev->cdev[1];
  4975. card->data.ccwdev = gdev->cdev[2];
  4976. dev_set_drvdata(&gdev->dev, card);
  4977. card->gdev = gdev;
  4978. gdev->cdev[0]->handler = qeth_irq;
  4979. gdev->cdev[1]->handler = qeth_irq;
  4980. gdev->cdev[2]->handler = qeth_irq;
  4981. rc = qeth_determine_card_type(card);
  4982. if (rc) {
  4983. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  4984. goto err_card;
  4985. }
  4986. rc = qeth_setup_card(card);
  4987. if (rc) {
  4988. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  4989. goto err_card;
  4990. }
  4991. if (card->info.type == QETH_CARD_TYPE_OSN)
  4992. gdev->dev.type = &qeth_osn_devtype;
  4993. else
  4994. gdev->dev.type = &qeth_generic_devtype;
  4995. switch (card->info.type) {
  4996. case QETH_CARD_TYPE_OSN:
  4997. case QETH_CARD_TYPE_OSM:
  4998. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  4999. if (rc)
  5000. goto err_card;
  5001. rc = card->discipline->setup(card->gdev);
  5002. if (rc)
  5003. goto err_disc;
  5004. case QETH_CARD_TYPE_OSD:
  5005. case QETH_CARD_TYPE_OSX:
  5006. default:
  5007. break;
  5008. }
  5009. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  5010. list_add_tail(&card->list, &qeth_core_card_list.list);
  5011. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  5012. qeth_determine_capabilities(card);
  5013. return 0;
  5014. err_disc:
  5015. qeth_core_free_discipline(card);
  5016. err_card:
  5017. qeth_core_free_card(card);
  5018. err_dev:
  5019. put_device(dev);
  5020. return rc;
  5021. }
  5022. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  5023. {
  5024. unsigned long flags;
  5025. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  5026. QETH_DBF_TEXT(SETUP, 2, "removedv");
  5027. if (card->discipline) {
  5028. card->discipline->remove(gdev);
  5029. qeth_core_free_discipline(card);
  5030. }
  5031. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  5032. list_del(&card->list);
  5033. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  5034. qeth_core_free_card(card);
  5035. dev_set_drvdata(&gdev->dev, NULL);
  5036. put_device(&gdev->dev);
  5037. return;
  5038. }
  5039. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  5040. {
  5041. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  5042. int rc = 0;
  5043. int def_discipline;
  5044. if (!card->discipline) {
  5045. if (card->info.type == QETH_CARD_TYPE_IQD)
  5046. def_discipline = QETH_DISCIPLINE_LAYER3;
  5047. else
  5048. def_discipline = QETH_DISCIPLINE_LAYER2;
  5049. rc = qeth_core_load_discipline(card, def_discipline);
  5050. if (rc)
  5051. goto err;
  5052. rc = card->discipline->setup(card->gdev);
  5053. if (rc)
  5054. goto err;
  5055. }
  5056. rc = card->discipline->set_online(gdev);
  5057. err:
  5058. return rc;
  5059. }
  5060. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  5061. {
  5062. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  5063. return card->discipline->set_offline(gdev);
  5064. }
  5065. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  5066. {
  5067. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  5068. if (card->discipline && card->discipline->shutdown)
  5069. card->discipline->shutdown(gdev);
  5070. }
  5071. static int qeth_core_prepare(struct ccwgroup_device *gdev)
  5072. {
  5073. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  5074. if (card->discipline && card->discipline->prepare)
  5075. return card->discipline->prepare(gdev);
  5076. return 0;
  5077. }
  5078. static void qeth_core_complete(struct ccwgroup_device *gdev)
  5079. {
  5080. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  5081. if (card->discipline && card->discipline->complete)
  5082. card->discipline->complete(gdev);
  5083. }
  5084. static int qeth_core_freeze(struct ccwgroup_device *gdev)
  5085. {
  5086. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  5087. if (card->discipline && card->discipline->freeze)
  5088. return card->discipline->freeze(gdev);
  5089. return 0;
  5090. }
  5091. static int qeth_core_thaw(struct ccwgroup_device *gdev)
  5092. {
  5093. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  5094. if (card->discipline && card->discipline->thaw)
  5095. return card->discipline->thaw(gdev);
  5096. return 0;
  5097. }
  5098. static int qeth_core_restore(struct ccwgroup_device *gdev)
  5099. {
  5100. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  5101. if (card->discipline && card->discipline->restore)
  5102. return card->discipline->restore(gdev);
  5103. return 0;
  5104. }
  5105. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  5106. .driver = {
  5107. .owner = THIS_MODULE,
  5108. .name = "qeth",
  5109. },
  5110. .setup = qeth_core_probe_device,
  5111. .remove = qeth_core_remove_device,
  5112. .set_online = qeth_core_set_online,
  5113. .set_offline = qeth_core_set_offline,
  5114. .shutdown = qeth_core_shutdown,
  5115. .prepare = qeth_core_prepare,
  5116. .complete = qeth_core_complete,
  5117. .freeze = qeth_core_freeze,
  5118. .thaw = qeth_core_thaw,
  5119. .restore = qeth_core_restore,
  5120. };
  5121. static ssize_t qeth_core_driver_group_store(struct device_driver *ddrv,
  5122. const char *buf, size_t count)
  5123. {
  5124. int err;
  5125. err = ccwgroup_create_dev(qeth_core_root_dev,
  5126. &qeth_core_ccwgroup_driver, 3, buf);
  5127. return err ? err : count;
  5128. }
  5129. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  5130. static struct attribute *qeth_drv_attrs[] = {
  5131. &driver_attr_group.attr,
  5132. NULL,
  5133. };
  5134. static struct attribute_group qeth_drv_attr_group = {
  5135. .attrs = qeth_drv_attrs,
  5136. };
  5137. static const struct attribute_group *qeth_drv_attr_groups[] = {
  5138. &qeth_drv_attr_group,
  5139. NULL,
  5140. };
  5141. static struct {
  5142. const char str[ETH_GSTRING_LEN];
  5143. } qeth_ethtool_stats_keys[] = {
  5144. /* 0 */{"rx skbs"},
  5145. {"rx buffers"},
  5146. {"tx skbs"},
  5147. {"tx buffers"},
  5148. {"tx skbs no packing"},
  5149. {"tx buffers no packing"},
  5150. {"tx skbs packing"},
  5151. {"tx buffers packing"},
  5152. {"tx sg skbs"},
  5153. {"tx sg frags"},
  5154. /* 10 */{"rx sg skbs"},
  5155. {"rx sg frags"},
  5156. {"rx sg page allocs"},
  5157. {"tx large kbytes"},
  5158. {"tx large count"},
  5159. {"tx pk state ch n->p"},
  5160. {"tx pk state ch p->n"},
  5161. {"tx pk watermark low"},
  5162. {"tx pk watermark high"},
  5163. {"queue 0 buffer usage"},
  5164. /* 20 */{"queue 1 buffer usage"},
  5165. {"queue 2 buffer usage"},
  5166. {"queue 3 buffer usage"},
  5167. {"rx poll time"},
  5168. {"rx poll count"},
  5169. {"rx do_QDIO time"},
  5170. {"rx do_QDIO count"},
  5171. {"tx handler time"},
  5172. {"tx handler count"},
  5173. {"tx time"},
  5174. /* 30 */{"tx count"},
  5175. {"tx do_QDIO time"},
  5176. {"tx do_QDIO count"},
  5177. {"tx csum"},
  5178. {"tx lin"},
  5179. {"tx linfail"},
  5180. {"cq handler count"},
  5181. {"cq handler time"}
  5182. };
  5183. int qeth_core_get_sset_count(struct net_device *dev, int stringset)
  5184. {
  5185. switch (stringset) {
  5186. case ETH_SS_STATS:
  5187. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  5188. default:
  5189. return -EINVAL;
  5190. }
  5191. }
  5192. EXPORT_SYMBOL_GPL(qeth_core_get_sset_count);
  5193. void qeth_core_get_ethtool_stats(struct net_device *dev,
  5194. struct ethtool_stats *stats, u64 *data)
  5195. {
  5196. struct qeth_card *card = dev->ml_priv;
  5197. data[0] = card->stats.rx_packets -
  5198. card->perf_stats.initial_rx_packets;
  5199. data[1] = card->perf_stats.bufs_rec;
  5200. data[2] = card->stats.tx_packets -
  5201. card->perf_stats.initial_tx_packets;
  5202. data[3] = card->perf_stats.bufs_sent;
  5203. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  5204. - card->perf_stats.skbs_sent_pack;
  5205. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  5206. data[6] = card->perf_stats.skbs_sent_pack;
  5207. data[7] = card->perf_stats.bufs_sent_pack;
  5208. data[8] = card->perf_stats.sg_skbs_sent;
  5209. data[9] = card->perf_stats.sg_frags_sent;
  5210. data[10] = card->perf_stats.sg_skbs_rx;
  5211. data[11] = card->perf_stats.sg_frags_rx;
  5212. data[12] = card->perf_stats.sg_alloc_page_rx;
  5213. data[13] = (card->perf_stats.large_send_bytes >> 10);
  5214. data[14] = card->perf_stats.large_send_cnt;
  5215. data[15] = card->perf_stats.sc_dp_p;
  5216. data[16] = card->perf_stats.sc_p_dp;
  5217. data[17] = QETH_LOW_WATERMARK_PACK;
  5218. data[18] = QETH_HIGH_WATERMARK_PACK;
  5219. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  5220. data[20] = (card->qdio.no_out_queues > 1) ?
  5221. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  5222. data[21] = (card->qdio.no_out_queues > 2) ?
  5223. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  5224. data[22] = (card->qdio.no_out_queues > 3) ?
  5225. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  5226. data[23] = card->perf_stats.inbound_time;
  5227. data[24] = card->perf_stats.inbound_cnt;
  5228. data[25] = card->perf_stats.inbound_do_qdio_time;
  5229. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  5230. data[27] = card->perf_stats.outbound_handler_time;
  5231. data[28] = card->perf_stats.outbound_handler_cnt;
  5232. data[29] = card->perf_stats.outbound_time;
  5233. data[30] = card->perf_stats.outbound_cnt;
  5234. data[31] = card->perf_stats.outbound_do_qdio_time;
  5235. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  5236. data[33] = card->perf_stats.tx_csum;
  5237. data[34] = card->perf_stats.tx_lin;
  5238. data[35] = card->perf_stats.tx_linfail;
  5239. data[36] = card->perf_stats.cq_cnt;
  5240. data[37] = card->perf_stats.cq_time;
  5241. }
  5242. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  5243. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  5244. {
  5245. switch (stringset) {
  5246. case ETH_SS_STATS:
  5247. memcpy(data, &qeth_ethtool_stats_keys,
  5248. sizeof(qeth_ethtool_stats_keys));
  5249. break;
  5250. default:
  5251. WARN_ON(1);
  5252. break;
  5253. }
  5254. }
  5255. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  5256. void qeth_core_get_drvinfo(struct net_device *dev,
  5257. struct ethtool_drvinfo *info)
  5258. {
  5259. struct qeth_card *card = dev->ml_priv;
  5260. strlcpy(info->driver, card->options.layer2 ? "qeth_l2" : "qeth_l3",
  5261. sizeof(info->driver));
  5262. strlcpy(info->version, "1.0", sizeof(info->version));
  5263. strlcpy(info->fw_version, card->info.mcl_level,
  5264. sizeof(info->fw_version));
  5265. snprintf(info->bus_info, sizeof(info->bus_info), "%s/%s/%s",
  5266. CARD_RDEV_ID(card), CARD_WDEV_ID(card), CARD_DDEV_ID(card));
  5267. }
  5268. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  5269. /* Helper function to fill 'advertizing' and 'supported' which are the same. */
  5270. /* Autoneg and full-duplex are supported and advertized uncondionally. */
  5271. /* Always advertize and support all speeds up to specified, and only one */
  5272. /* specified port type. */
  5273. static void qeth_set_ecmd_adv_sup(struct ethtool_cmd *ecmd,
  5274. int maxspeed, int porttype)
  5275. {
  5276. int port_sup, port_adv, spd_sup, spd_adv;
  5277. switch (porttype) {
  5278. case PORT_TP:
  5279. port_sup = SUPPORTED_TP;
  5280. port_adv = ADVERTISED_TP;
  5281. break;
  5282. case PORT_FIBRE:
  5283. port_sup = SUPPORTED_FIBRE;
  5284. port_adv = ADVERTISED_FIBRE;
  5285. break;
  5286. default:
  5287. port_sup = SUPPORTED_TP;
  5288. port_adv = ADVERTISED_TP;
  5289. WARN_ON_ONCE(1);
  5290. }
  5291. /* "Fallthrough" case'es ordered from high to low result in setting */
  5292. /* flags cumulatively, starting from the specified speed and down to */
  5293. /* the lowest possible. */
  5294. spd_sup = 0;
  5295. spd_adv = 0;
  5296. switch (maxspeed) {
  5297. case SPEED_10000:
  5298. spd_sup |= SUPPORTED_10000baseT_Full;
  5299. spd_adv |= ADVERTISED_10000baseT_Full;
  5300. case SPEED_1000:
  5301. spd_sup |= SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full;
  5302. spd_adv |= ADVERTISED_1000baseT_Half |
  5303. ADVERTISED_1000baseT_Full;
  5304. case SPEED_100:
  5305. spd_sup |= SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full;
  5306. spd_adv |= ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
  5307. case SPEED_10:
  5308. spd_sup |= SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full;
  5309. spd_adv |= ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
  5310. break;
  5311. default:
  5312. spd_sup = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full;
  5313. spd_adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
  5314. WARN_ON_ONCE(1);
  5315. }
  5316. ecmd->advertising = ADVERTISED_Autoneg | port_adv | spd_adv;
  5317. ecmd->supported = SUPPORTED_Autoneg | port_sup | spd_sup;
  5318. }
  5319. int qeth_core_ethtool_get_settings(struct net_device *netdev,
  5320. struct ethtool_cmd *ecmd)
  5321. {
  5322. struct qeth_card *card = netdev->ml_priv;
  5323. enum qeth_link_types link_type;
  5324. struct carrier_info carrier_info;
  5325. int rc;
  5326. u32 speed;
  5327. if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
  5328. link_type = QETH_LINK_TYPE_10GBIT_ETH;
  5329. else
  5330. link_type = card->info.link_type;
  5331. ecmd->transceiver = XCVR_INTERNAL;
  5332. ecmd->duplex = DUPLEX_FULL;
  5333. ecmd->autoneg = AUTONEG_ENABLE;
  5334. switch (link_type) {
  5335. case QETH_LINK_TYPE_FAST_ETH:
  5336. case QETH_LINK_TYPE_LANE_ETH100:
  5337. qeth_set_ecmd_adv_sup(ecmd, SPEED_100, PORT_TP);
  5338. speed = SPEED_100;
  5339. ecmd->port = PORT_TP;
  5340. break;
  5341. case QETH_LINK_TYPE_GBIT_ETH:
  5342. case QETH_LINK_TYPE_LANE_ETH1000:
  5343. qeth_set_ecmd_adv_sup(ecmd, SPEED_1000, PORT_FIBRE);
  5344. speed = SPEED_1000;
  5345. ecmd->port = PORT_FIBRE;
  5346. break;
  5347. case QETH_LINK_TYPE_10GBIT_ETH:
  5348. qeth_set_ecmd_adv_sup(ecmd, SPEED_10000, PORT_FIBRE);
  5349. speed = SPEED_10000;
  5350. ecmd->port = PORT_FIBRE;
  5351. break;
  5352. default:
  5353. qeth_set_ecmd_adv_sup(ecmd, SPEED_10, PORT_TP);
  5354. speed = SPEED_10;
  5355. ecmd->port = PORT_TP;
  5356. }
  5357. ethtool_cmd_speed_set(ecmd, speed);
  5358. /* Check if we can obtain more accurate information. */
  5359. /* If QUERY_CARD_INFO command is not supported or fails, */
  5360. /* just return the heuristics that was filled above. */
  5361. if (!qeth_card_hw_is_reachable(card))
  5362. return -ENODEV;
  5363. rc = qeth_query_card_info(card, &carrier_info);
  5364. if (rc == -EOPNOTSUPP) /* for old hardware, return heuristic */
  5365. return 0;
  5366. if (rc) /* report error from the hardware operation */
  5367. return rc;
  5368. /* on success, fill in the information got from the hardware */
  5369. netdev_dbg(netdev,
  5370. "card info: card_type=0x%02x, port_mode=0x%04x, port_speed=0x%08x\n",
  5371. carrier_info.card_type,
  5372. carrier_info.port_mode,
  5373. carrier_info.port_speed);
  5374. /* Update attributes for which we've obtained more authoritative */
  5375. /* information, leave the rest the way they where filled above. */
  5376. switch (carrier_info.card_type) {
  5377. case CARD_INFO_TYPE_1G_COPPER_A:
  5378. case CARD_INFO_TYPE_1G_COPPER_B:
  5379. qeth_set_ecmd_adv_sup(ecmd, SPEED_1000, PORT_TP);
  5380. ecmd->port = PORT_TP;
  5381. break;
  5382. case CARD_INFO_TYPE_1G_FIBRE_A:
  5383. case CARD_INFO_TYPE_1G_FIBRE_B:
  5384. qeth_set_ecmd_adv_sup(ecmd, SPEED_1000, PORT_FIBRE);
  5385. ecmd->port = PORT_FIBRE;
  5386. break;
  5387. case CARD_INFO_TYPE_10G_FIBRE_A:
  5388. case CARD_INFO_TYPE_10G_FIBRE_B:
  5389. qeth_set_ecmd_adv_sup(ecmd, SPEED_10000, PORT_FIBRE);
  5390. ecmd->port = PORT_FIBRE;
  5391. break;
  5392. }
  5393. switch (carrier_info.port_mode) {
  5394. case CARD_INFO_PORTM_FULLDUPLEX:
  5395. ecmd->duplex = DUPLEX_FULL;
  5396. break;
  5397. case CARD_INFO_PORTM_HALFDUPLEX:
  5398. ecmd->duplex = DUPLEX_HALF;
  5399. break;
  5400. }
  5401. switch (carrier_info.port_speed) {
  5402. case CARD_INFO_PORTS_10M:
  5403. speed = SPEED_10;
  5404. break;
  5405. case CARD_INFO_PORTS_100M:
  5406. speed = SPEED_100;
  5407. break;
  5408. case CARD_INFO_PORTS_1G:
  5409. speed = SPEED_1000;
  5410. break;
  5411. case CARD_INFO_PORTS_10G:
  5412. speed = SPEED_10000;
  5413. break;
  5414. }
  5415. ethtool_cmd_speed_set(ecmd, speed);
  5416. return 0;
  5417. }
  5418. EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
  5419. static int qeth_send_checksum_on(struct qeth_card *card, int cstype)
  5420. {
  5421. long rxtx_arg;
  5422. int rc;
  5423. rc = qeth_send_simple_setassparms(card, cstype, IPA_CMD_ASS_START, 0);
  5424. if (rc) {
  5425. dev_warn(&card->gdev->dev,
  5426. "Starting HW checksumming for %s failed, using SW checksumming\n",
  5427. QETH_CARD_IFNAME(card));
  5428. return rc;
  5429. }
  5430. rxtx_arg = (cstype == IPA_OUTBOUND_CHECKSUM) ? card->info.tx_csum_mask
  5431. : card->info.csum_mask;
  5432. rc = qeth_send_simple_setassparms(card, cstype, IPA_CMD_ASS_ENABLE,
  5433. rxtx_arg);
  5434. if (rc) {
  5435. dev_warn(&card->gdev->dev,
  5436. "Enabling HW checksumming for %s failed, using SW checksumming\n",
  5437. QETH_CARD_IFNAME(card));
  5438. return rc;
  5439. }
  5440. dev_info(&card->gdev->dev, "HW Checksumming (%sbound) enabled\n",
  5441. cstype == IPA_INBOUND_CHECKSUM ? "in" : "out");
  5442. return 0;
  5443. }
  5444. static int qeth_set_ipa_csum(struct qeth_card *card, int on, int cstype)
  5445. {
  5446. int rc;
  5447. if (on) {
  5448. rc = qeth_send_checksum_on(card, cstype);
  5449. if (rc)
  5450. return -EIO;
  5451. } else {
  5452. rc = qeth_send_simple_setassparms(card, cstype,
  5453. IPA_CMD_ASS_STOP, 0);
  5454. if (rc)
  5455. return -EIO;
  5456. }
  5457. return 0;
  5458. }
  5459. static int qeth_set_ipa_tso(struct qeth_card *card, int on)
  5460. {
  5461. int rc;
  5462. QETH_CARD_TEXT(card, 3, "sttso");
  5463. if (on) {
  5464. rc = qeth_send_simple_setassparms(card, IPA_OUTBOUND_TSO,
  5465. IPA_CMD_ASS_START, 0);
  5466. if (rc) {
  5467. dev_warn(&card->gdev->dev,
  5468. "Starting outbound TCP segmentation offload for %s failed\n",
  5469. QETH_CARD_IFNAME(card));
  5470. return -EIO;
  5471. }
  5472. dev_info(&card->gdev->dev, "Outbound TSO enabled\n");
  5473. } else {
  5474. rc = qeth_send_simple_setassparms(card, IPA_OUTBOUND_TSO,
  5475. IPA_CMD_ASS_STOP, 0);
  5476. }
  5477. return rc;
  5478. }
  5479. /* try to restore device features on a device after recovery */
  5480. int qeth_recover_features(struct net_device *dev)
  5481. {
  5482. struct qeth_card *card = dev->ml_priv;
  5483. netdev_features_t recover = dev->features;
  5484. if (recover & NETIF_F_IP_CSUM) {
  5485. if (qeth_set_ipa_csum(card, 1, IPA_OUTBOUND_CHECKSUM))
  5486. recover ^= NETIF_F_IP_CSUM;
  5487. }
  5488. if (recover & NETIF_F_RXCSUM) {
  5489. if (qeth_set_ipa_csum(card, 1, IPA_INBOUND_CHECKSUM))
  5490. recover ^= NETIF_F_RXCSUM;
  5491. }
  5492. if (recover & NETIF_F_TSO) {
  5493. if (qeth_set_ipa_tso(card, 1))
  5494. recover ^= NETIF_F_TSO;
  5495. }
  5496. if (recover == dev->features)
  5497. return 0;
  5498. dev_warn(&card->gdev->dev,
  5499. "Device recovery failed to restore all offload features\n");
  5500. dev->features = recover;
  5501. return -EIO;
  5502. }
  5503. EXPORT_SYMBOL_GPL(qeth_recover_features);
  5504. int qeth_set_features(struct net_device *dev, netdev_features_t features)
  5505. {
  5506. struct qeth_card *card = dev->ml_priv;
  5507. netdev_features_t changed = dev->features ^ features;
  5508. int rc = 0;
  5509. QETH_DBF_TEXT(SETUP, 2, "setfeat");
  5510. QETH_DBF_HEX(SETUP, 2, &features, sizeof(features));
  5511. if ((changed & NETIF_F_IP_CSUM)) {
  5512. rc = qeth_set_ipa_csum(card,
  5513. features & NETIF_F_IP_CSUM ? 1 : 0,
  5514. IPA_OUTBOUND_CHECKSUM);
  5515. if (rc)
  5516. changed ^= NETIF_F_IP_CSUM;
  5517. }
  5518. if ((changed & NETIF_F_RXCSUM)) {
  5519. rc = qeth_set_ipa_csum(card,
  5520. features & NETIF_F_RXCSUM ? 1 : 0,
  5521. IPA_INBOUND_CHECKSUM);
  5522. if (rc)
  5523. changed ^= NETIF_F_RXCSUM;
  5524. }
  5525. if ((changed & NETIF_F_TSO)) {
  5526. rc = qeth_set_ipa_tso(card, features & NETIF_F_TSO ? 1 : 0);
  5527. if (rc)
  5528. changed ^= NETIF_F_TSO;
  5529. }
  5530. /* everything changed successfully? */
  5531. if ((dev->features ^ features) == changed)
  5532. return 0;
  5533. /* something went wrong. save changed features and return error */
  5534. dev->features ^= changed;
  5535. return -EIO;
  5536. }
  5537. EXPORT_SYMBOL_GPL(qeth_set_features);
  5538. netdev_features_t qeth_fix_features(struct net_device *dev,
  5539. netdev_features_t features)
  5540. {
  5541. struct qeth_card *card = dev->ml_priv;
  5542. QETH_DBF_TEXT(SETUP, 2, "fixfeat");
  5543. if (!qeth_is_supported(card, IPA_OUTBOUND_CHECKSUM))
  5544. features &= ~NETIF_F_IP_CSUM;
  5545. if (!qeth_is_supported(card, IPA_INBOUND_CHECKSUM))
  5546. features &= ~NETIF_F_RXCSUM;
  5547. if (!qeth_is_supported(card, IPA_OUTBOUND_TSO)) {
  5548. features &= ~NETIF_F_TSO;
  5549. dev_info(&card->gdev->dev, "Outbound TSO not supported on %s\n",
  5550. QETH_CARD_IFNAME(card));
  5551. }
  5552. /* if the card isn't up, remove features that require hw changes */
  5553. if (card->state == CARD_STATE_DOWN ||
  5554. card->state == CARD_STATE_RECOVER)
  5555. features = features & ~(NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
  5556. NETIF_F_TSO);
  5557. QETH_DBF_HEX(SETUP, 2, &features, sizeof(features));
  5558. return features;
  5559. }
  5560. EXPORT_SYMBOL_GPL(qeth_fix_features);
  5561. static int __init qeth_core_init(void)
  5562. {
  5563. int rc;
  5564. pr_info("loading core functions\n");
  5565. INIT_LIST_HEAD(&qeth_core_card_list.list);
  5566. INIT_LIST_HEAD(&qeth_dbf_list);
  5567. rwlock_init(&qeth_core_card_list.rwlock);
  5568. mutex_init(&qeth_mod_mutex);
  5569. qeth_wq = create_singlethread_workqueue("qeth_wq");
  5570. rc = qeth_register_dbf_views();
  5571. if (rc)
  5572. goto out_err;
  5573. qeth_core_root_dev = root_device_register("qeth");
  5574. rc = PTR_ERR_OR_ZERO(qeth_core_root_dev);
  5575. if (rc)
  5576. goto register_err;
  5577. qeth_core_header_cache = kmem_cache_create("qeth_hdr",
  5578. sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL);
  5579. if (!qeth_core_header_cache) {
  5580. rc = -ENOMEM;
  5581. goto slab_err;
  5582. }
  5583. qeth_qdio_outbuf_cache = kmem_cache_create("qeth_buf",
  5584. sizeof(struct qeth_qdio_out_buffer), 0, 0, NULL);
  5585. if (!qeth_qdio_outbuf_cache) {
  5586. rc = -ENOMEM;
  5587. goto cqslab_err;
  5588. }
  5589. rc = ccw_driver_register(&qeth_ccw_driver);
  5590. if (rc)
  5591. goto ccw_err;
  5592. qeth_core_ccwgroup_driver.driver.groups = qeth_drv_attr_groups;
  5593. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  5594. if (rc)
  5595. goto ccwgroup_err;
  5596. return 0;
  5597. ccwgroup_err:
  5598. ccw_driver_unregister(&qeth_ccw_driver);
  5599. ccw_err:
  5600. kmem_cache_destroy(qeth_qdio_outbuf_cache);
  5601. cqslab_err:
  5602. kmem_cache_destroy(qeth_core_header_cache);
  5603. slab_err:
  5604. root_device_unregister(qeth_core_root_dev);
  5605. register_err:
  5606. qeth_unregister_dbf_views();
  5607. out_err:
  5608. pr_err("Initializing the qeth device driver failed\n");
  5609. return rc;
  5610. }
  5611. static void __exit qeth_core_exit(void)
  5612. {
  5613. qeth_clear_dbf_list();
  5614. destroy_workqueue(qeth_wq);
  5615. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  5616. ccw_driver_unregister(&qeth_ccw_driver);
  5617. kmem_cache_destroy(qeth_qdio_outbuf_cache);
  5618. kmem_cache_destroy(qeth_core_header_cache);
  5619. root_device_unregister(qeth_core_root_dev);
  5620. qeth_unregister_dbf_views();
  5621. pr_info("core functions removed\n");
  5622. }
  5623. module_init(qeth_core_init);
  5624. module_exit(qeth_core_exit);
  5625. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  5626. MODULE_DESCRIPTION("qeth core functions");
  5627. MODULE_LICENSE("GPL");