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@@ -313,6 +313,7 @@ int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
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for (i = 0; i < bo->placement.num_placement; i++) {
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for (i = 0; i < bo->placement.num_placement; i++) {
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/* force to pin into visible video ram */
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/* force to pin into visible video ram */
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if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
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if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
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+ !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
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(!max_offset || max_offset > bo->rdev->mc.visible_vram_size))
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(!max_offset || max_offset > bo->rdev->mc.visible_vram_size))
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bo->placements[i].lpfn =
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bo->placements[i].lpfn =
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bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
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bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
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