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@@ -311,18 +311,14 @@ int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
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}
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radeon_ttm_placement_from_domain(bo, domain);
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for (i = 0; i < bo->placement.num_placement; i++) {
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- unsigned lpfn = 0;
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-
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/* force to pin into visible video ram */
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- if (bo->placements[i].flags & TTM_PL_FLAG_VRAM)
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- lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
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+ if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
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+ (!max_offset || max_offset > bo->rdev->mc.visible_vram_size))
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+ bo->placements[i].lpfn =
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+ bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
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else
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- lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT; /* ??? */
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-
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- if (max_offset)
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- lpfn = min (lpfn, (unsigned)(max_offset >> PAGE_SHIFT));
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+ bo->placements[i].lpfn = max_offset >> PAGE_SHIFT;
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- bo->placements[i].lpfn = lpfn;
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bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
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}
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