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+OMAP PRCM bindings
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+
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+Power Reset and Clock Manager lists the device clocks and clockdomains under
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+a DT hierarchy. Each TI SoC can have multiple PRCM entities listed for it,
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+each describing one module and the clock hierarchy under it. see [1] for
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+documentation about the individual clock/clockdomain nodes.
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+
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+[1] Documentation/devicetree/bindings/clock/ti/*
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+
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+Required properties:
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+- compatible: Must be one of:
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+ "ti,am3-prcm"
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+ "ti,am3-scrm"
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+ "ti,am4-prcm"
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+ "ti,am4-scrm"
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+ "ti,omap2-prcm"
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+ "ti,omap2-scrm"
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+ "ti,omap3-prm"
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+ "ti,omap3-cm"
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+ "ti,omap3-scrm"
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+ "ti,omap4-cm1"
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+ "ti,omap4-prm"
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+ "ti,omap4-cm2"
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+ "ti,omap4-scrm"
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+ "ti,omap5-prm"
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+ "ti,omap5-cm-core-aon"
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+ "ti,omap5-scrm"
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+ "ti,omap5-cm-core"
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+ "ti,dra7-prm"
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+ "ti,dra7-cm-core-aon"
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+ "ti,dra7-cm-core"
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+- reg: Contains PRCM module register address range
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+ (base address and length)
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+- clocks: clocks for this module
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+- clockdomains: clockdomains for this module
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+
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+Example:
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+
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+cm: cm@48004000 {
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+ compatible = "ti,omap3-cm";
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+ reg = <0x48004000 0x4000>;
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+
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+ cm_clocks: clocks {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ cm_clockdomains: clockdomains {
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+ };
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+}
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+
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+&cm_clocks {
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+ omap2_32k_fck: omap_32k_fck {
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+ #clock-cells = <0>;
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+ compatible = "fixed-clock";
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+ clock-frequency = <32768>;
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+ };
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+};
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+
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+&cm_clockdomains {
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+ core_l3_clkdm: core_l3_clkdm {
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+ compatible = "ti,clockdomain";
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+ clocks = <&sdrc_ick>;
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+ };
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+};
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