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@@ -1342,6 +1342,14 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
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DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
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out:
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+ if (ret && IS_BROXTON(dev_priv)) {
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+ tmp = I915_READ(BXT_PHY_CTL(port));
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+ if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK |
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+ BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
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+ DRM_ERROR("Port %c enabled but PHY powered down? "
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+ "(PHY_CTL %08x)\n", port_name(port), tmp);
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+ }
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+
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intel_display_power_put(dev_priv, power_domain);
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return ret;
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@@ -1745,6 +1753,8 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder)
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bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
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enum dpio_phy phy)
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{
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+ enum port port;
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+
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if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & GT_DISPLAY_POWER_ON(phy)))
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return false;
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@@ -1770,6 +1780,21 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
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return false;
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}
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+ for_each_port_masked(port,
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+ phy == DPIO_PHY0 ? BIT(PORT_B) | BIT(PORT_C) :
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+ BIT(PORT_A)) {
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+ u32 tmp = I915_READ(BXT_PHY_CTL(port));
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+
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+ if (tmp & BXT_PHY_CMNLANE_POWERDOWN_ACK) {
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+ DRM_DEBUG_DRIVER("DDI PHY %d powered, but common lane "
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+ "for port %c powered down "
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+ "(PHY_CTL %08x)\n",
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+ phy, port_name(port), tmp);
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+
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+ return false;
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+ }
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+ }
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+
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return true;
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}
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