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@@ -17,6 +17,7 @@
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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+#include <linux/acpi.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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@@ -318,56 +319,157 @@ void __init smp_prepare_boot_cpu(void)
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set_my_cpu_offset(per_cpu_offset(smp_processor_id()));
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}
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+static u64 __init of_get_cpu_mpidr(struct device_node *dn)
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+{
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+ const __be32 *cell;
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+ u64 hwid;
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+
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+ /*
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+ * A cpu node with missing "reg" property is
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+ * considered invalid to build a cpu_logical_map
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+ * entry.
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+ */
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+ cell = of_get_property(dn, "reg", NULL);
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+ if (!cell) {
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+ pr_err("%s: missing reg property\n", dn->full_name);
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+ return INVALID_HWID;
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+ }
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+
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+ hwid = of_read_number(cell, of_n_addr_cells(dn));
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+ /*
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+ * Non affinity bits must be set to 0 in the DT
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+ */
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+ if (hwid & ~MPIDR_HWID_BITMASK) {
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+ pr_err("%s: invalid reg property\n", dn->full_name);
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+ return INVALID_HWID;
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+ }
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+ return hwid;
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+}
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+
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+/*
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+ * Duplicate MPIDRs are a recipe for disaster. Scan all initialized
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+ * entries and check for duplicates. If any is found just ignore the
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+ * cpu. cpu_logical_map was initialized to INVALID_HWID to avoid
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+ * matching valid MPIDR values.
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+ */
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+static bool __init is_mpidr_duplicate(unsigned int cpu, u64 hwid)
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+{
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+ unsigned int i;
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+
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+ for (i = 1; (i < cpu) && (i < NR_CPUS); i++)
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+ if (cpu_logical_map(i) == hwid)
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+ return true;
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+ return false;
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+}
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+
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+/*
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+ * Initialize cpu operations for a logical cpu and
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+ * set it in the possible mask on success
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+ */
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+static int __init smp_cpu_setup(int cpu)
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+{
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+ if (cpu_read_ops(cpu))
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+ return -ENODEV;
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+
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+ if (cpu_ops[cpu]->cpu_init(cpu))
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+ return -ENODEV;
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+
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+ set_cpu_possible(cpu, true);
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+
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+ return 0;
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+}
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+
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+static bool bootcpu_valid __initdata;
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+static unsigned int cpu_count = 1;
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+
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+#ifdef CONFIG_ACPI
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+/*
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+ * acpi_map_gic_cpu_interface - parse processor MADT entry
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+ *
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+ * Carry out sanity checks on MADT processor entry and initialize
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+ * cpu_logical_map on success
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+ */
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+static void __init
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+acpi_map_gic_cpu_interface(struct acpi_madt_generic_interrupt *processor)
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+{
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+ u64 hwid = processor->arm_mpidr;
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+
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+ if (hwid & ~MPIDR_HWID_BITMASK || hwid == INVALID_HWID) {
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+ pr_err("skipping CPU entry with invalid MPIDR 0x%llx\n", hwid);
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+ return;
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+ }
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+
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+ if (!(processor->flags & ACPI_MADT_ENABLED)) {
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+ pr_err("skipping disabled CPU entry with 0x%llx MPIDR\n", hwid);
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+ return;
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+ }
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+
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+ if (is_mpidr_duplicate(cpu_count, hwid)) {
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+ pr_err("duplicate CPU MPIDR 0x%llx in MADT\n", hwid);
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+ return;
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+ }
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+
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+ /* Check if GICC structure of boot CPU is available in the MADT */
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+ if (cpu_logical_map(0) == hwid) {
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+ if (bootcpu_valid) {
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+ pr_err("duplicate boot CPU MPIDR: 0x%llx in MADT\n",
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+ hwid);
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+ return;
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+ }
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+ bootcpu_valid = true;
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+ return;
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+ }
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+
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+ if (cpu_count >= NR_CPUS)
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+ return;
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+
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+ /* map the logical cpu id to cpu MPIDR */
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+ cpu_logical_map(cpu_count) = hwid;
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+
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+ cpu_count++;
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+}
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+
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+static int __init
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+acpi_parse_gic_cpu_interface(struct acpi_subtable_header *header,
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+ const unsigned long end)
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+{
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+ struct acpi_madt_generic_interrupt *processor;
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+
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+ processor = (struct acpi_madt_generic_interrupt *)header;
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+ if (BAD_MADT_ENTRY(processor, end))
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+ return -EINVAL;
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+
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+ acpi_table_print_madt_entry(header);
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+
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+ acpi_map_gic_cpu_interface(processor);
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+
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+ return 0;
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+}
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+#else
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+#define acpi_table_parse_madt(...) do { } while (0)
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+#endif
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+
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/*
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* Enumerate the possible CPU set from the device tree and build the
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* cpu logical map array containing MPIDR values related to logical
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* cpus. Assumes that cpu_logical_map(0) has already been initialized.
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*/
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-void __init of_smp_init_cpus(void)
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+void __init of_parse_and_init_cpus(void)
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{
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struct device_node *dn = NULL;
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- unsigned int i, cpu = 1;
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- bool bootcpu_valid = false;
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while ((dn = of_find_node_by_type(dn, "cpu"))) {
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- const u32 *cell;
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- u64 hwid;
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+ u64 hwid = of_get_cpu_mpidr(dn);
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- /*
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- * A cpu node with missing "reg" property is
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- * considered invalid to build a cpu_logical_map
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- * entry.
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- */
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- cell = of_get_property(dn, "reg", NULL);
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- if (!cell) {
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- pr_err("%s: missing reg property\n", dn->full_name);
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+ if (hwid == INVALID_HWID)
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goto next;
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- }
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- hwid = of_read_number(cell, of_n_addr_cells(dn));
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- /*
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- * Non affinity bits must be set to 0 in the DT
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- */
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- if (hwid & ~MPIDR_HWID_BITMASK) {
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- pr_err("%s: invalid reg property\n", dn->full_name);
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+ if (is_mpidr_duplicate(cpu_count, hwid)) {
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+ pr_err("%s: duplicate cpu reg properties in the DT\n",
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+ dn->full_name);
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goto next;
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}
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- /*
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- * Duplicate MPIDRs are a recipe for disaster. Scan
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- * all initialized entries and check for
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- * duplicates. If any is found just ignore the cpu.
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- * cpu_logical_map was initialized to INVALID_HWID to
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- * avoid matching valid MPIDR values.
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- */
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- for (i = 1; (i < cpu) && (i < NR_CPUS); i++) {
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- if (cpu_logical_map(i) == hwid) {
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- pr_err("%s: duplicate cpu reg properties in the DT\n",
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- dn->full_name);
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- goto next;
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- }
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- }
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-
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/*
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* The numbering scheme requires that the boot CPU
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* must be assigned logical id 0. Record it so that
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@@ -392,38 +494,58 @@ void __init of_smp_init_cpus(void)
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continue;
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}
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- if (cpu >= NR_CPUS)
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- goto next;
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-
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- if (cpu_read_ops(dn, cpu) != 0)
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- goto next;
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-
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- if (cpu_ops[cpu]->cpu_init(dn, cpu))
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+ if (cpu_count >= NR_CPUS)
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goto next;
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pr_debug("cpu logical map 0x%llx\n", hwid);
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- cpu_logical_map(cpu) = hwid;
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+ cpu_logical_map(cpu_count) = hwid;
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next:
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- cpu++;
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+ cpu_count++;
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}
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+}
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+
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+/*
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+ * Enumerate the possible CPU set from the device tree or ACPI and build the
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+ * cpu logical map array containing MPIDR values related to logical
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+ * cpus. Assumes that cpu_logical_map(0) has already been initialized.
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+ */
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+void __init smp_init_cpus(void)
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+{
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+ int i;
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- /* sanity check */
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- if (cpu > NR_CPUS)
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- pr_warning("no. of cores (%d) greater than configured maximum of %d - clipping\n",
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- cpu, NR_CPUS);
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+ if (acpi_disabled)
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+ of_parse_and_init_cpus();
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+ else
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+ /*
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+ * do a walk of MADT to determine how many CPUs
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+ * we have including disabled CPUs, and get information
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+ * we need for SMP init
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+ */
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+ acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
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+ acpi_parse_gic_cpu_interface, 0);
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+
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+ if (cpu_count > NR_CPUS)
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+ pr_warn("no. of cores (%d) greater than configured maximum of %d - clipping\n",
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+ cpu_count, NR_CPUS);
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if (!bootcpu_valid) {
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- pr_err("DT missing boot CPU MPIDR, not enabling secondaries\n");
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+ pr_err("missing boot CPU MPIDR, not enabling secondaries\n");
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return;
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}
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/*
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- * All the cpus that made it to the cpu_logical_map have been
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- * validated so set them as possible cpus.
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+ * We need to set the cpu_logical_map entries before enabling
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+ * the cpus so that cpu processor description entries (DT cpu nodes
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+ * and ACPI MADT entries) can be retrieved by matching the cpu hwid
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+ * with entries in cpu_logical_map while initializing the cpus.
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+ * If the cpu set-up fails, invalidate the cpu_logical_map entry.
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*/
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- for (i = 0; i < NR_CPUS; i++)
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- if (cpu_logical_map(i) != INVALID_HWID)
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- set_cpu_possible(i, true);
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+ for (i = 1; i < NR_CPUS; i++) {
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+ if (cpu_logical_map(i) != INVALID_HWID) {
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+ if (smp_cpu_setup(i))
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+ cpu_logical_map(i) = INVALID_HWID;
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+ }
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+ }
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}
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void __init smp_prepare_cpus(unsigned int max_cpus)
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Catalin Marinas