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@@ -2050,6 +2050,52 @@ void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rde
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}
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}
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}
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}
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+/* get the current sclk in 10 khz units */
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+u32 rv6xx_dpm_get_current_sclk(struct radeon_device *rdev)
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+{
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+ struct radeon_ps *rps = rdev->pm.dpm.current_ps;
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+ struct rv6xx_ps *ps = rv6xx_get_ps(rps);
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+ struct rv6xx_pl *pl;
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+ u32 current_index =
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+ (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
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+ CURRENT_PROFILE_INDEX_SHIFT;
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+
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+ if (current_index > 2) {
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+ return 0;
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+ } else {
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+ if (current_index == 0)
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+ pl = &ps->low;
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+ else if (current_index == 1)
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+ pl = &ps->medium;
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+ else /* current_index == 2 */
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+ pl = &ps->high;
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+ return pl->sclk;
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+ }
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+}
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+
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+/* get the current mclk in 10 khz units */
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+u32 rv6xx_dpm_get_current_mclk(struct radeon_device *rdev)
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+{
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+ struct radeon_ps *rps = rdev->pm.dpm.current_ps;
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+ struct rv6xx_ps *ps = rv6xx_get_ps(rps);
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+ struct rv6xx_pl *pl;
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+ u32 current_index =
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+ (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
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+ CURRENT_PROFILE_INDEX_SHIFT;
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+
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+ if (current_index > 2) {
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+ return 0;
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+ } else {
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+ if (current_index == 0)
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+ pl = &ps->low;
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+ else if (current_index == 1)
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+ pl = &ps->medium;
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+ else /* current_index == 2 */
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+ pl = &ps->high;
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+ return pl->mclk;
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+ }
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+}
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+
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void rv6xx_dpm_fini(struct radeon_device *rdev)
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void rv6xx_dpm_fini(struct radeon_device *rdev)
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{
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{
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int i;
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int i;
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