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@@ -33,6 +33,14 @@
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#define TSTCNTL_WRITE_ADDRESS GENMASK(4, 0)
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#define TSTREAD1 21
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#define TSTWRITE 23
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+#define INTSRC_FLAG 29
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+#define INTSRC_ANEG_PR BIT(1)
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+#define INTSRC_PARALLEL_FAULT BIT(2)
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+#define INTSRC_ANEG_LP_ACK BIT(3)
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+#define INTSRC_LINK_DOWN BIT(4)
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+#define INTSRC_REMOTE_FAULT BIT(5)
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+#define INTSRC_ANEG_COMPLETE BIT(6)
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+#define INTSRC_MASK 30
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#define BANK_ANALOG_DSP 0
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#define BANK_WOL 1
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@@ -193,16 +201,43 @@ read_status_continue:
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return genphy_read_status(phydev);
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}
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+static int meson_gxl_ack_interrupt(struct phy_device *phydev)
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+{
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+ int ret = phy_read(phydev, INTSRC_FLAG);
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+
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+ return ret < 0 ? ret : 0;
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+}
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+
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+static int meson_gxl_config_intr(struct phy_device *phydev)
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+{
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+ u16 val;
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+
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+ if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
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+ val = INTSRC_ANEG_PR
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+ | INTSRC_PARALLEL_FAULT
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+ | INTSRC_ANEG_LP_ACK
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+ | INTSRC_LINK_DOWN
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+ | INTSRC_REMOTE_FAULT
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+ | INTSRC_ANEG_COMPLETE;
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+ } else {
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+ val = 0;
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+ }
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+
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+ return phy_write(phydev, INTSRC_MASK, val);
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+}
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+
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static struct phy_driver meson_gxl_phy[] = {
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{
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.phy_id = 0x01814400,
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.phy_id_mask = 0xfffffff0,
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.name = "Meson GXL Internal PHY",
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.features = PHY_BASIC_FEATURES,
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- .flags = PHY_IS_INTERNAL,
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+ .flags = PHY_IS_INTERNAL | PHY_HAS_INTERRUPT,
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.config_init = meson_gxl_config_init,
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.aneg_done = genphy_aneg_done,
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.read_status = meson_gxl_read_status,
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+ .ack_interrupt = meson_gxl_ack_interrupt,
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+ .config_intr = meson_gxl_config_intr,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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},
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