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@@ -1325,12 +1325,15 @@ static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
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static void uvd_v7_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
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{
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- int i;
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struct amdgpu_device *adev = ring->adev;
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+ int i;
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- for (i = 0; i < count; i++)
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- amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_NO_OP), 0));
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+ WARN_ON(ring->wptr % 2 || count % 2);
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+ for (i = 0; i < count / 2; i++) {
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+ amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_NO_OP), 0));
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+ amdgpu_ring_write(ring, 0);
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+ }
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}
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static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring)
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@@ -1710,7 +1713,6 @@ const struct amd_ip_funcs uvd_v7_0_ip_funcs = {
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static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = {
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.type = AMDGPU_RING_TYPE_UVD,
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.align_mask = 0xf,
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- .nop = PACKET0(0x81ff, 0),
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.support_64bit_ptrs = false,
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.vmhub = AMDGPU_MMHUB,
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.get_rptr = uvd_v7_0_ring_get_rptr,
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