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@@ -29,8 +29,8 @@
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* struct clk_pllv3 - IMX PLL clock version 3
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* @clk_hw: clock source
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* @base: base address of PLL registers
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- * @powerup_set: set POWER bit to power up the PLL
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- * @powerdown: pll powerdown offset bit
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+ * @power_bit: pll power bit mask
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+ * @powerup_set: set power_bit to power up the PLL
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* @div_mask: mask of divider bits
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* @div_shift: shift of divider bits
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*
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@@ -40,8 +40,8 @@
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struct clk_pllv3 {
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struct clk_hw hw;
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void __iomem *base;
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+ u32 power_bit;
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bool powerup_set;
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- u32 powerdown;
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u32 div_mask;
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u32 div_shift;
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unsigned long ref_clock;
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@@ -52,7 +52,7 @@ struct clk_pllv3 {
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static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
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{
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unsigned long timeout = jiffies + msecs_to_jiffies(10);
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- u32 val = readl_relaxed(pll->base) & pll->powerdown;
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+ u32 val = readl_relaxed(pll->base) & pll->power_bit;
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/* No need to wait for lock when pll is not powered up */
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if ((pll->powerup_set && !val) || (!pll->powerup_set && val))
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@@ -77,9 +77,9 @@ static int clk_pllv3_prepare(struct clk_hw *hw)
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val = readl_relaxed(pll->base);
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if (pll->powerup_set)
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- val |= pll->powerdown;
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+ val |= pll->power_bit;
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else
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- val &= ~pll->powerdown;
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+ val &= ~pll->power_bit;
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writel_relaxed(val, pll->base);
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return clk_pllv3_wait_lock(pll);
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@@ -92,9 +92,9 @@ static void clk_pllv3_unprepare(struct clk_hw *hw)
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val = readl_relaxed(pll->base);
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if (pll->powerup_set)
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- val &= ~pll->powerdown;
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+ val &= ~pll->power_bit;
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else
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- val |= pll->powerdown;
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+ val |= pll->power_bit;
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writel_relaxed(val, pll->base);
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}
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@@ -316,7 +316,7 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
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if (!pll)
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return ERR_PTR(-ENOMEM);
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- pll->powerdown = BM_PLL_POWER;
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+ pll->power_bit = BM_PLL_POWER;
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switch (type) {
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case IMX_PLLV3_SYS:
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@@ -332,7 +332,7 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
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ops = &clk_pllv3_av_ops;
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break;
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case IMX_PLLV3_ENET_IMX7:
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- pll->powerdown = IMX7_ENET_PLL_POWER;
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+ pll->power_bit = IMX7_ENET_PLL_POWER;
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pll->ref_clock = 1000000000;
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ops = &clk_pllv3_enet_ops;
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break;
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