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@@ -734,6 +734,7 @@ int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev,
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switch (adev->asic_type) {
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switch (adev->asic_type) {
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case CHIP_VEGA10:
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case CHIP_VEGA10:
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case CHIP_VEGA12:
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case CHIP_VEGA12:
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+ case CHIP_VEGA20:
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case CHIP_RAVEN:
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case CHIP_RAVEN:
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mmhub_v1_0_update_medium_grain_clock_gating(adev,
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mmhub_v1_0_update_medium_grain_clock_gating(adev,
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state == AMD_CG_STATE_GATE ? true : false);
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state == AMD_CG_STATE_GATE ? true : false);
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