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@@ -752,6 +752,7 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
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switch (adev->asic_type) {
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case CHIP_VEGA10: /* all engines support GPUVM */
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case CHIP_VEGA12: /* all engines support GPUVM */
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+ case CHIP_VEGA20:
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default:
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adev->gmc.gart_size = 512ULL << 20;
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break;
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@@ -857,6 +858,7 @@ static int gmc_v9_0_sw_init(void *handle)
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break;
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case CHIP_VEGA10:
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case CHIP_VEGA12:
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+ case CHIP_VEGA20:
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/*
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* To fulfill 4-level page support,
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* vm size is 256TB (48bit), maximum size of Vega10,
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@@ -974,6 +976,7 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
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switch (adev->asic_type) {
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case CHIP_VEGA10:
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+ case CHIP_VEGA20:
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soc15_program_register_sequence(adev,
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golden_settings_mmhub_1_0_0,
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ARRAY_SIZE(golden_settings_mmhub_1_0_0));
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