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@@ -0,0 +1,616 @@
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+/*
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+ * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
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+ * Copyright 2015 Linaro Limited.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 and
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+ * only version 2 as published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#include <linux/clk.h>
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+#include <linux/delay.h>
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+#include <linux/gpio.h>
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+#include <linux/interrupt.h>
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+#include <linux/io.h>
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+#include <linux/iopoll.h>
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/of_device.h>
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+#include <linux/of_gpio.h>
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+#include <linux/pci.h>
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+#include <linux/platform_device.h>
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+#include <linux/phy/phy.h>
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+#include <linux/regulator/consumer.h>
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+#include <linux/reset.h>
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+#include <linux/slab.h>
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+#include <linux/types.h>
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+
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+#include "pcie-designware.h"
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+
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+#define PCIE20_PARF_PHY_CTRL 0x40
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+#define PCIE20_PARF_PHY_REFCLK 0x4C
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+#define PCIE20_PARF_DBI_BASE_ADDR 0x168
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+#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16c
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+#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178
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+
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+#define PCIE20_ELBI_SYS_CTRL 0x04
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+#define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0)
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+
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+#define PCIE20_CAP 0x70
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+
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+#define PERST_DELAY_US 1000
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+
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+struct qcom_pcie_resources_v0 {
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+ struct clk *iface_clk;
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+ struct clk *core_clk;
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+ struct clk *phy_clk;
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+ struct reset_control *pci_reset;
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+ struct reset_control *axi_reset;
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+ struct reset_control *ahb_reset;
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+ struct reset_control *por_reset;
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+ struct reset_control *phy_reset;
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+ struct regulator *vdda;
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+ struct regulator *vdda_phy;
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+ struct regulator *vdda_refclk;
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+};
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+
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+struct qcom_pcie_resources_v1 {
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+ struct clk *iface;
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+ struct clk *aux;
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+ struct clk *master_bus;
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+ struct clk *slave_bus;
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+ struct reset_control *core;
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+ struct regulator *vdda;
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+};
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+
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+union qcom_pcie_resources {
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+ struct qcom_pcie_resources_v0 v0;
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+ struct qcom_pcie_resources_v1 v1;
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+};
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+
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+struct qcom_pcie;
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+
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+struct qcom_pcie_ops {
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+ int (*get_resources)(struct qcom_pcie *pcie);
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+ int (*init)(struct qcom_pcie *pcie);
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+ void (*deinit)(struct qcom_pcie *pcie);
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+};
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+
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+struct qcom_pcie {
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+ struct pcie_port pp;
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+ struct device *dev;
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+ union qcom_pcie_resources res;
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+ void __iomem *parf;
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+ void __iomem *dbi;
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+ void __iomem *elbi;
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+ struct phy *phy;
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+ struct gpio_desc *reset;
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+ struct qcom_pcie_ops *ops;
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+};
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+
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+#define to_qcom_pcie(x) container_of(x, struct qcom_pcie, pp)
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+
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+static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
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+{
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+ gpiod_set_value(pcie->reset, 1);
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+ usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
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+}
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+
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+static void qcom_ep_reset_deassert(struct qcom_pcie *pcie)
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+{
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+ gpiod_set_value(pcie->reset, 0);
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+ usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
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+}
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+
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+static irqreturn_t qcom_pcie_msi_irq_handler(int irq, void *arg)
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+{
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+ struct pcie_port *pp = arg;
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+
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+ return dw_handle_msi_irq(pp);
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+}
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+
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+static int qcom_pcie_establish_link(struct qcom_pcie *pcie)
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+{
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+ struct device *dev = pcie->dev;
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+ unsigned int retries = 0;
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+ u32 val;
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+
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+ if (dw_pcie_link_up(&pcie->pp))
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+ return 0;
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+
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+ /* enable link training */
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+ val = readl(pcie->elbi + PCIE20_ELBI_SYS_CTRL);
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+ val |= PCIE20_ELBI_SYS_CTRL_LT_ENABLE;
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+ writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);
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+
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+ do {
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+ if (dw_pcie_link_up(&pcie->pp))
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+ return 0;
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+ usleep_range(250, 1000);
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+ } while (retries < 200);
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+
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+ dev_warn(dev, "phy link never came up\n");
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+
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+ return -ETIMEDOUT;
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+}
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+
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+static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie)
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+{
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+ struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
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+ struct device *dev = pcie->dev;
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+
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+ res->vdda = devm_regulator_get(dev, "vdda");
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+ if (IS_ERR(res->vdda))
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+ return PTR_ERR(res->vdda);
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+
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+ res->vdda_phy = devm_regulator_get(dev, "vdda_phy");
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+ if (IS_ERR(res->vdda_phy))
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+ return PTR_ERR(res->vdda_phy);
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+
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+ res->vdda_refclk = devm_regulator_get(dev, "vdda_refclk");
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+ if (IS_ERR(res->vdda_refclk))
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+ return PTR_ERR(res->vdda_refclk);
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+
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+ res->iface_clk = devm_clk_get(dev, "iface");
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+ if (IS_ERR(res->iface_clk))
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+ return PTR_ERR(res->iface_clk);
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+
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+ res->core_clk = devm_clk_get(dev, "core");
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+ if (IS_ERR(res->core_clk))
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+ return PTR_ERR(res->core_clk);
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+
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+ res->phy_clk = devm_clk_get(dev, "phy");
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+ if (IS_ERR(res->phy_clk))
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+ return PTR_ERR(res->phy_clk);
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+
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+ res->pci_reset = devm_reset_control_get(dev, "pci");
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+ if (IS_ERR(res->pci_reset))
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+ return PTR_ERR(res->pci_reset);
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+
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+ res->axi_reset = devm_reset_control_get(dev, "axi");
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+ if (IS_ERR(res->axi_reset))
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+ return PTR_ERR(res->axi_reset);
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+
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+ res->ahb_reset = devm_reset_control_get(dev, "ahb");
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+ if (IS_ERR(res->ahb_reset))
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+ return PTR_ERR(res->ahb_reset);
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+
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+ res->por_reset = devm_reset_control_get(dev, "por");
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+ if (IS_ERR(res->por_reset))
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+ return PTR_ERR(res->por_reset);
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+
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+ res->phy_reset = devm_reset_control_get(dev, "phy");
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+ if (IS_ERR(res->phy_reset))
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+ return PTR_ERR(res->phy_reset);
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+
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+ return 0;
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+}
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+
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+static int qcom_pcie_get_resources_v1(struct qcom_pcie *pcie)
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+{
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+ struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
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+ struct device *dev = pcie->dev;
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+
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+ res->vdda = devm_regulator_get(dev, "vdda");
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+ if (IS_ERR(res->vdda))
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+ return PTR_ERR(res->vdda);
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+
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+ res->iface = devm_clk_get(dev, "iface");
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+ if (IS_ERR(res->iface))
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+ return PTR_ERR(res->iface);
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+
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+ res->aux = devm_clk_get(dev, "aux");
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+ if (IS_ERR(res->aux))
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+ return PTR_ERR(res->aux);
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+
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+ res->master_bus = devm_clk_get(dev, "master_bus");
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+ if (IS_ERR(res->master_bus))
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+ return PTR_ERR(res->master_bus);
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+
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+ res->slave_bus = devm_clk_get(dev, "slave_bus");
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+ if (IS_ERR(res->slave_bus))
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+ return PTR_ERR(res->slave_bus);
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+
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+ res->core = devm_reset_control_get(dev, "core");
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+ if (IS_ERR(res->core))
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+ return PTR_ERR(res->core);
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+
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+ return 0;
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+}
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+
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+static void qcom_pcie_deinit_v0(struct qcom_pcie *pcie)
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+{
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+ struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
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+
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+ reset_control_assert(res->pci_reset);
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+ reset_control_assert(res->axi_reset);
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+ reset_control_assert(res->ahb_reset);
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+ reset_control_assert(res->por_reset);
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+ reset_control_assert(res->pci_reset);
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+ clk_disable_unprepare(res->iface_clk);
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+ clk_disable_unprepare(res->core_clk);
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+ clk_disable_unprepare(res->phy_clk);
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+ regulator_disable(res->vdda);
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+ regulator_disable(res->vdda_phy);
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+ regulator_disable(res->vdda_refclk);
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+}
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+
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+static int qcom_pcie_init_v0(struct qcom_pcie *pcie)
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+{
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+ struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
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+ struct device *dev = pcie->dev;
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+ u32 val;
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+ int ret;
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+
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+ ret = regulator_enable(res->vdda);
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+ if (ret) {
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+ dev_err(dev, "cannot enable vdda regulator\n");
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+ return ret;
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+ }
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+
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+ ret = regulator_enable(res->vdda_refclk);
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+ if (ret) {
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+ dev_err(dev, "cannot enable vdda_refclk regulator\n");
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+ goto err_refclk;
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+ }
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+
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+ ret = regulator_enable(res->vdda_phy);
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+ if (ret) {
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+ dev_err(dev, "cannot enable vdda_phy regulator\n");
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+ goto err_vdda_phy;
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+ }
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+
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+ ret = reset_control_assert(res->ahb_reset);
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+ if (ret) {
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+ dev_err(dev, "cannot assert ahb reset\n");
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+ goto err_assert_ahb;
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+ }
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+
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+ ret = clk_prepare_enable(res->iface_clk);
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+ if (ret) {
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+ dev_err(dev, "cannot prepare/enable iface clock\n");
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+ goto err_assert_ahb;
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+ }
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+
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+ ret = clk_prepare_enable(res->phy_clk);
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+ if (ret) {
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+ dev_err(dev, "cannot prepare/enable phy clock\n");
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+ goto err_clk_phy;
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+ }
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+
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+ ret = clk_prepare_enable(res->core_clk);
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+ if (ret) {
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+ dev_err(dev, "cannot prepare/enable core clock\n");
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+ goto err_clk_core;
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+ }
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+
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+ ret = reset_control_deassert(res->ahb_reset);
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+ if (ret) {
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+ dev_err(dev, "cannot deassert ahb reset\n");
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+ goto err_deassert_ahb;
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+ }
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+
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+ /* enable PCIe clocks and resets */
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+ val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
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+ val &= ~BIT(0);
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+ writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
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+
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+ /* enable external reference clock */
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+ val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
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+ val |= BIT(16);
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+ writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
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+
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+ ret = reset_control_deassert(res->phy_reset);
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+ if (ret) {
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+ dev_err(dev, "cannot deassert phy reset\n");
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+ return ret;
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+ }
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+
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+ ret = reset_control_deassert(res->pci_reset);
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+ if (ret) {
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+ dev_err(dev, "cannot deassert pci reset\n");
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+ return ret;
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+ }
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+
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+ ret = reset_control_deassert(res->por_reset);
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+ if (ret) {
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+ dev_err(dev, "cannot deassert por reset\n");
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+ return ret;
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+ }
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+
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+ ret = reset_control_deassert(res->axi_reset);
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+ if (ret) {
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+ dev_err(dev, "cannot deassert axi reset\n");
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+ return ret;
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+ }
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+
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+ /* wait for clock acquisition */
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+ usleep_range(1000, 1500);
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+
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+ return 0;
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+
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+err_deassert_ahb:
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+ clk_disable_unprepare(res->core_clk);
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+err_clk_core:
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+ clk_disable_unprepare(res->phy_clk);
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+err_clk_phy:
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+ clk_disable_unprepare(res->iface_clk);
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+err_assert_ahb:
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+ regulator_disable(res->vdda_phy);
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+err_vdda_phy:
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+ regulator_disable(res->vdda_refclk);
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+err_refclk:
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+ regulator_disable(res->vdda);
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+
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+ return ret;
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+}
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+
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+static void qcom_pcie_deinit_v1(struct qcom_pcie *pcie)
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+{
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+ struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
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+
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+ reset_control_assert(res->core);
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+ clk_disable_unprepare(res->slave_bus);
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+ clk_disable_unprepare(res->master_bus);
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+ clk_disable_unprepare(res->iface);
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+ clk_disable_unprepare(res->aux);
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+ regulator_disable(res->vdda);
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+}
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+
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+static int qcom_pcie_init_v1(struct qcom_pcie *pcie)
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+{
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+ struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
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+ struct device *dev = pcie->dev;
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+ int ret;
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+
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+ ret = reset_control_deassert(res->core);
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+ if (ret) {
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+ dev_err(dev, "cannot deassert core reset\n");
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+ return ret;
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+ }
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+
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+ ret = clk_prepare_enable(res->aux);
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+ if (ret) {
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+ dev_err(dev, "cannot prepare/enable aux clock\n");
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+ goto err_res;
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+ }
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+
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+ ret = clk_prepare_enable(res->iface);
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+ if (ret) {
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+ dev_err(dev, "cannot prepare/enable iface clock\n");
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+ goto err_aux;
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+ }
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+
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+ ret = clk_prepare_enable(res->master_bus);
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+ if (ret) {
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+ dev_err(dev, "cannot prepare/enable master_bus clock\n");
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+ goto err_iface;
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+ }
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+
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+ ret = clk_prepare_enable(res->slave_bus);
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+ if (ret) {
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|
+ dev_err(dev, "cannot prepare/enable slave_bus clock\n");
|
|
|
+ goto err_master;
|
|
|
+ }
|
|
|
+
|
|
|
+ ret = regulator_enable(res->vdda);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(dev, "cannot enable vdda regulator\n");
|
|
|
+ goto err_slave;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* change DBI base address */
|
|
|
+ writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
|
|
|
+
|
|
|
+ if (IS_ENABLED(CONFIG_PCI_MSI)) {
|
|
|
+ u32 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
|
|
|
+
|
|
|
+ val |= BIT(31);
|
|
|
+ writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+err_slave:
|
|
|
+ clk_disable_unprepare(res->slave_bus);
|
|
|
+err_master:
|
|
|
+ clk_disable_unprepare(res->master_bus);
|
|
|
+err_iface:
|
|
|
+ clk_disable_unprepare(res->iface);
|
|
|
+err_aux:
|
|
|
+ clk_disable_unprepare(res->aux);
|
|
|
+err_res:
|
|
|
+ reset_control_assert(res->core);
|
|
|
+
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+static int qcom_pcie_link_up(struct pcie_port *pp)
|
|
|
+{
|
|
|
+ struct qcom_pcie *pcie = to_qcom_pcie(pp);
|
|
|
+ u16 val = readw(pcie->dbi + PCIE20_CAP + PCI_EXP_LNKSTA);
|
|
|
+
|
|
|
+ return !!(val & PCI_EXP_LNKSTA_DLLLA);
|
|
|
+}
|
|
|
+
|
|
|
+static void qcom_pcie_host_init(struct pcie_port *pp)
|
|
|
+{
|
|
|
+ struct qcom_pcie *pcie = to_qcom_pcie(pp);
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ qcom_ep_reset_assert(pcie);
|
|
|
+
|
|
|
+ ret = pcie->ops->init(pcie);
|
|
|
+ if (ret)
|
|
|
+ goto err_deinit;
|
|
|
+
|
|
|
+ ret = phy_power_on(pcie->phy);
|
|
|
+ if (ret)
|
|
|
+ goto err_deinit;
|
|
|
+
|
|
|
+ dw_pcie_setup_rc(pp);
|
|
|
+
|
|
|
+ if (IS_ENABLED(CONFIG_PCI_MSI))
|
|
|
+ dw_pcie_msi_init(pp);
|
|
|
+
|
|
|
+ qcom_ep_reset_deassert(pcie);
|
|
|
+
|
|
|
+ ret = qcom_pcie_establish_link(pcie);
|
|
|
+ if (ret)
|
|
|
+ goto err;
|
|
|
+
|
|
|
+ return;
|
|
|
+err:
|
|
|
+ qcom_ep_reset_assert(pcie);
|
|
|
+ phy_power_off(pcie->phy);
|
|
|
+err_deinit:
|
|
|
+ pcie->ops->deinit(pcie);
|
|
|
+}
|
|
|
+
|
|
|
+static int qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
|
|
|
+ u32 *val)
|
|
|
+{
|
|
|
+ /* the device class is not reported correctly from the register */
|
|
|
+ if (where == PCI_CLASS_REVISION && size == 4) {
|
|
|
+ *val = readl(pp->dbi_base + PCI_CLASS_REVISION);
|
|
|
+ *val &= 0xff; /* keep revision id */
|
|
|
+ *val |= PCI_CLASS_BRIDGE_PCI << 16;
|
|
|
+ return PCIBIOS_SUCCESSFUL;
|
|
|
+ }
|
|
|
+
|
|
|
+ return dw_pcie_cfg_read(pp->dbi_base + where, size, val);
|
|
|
+}
|
|
|
+
|
|
|
+static struct pcie_host_ops qcom_pcie_dw_ops = {
|
|
|
+ .link_up = qcom_pcie_link_up,
|
|
|
+ .host_init = qcom_pcie_host_init,
|
|
|
+ .rd_own_conf = qcom_pcie_rd_own_conf,
|
|
|
+};
|
|
|
+
|
|
|
+static const struct qcom_pcie_ops ops_v0 = {
|
|
|
+ .get_resources = qcom_pcie_get_resources_v0,
|
|
|
+ .init = qcom_pcie_init_v0,
|
|
|
+ .deinit = qcom_pcie_deinit_v0,
|
|
|
+};
|
|
|
+
|
|
|
+static const struct qcom_pcie_ops ops_v1 = {
|
|
|
+ .get_resources = qcom_pcie_get_resources_v1,
|
|
|
+ .init = qcom_pcie_init_v1,
|
|
|
+ .deinit = qcom_pcie_deinit_v1,
|
|
|
+};
|
|
|
+
|
|
|
+static int qcom_pcie_probe(struct platform_device *pdev)
|
|
|
+{
|
|
|
+ struct device *dev = &pdev->dev;
|
|
|
+ struct resource *res;
|
|
|
+ struct qcom_pcie *pcie;
|
|
|
+ struct pcie_port *pp;
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
|
|
|
+ if (!pcie)
|
|
|
+ return -ENOMEM;
|
|
|
+
|
|
|
+ pcie->ops = (struct qcom_pcie_ops *)of_device_get_match_data(dev);
|
|
|
+ pcie->dev = dev;
|
|
|
+
|
|
|
+ pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_LOW);
|
|
|
+ if (IS_ERR(pcie->reset))
|
|
|
+ return PTR_ERR(pcie->reset);
|
|
|
+
|
|
|
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
|
|
|
+ pcie->parf = devm_ioremap_resource(dev, res);
|
|
|
+ if (IS_ERR(pcie->parf))
|
|
|
+ return PTR_ERR(pcie->parf);
|
|
|
+
|
|
|
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
|
|
|
+ pcie->dbi = devm_ioremap_resource(dev, res);
|
|
|
+ if (IS_ERR(pcie->dbi))
|
|
|
+ return PTR_ERR(pcie->dbi);
|
|
|
+
|
|
|
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");
|
|
|
+ pcie->elbi = devm_ioremap_resource(dev, res);
|
|
|
+ if (IS_ERR(pcie->elbi))
|
|
|
+ return PTR_ERR(pcie->elbi);
|
|
|
+
|
|
|
+ pcie->phy = devm_phy_optional_get(dev, "pciephy");
|
|
|
+ if (IS_ERR(pcie->phy))
|
|
|
+ return PTR_ERR(pcie->phy);
|
|
|
+
|
|
|
+ ret = pcie->ops->get_resources(pcie);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ pp = &pcie->pp;
|
|
|
+ pp->dev = dev;
|
|
|
+ pp->dbi_base = pcie->dbi;
|
|
|
+ pp->root_bus_nr = -1;
|
|
|
+ pp->ops = &qcom_pcie_dw_ops;
|
|
|
+
|
|
|
+ if (IS_ENABLED(CONFIG_PCI_MSI)) {
|
|
|
+ pp->msi_irq = platform_get_irq_byname(pdev, "msi");
|
|
|
+ if (pp->msi_irq < 0)
|
|
|
+ return pp->msi_irq;
|
|
|
+
|
|
|
+ ret = devm_request_irq(dev, pp->msi_irq,
|
|
|
+ qcom_pcie_msi_irq_handler,
|
|
|
+ IRQF_SHARED, "qcom-pcie-msi", pp);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(dev, "cannot request msi irq\n");
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ ret = phy_init(pcie->phy);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ ret = dw_pcie_host_init(pp);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(dev, "cannot initialize host\n");
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ platform_set_drvdata(pdev, pcie);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int qcom_pcie_remove(struct platform_device *pdev)
|
|
|
+{
|
|
|
+ struct qcom_pcie *pcie = platform_get_drvdata(pdev);
|
|
|
+
|
|
|
+ qcom_ep_reset_assert(pcie);
|
|
|
+ phy_power_off(pcie->phy);
|
|
|
+ phy_exit(pcie->phy);
|
|
|
+ pcie->ops->deinit(pcie);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static const struct of_device_id qcom_pcie_match[] = {
|
|
|
+ { .compatible = "qcom,pcie-ipq8064", .data = &ops_v0 },
|
|
|
+ { .compatible = "qcom,pcie-apq8064", .data = &ops_v0 },
|
|
|
+ { .compatible = "qcom,pcie-apq8084", .data = &ops_v1 },
|
|
|
+ { }
|
|
|
+};
|
|
|
+MODULE_DEVICE_TABLE(of, qcom_pcie_match);
|
|
|
+
|
|
|
+static struct platform_driver qcom_pcie_driver = {
|
|
|
+ .probe = qcom_pcie_probe,
|
|
|
+ .remove = qcom_pcie_remove,
|
|
|
+ .driver = {
|
|
|
+ .name = "qcom-pcie",
|
|
|
+ .of_match_table = qcom_pcie_match,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+module_platform_driver(qcom_pcie_driver);
|
|
|
+
|
|
|
+MODULE_AUTHOR("Stanimir Varbanov <svarbanov@mm-sol.com>");
|
|
|
+MODULE_DESCRIPTION("Qualcomm PCIe root complex driver");
|
|
|
+MODULE_LICENSE("GPL v2");
|
Bjorn Helgaas
9 年之前