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@@ -95,6 +95,11 @@
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#define H1_PCIEPHYDOUTR 0x040014
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#define H1_PCIEPHYSR 0x040018
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+/* R-Car Gen2 PHY */
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+#define GEN2_PCIEPHYADDR 0x780
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+#define GEN2_PCIEPHYDATA 0x784
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+#define GEN2_PCIEPHYCTRL 0x78c
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+
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#define INT_PCI_MSI_NR 32
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#define RCONF(x) (PCICONF(0)+(x))
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@@ -568,6 +573,26 @@ static int rcar_pcie_hw_init_h1(struct rcar_pcie *pcie)
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return -ETIMEDOUT;
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}
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+static int rcar_pcie_hw_init_gen2(struct rcar_pcie *pcie)
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+{
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+ /*
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+ * These settings come from the R-Car Series, 2nd Generation User's
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+ * Manual, section 50.3.1 (2) Initialization of the physical layer.
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+ */
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+ rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR);
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+ rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA);
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+ rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
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+ rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
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+
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+ rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR);
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+ /* The following value is for DC connection, no termination resistor */
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+ rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA);
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+ rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
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+ rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
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+
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+ return rcar_pcie_hw_init(pcie);
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+}
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+
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static int rcar_msi_alloc(struct rcar_msi *chip)
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{
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int msi;
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@@ -907,9 +932,9 @@ static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie,
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static const struct of_device_id rcar_pcie_of_match[] = {
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{ .compatible = "renesas,pcie-r8a7779", .data = rcar_pcie_hw_init_h1 },
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- { .compatible = "renesas,pcie-rcar-gen2", .data = rcar_pcie_hw_init },
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- { .compatible = "renesas,pcie-r8a7790", .data = rcar_pcie_hw_init },
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- { .compatible = "renesas,pcie-r8a7791", .data = rcar_pcie_hw_init },
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+ { .compatible = "renesas,pcie-rcar-gen2", .data = rcar_pcie_hw_init_gen2 },
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+ { .compatible = "renesas,pcie-r8a7790", .data = rcar_pcie_hw_init_gen2 },
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+ { .compatible = "renesas,pcie-r8a7791", .data = rcar_pcie_hw_init_gen2 },
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{ .compatible = "renesas,pcie-r8a7795", .data = rcar_pcie_hw_init },
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{},
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};
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