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Merge branch 'mips-for-linux-next' of git://git.linux-mips.org/pub/scm/ralf/upstream-sfr

Pull MIPS updates from Ralf Baechle:
 - Support for Imgtec's Aptiv family of MIPS cores.
 - Improved detection of BCM47xx configurations.
 - Fix hiberation for certain configurations.
 - Add support for the Chinese Loongson 3 CPU, a MIPS64 R2 core and
   systems.
 - Detection and support for the MIPS P5600 core.
 - A few more random fixes that didn't make 3.14.
 - Support for the EVA Extended Virtual Addressing
 - Switch Alchemy to the platform PATA driver
 - Complete unification of Alchemy support
 - Allow availability of I/O cache coherency to be runtime detected
 - Improvments to multiprocessing support for Imgtec platforms
 - A few microoptimizations
 - Cleanups of FPU support
 - Paul Gortmaker's fixes for the init stuff
 - Support for seccomp

* 'mips-for-linux-next' of git://git.linux-mips.org/pub/scm/ralf/upstream-sfr: (165 commits)
  MIPS: CPC: Use __raw_ memory access functions
  MIPS: CM: use __raw_ memory access functions
  MIPS: Fix warning when including smp-ops.h with CONFIG_SMP=n
  MIPS: Malta: GIC IPIs may be used without MT
  MIPS: smp-mt: Use common GIC IPI implementation
  MIPS: smp-cmp: Remove incorrect core number probe
  MIPS: Fix gigaton of warning building with microMIPS.
  MIPS: Fix core number detection for MT cores
  MIPS: MT: core_nvpes function to retrieve VPE count
  MIPS: Provide empty mips_mt_set_cpuoptions when CONFIG_MIPS_MT=n
  MIPS: Lasat: Replace del_timer by del_timer_sync
  MIPS: Malta: Setup PM I/O region on boot
  MIPS: Loongson: Add a Loongson-3 default config file
  MIPS: Loongson 3: Add CPU hotplug support
  MIPS: Loongson 3: Add Loongson-3 SMP support
  MIPS: Loongson: Add Loongson-3 Kconfig options
  MIPS: Loongson: Add swiotlb to support All-Memory DMA
  MIPS: Loongson 3: Add serial port support
  MIPS: Loongson 3: Add IRQ init and dispatch support
  MIPS: Loongson 3: Add HT-linked PCI support
  ...
Linus Torvalds 11 ani în urmă
părinte
62d1a3ba5a ade63aada7
comite
bdfc7cbdee
100 a modificat fișierele cu 4251 adăugiri și 1590 ștergeri
Vedere unificată Arată Statisticile Diff
  1. 125 10
      arch/mips/Kconfig
  2. 7 3
      arch/mips/Kconfig.debug
  3. 5 0
      arch/mips/Makefile
  4. 8 16
      arch/mips/alchemy/Kconfig
  5. 5 11
      arch/mips/alchemy/Platform
  6. 10 0
      arch/mips/alchemy/common/setup.c
  7. 3 3
      arch/mips/alchemy/common/sleeper.S
  8. 1 3
      arch/mips/alchemy/devboards/Makefile
  9. 12 35
      arch/mips/alchemy/devboards/db1000.c
  10. 70 8
      arch/mips/alchemy/devboards/db1200.c
  11. 38 2
      arch/mips/alchemy/devboards/db1300.c
  12. 8 2
      arch/mips/alchemy/devboards/db1550.c
  13. 34 7
      arch/mips/alchemy/devboards/db1xxx.c
  14. 1 0
      arch/mips/ar7/time.c
  15. 1 1
      arch/mips/bcm47xx/Makefile
  16. 3 0
      arch/mips/bcm47xx/bcm47xx_private.h
  17. 24 1
      arch/mips/bcm47xx/board.c
  18. 31 0
      arch/mips/bcm47xx/buttons.c
  19. 49 0
      arch/mips/bcm47xx/leds.c
  20. 2 1
      arch/mips/bcm47xx/setup.c
  21. 31 0
      arch/mips/bcm47xx/workarounds.c
  22. 1 2
      arch/mips/bcm63xx/cpu.c
  23. 0 359
      arch/mips/configs/db1000_defconfig
  24. 0 434
      arch/mips/configs/db1235_defconfig
  25. 245 0
      arch/mips/configs/db1xxx_defconfig
  26. 362 0
      arch/mips/configs/loongson3_defconfig
  27. 3 6
      arch/mips/configs/malta_defconfig
  28. 3 7
      arch/mips/configs/malta_kvm_defconfig
  29. 1 6
      arch/mips/configs/malta_kvm_guest_defconfig
  30. 1 2
      arch/mips/configs/maltaaprp_defconfig
  31. 2 2
      arch/mips/configs/maltasmtc_defconfig
  32. 3 2
      arch/mips/configs/maltasmvp_defconfig
  33. 200 0
      arch/mips/configs/maltasmvp_eva_defconfig
  34. 1 2
      arch/mips/configs/maltaup_defconfig
  35. 135 0
      arch/mips/include/asm/asm-eva.h
  36. 11 2
      arch/mips/include/asm/asm.h
  37. 64 64
      arch/mips/include/asm/asmmacro-32.h
  38. 266 64
      arch/mips/include/asm/asmmacro.h
  39. 20 20
      arch/mips/include/asm/atomic.h
  40. 14 14
      arch/mips/include/asm/bitops.h
  41. 17 9
      arch/mips/include/asm/bootinfo.h
  42. 37 7
      arch/mips/include/asm/checksum.h
  43. 10 10
      arch/mips/include/asm/cmpxchg.h
  44. 9 1
      arch/mips/include/asm/cpu-features.h
  45. 28 0
      arch/mips/include/asm/cpu-info.h
  46. 6 0
      arch/mips/include/asm/cpu-type.h
  47. 10 5
      arch/mips/include/asm/cpu.h
  48. 5 0
      arch/mips/include/asm/dma-mapping.h
  49. 1 1
      arch/mips/include/asm/fpu.h
  50. 13 12
      arch/mips/include/asm/futex.h
  51. 1 1
      arch/mips/include/asm/fw/fw.h
  52. 0 125
      arch/mips/include/asm/gcmpregs.h
  53. 3 0
      arch/mips/include/asm/gic.h
  54. 4 4
      arch/mips/include/asm/io.h
  55. 4 4
      arch/mips/include/asm/local.h
  56. 0 12
      arch/mips/include/asm/mach-au1x00/au1000.h
  57. 7 1
      arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
  58. 0 91
      arch/mips/include/asm/mach-db1x00/db1200.h
  59. 0 40
      arch/mips/include/asm/mach-db1x00/db1300.h
  60. 163 0
      arch/mips/include/asm/mach-loongson/boot_param.h
  61. 21 1
      arch/mips/include/asm/mach-loongson/dma-coherence.h
  62. 44 0
      arch/mips/include/asm/mach-loongson/irq.h
  63. 23 5
      arch/mips/include/asm/mach-loongson/loongson.h
  64. 6 0
      arch/mips/include/asm/mach-loongson/machine.h
  65. 5 0
      arch/mips/include/asm/mach-loongson/pci.h
  66. 9 0
      arch/mips/include/asm/mach-loongson/spaces.h
  67. 114 1
      arch/mips/include/asm/mach-malta/kernel-entry-init.h
  68. 46 0
      arch/mips/include/asm/mach-malta/spaces.h
  69. 6 6
      arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h
  70. 5 0
      arch/mips/include/asm/mips-boards/malta.h
  71. 5 0
      arch/mips/include/asm/mips-boards/piix4.h
  72. 322 0
      arch/mips/include/asm/mips-cm.h
  73. 150 0
      arch/mips/include/asm/mips-cpc.h
  74. 5 0
      arch/mips/include/asm/mips_mt.h
  75. 11 0
      arch/mips/include/asm/mipsmtregs.h
  76. 22 0
      arch/mips/include/asm/mipsregs.h
  77. 2 0
      arch/mips/include/asm/module.h
  78. 203 0
      arch/mips/include/asm/msa.h
  79. 2 0
      arch/mips/include/asm/page.h
  80. 9 0
      arch/mips/include/asm/pgtable-bits.h
  81. 38 7
      arch/mips/include/asm/processor.h
  82. 1 1
      arch/mips/include/asm/ptrace.h
  83. 172 3
      arch/mips/include/asm/r4kcache.h
  84. 2 0
      arch/mips/include/asm/sigcontext.h
  85. 33 0
      arch/mips/include/asm/smp-cps.h
  86. 17 0
      arch/mips/include/asm/smp-ops.h
  87. 1 0
      arch/mips/include/asm/smp.h
  88. 1 1
      arch/mips/include/asm/stackframe.h
  89. 17 5
      arch/mips/include/asm/switch_to.h
  90. 29 3
      arch/mips/include/asm/syscall.h
  91. 6 1
      arch/mips/include/asm/thread_info.h
  92. 432 127
      arch/mips/include/asm/uaccess.h
  93. 21 4
      arch/mips/include/uapi/asm/inst.h
  94. 8 0
      arch/mips/include/uapi/asm/sigcontext.h
  95. 5 0
      arch/mips/kernel/Makefile
  96. 82 0
      arch/mips/kernel/asm-offsets.c
  97. 1 1
      arch/mips/kernel/bmips_vec.S
  98. 191 0
      arch/mips/kernel/cps-vec.S
  99. 62 12
      arch/mips/kernel/cpu-probe.c
  100. 4 0
      arch/mips/kernel/ftrace.c

+ 125 - 10
arch/mips/Kconfig
Vizualizați fișierul 

@@ -10,6 +10,7 @@ config MIPS
 
 	select HAVE_PERF_EVENTS
 
 	select HAVE_PERF_EVENTS
 
 	select PERF_USE_VMALLOC
 
 	select PERF_USE_VMALLOC
 
 	select HAVE_ARCH_KGDB
 
 	select HAVE_ARCH_KGDB
 
+	select HAVE_ARCH_SECCOMP_FILTER
 
 	select HAVE_ARCH_TRACEHOOK
 
 	select HAVE_ARCH_TRACEHOOK
 
 	select ARCH_HAVE_CUSTOM_GPIO_H
 
 	select ARCH_HAVE_CUSTOM_GPIO_H
 
 	select HAVE_FUNCTION_TRACER
 
 	select HAVE_FUNCTION_TRACER
 
@@ -62,6 +63,7 @@ config MIPS_ALCHEMY
 
 	select CEVT_R4K
 
 	select CEVT_R4K
 
 	select CSRC_R4K
 
 	select CSRC_R4K
 
 	select IRQ_CPU
 
 	select IRQ_CPU
 
+	select DMA_MAYBE_COHERENT	# Au1000,1500,1100 aren't, rest is
 
 	select SYS_HAS_CPU_MIPS32_R1
 
 	select SYS_HAS_CPU_MIPS32_R1
 
 	select SYS_SUPPORTS_32BIT_KERNEL
 
 	select SYS_SUPPORTS_32BIT_KERNEL
 
 	select SYS_SUPPORTS_APM_EMULATION
 
 	select SYS_SUPPORTS_APM_EMULATION
 
@@ -121,7 +123,7 @@ config BCM47XX
 
 	select SYS_SUPPORTS_32BIT_KERNEL
 
 	select SYS_SUPPORTS_32BIT_KERNEL
 
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 
 	select SYS_HAS_EARLY_PRINTK
 
 	select SYS_HAS_EARLY_PRINTK
 
-	select EARLY_PRINTK_8250 if EARLY_PRINTK
 
+	select USE_GENERIC_EARLY_PRINTK_8250
 
 	help
 
 	help
 
 	 Support for BCM47XX based boards
 
 	 Support for BCM47XX based boards
 
 
 
@@ -148,7 +150,6 @@ config MIPS_COBALT
 
 	select CSRC_R4K
 
 	select CSRC_R4K
 
 	select CEVT_GT641XX
 
 	select CEVT_GT641XX
 
 	select DMA_NONCOHERENT
 
 	select DMA_NONCOHERENT
 
-	select EARLY_PRINTK_8250 if EARLY_PRINTK
 
 	select HW_HAS_PCI
 
 	select HW_HAS_PCI
 
 	select I8253
 
 	select I8253
 
 	select I8259
 
 	select I8259
 
@@ -161,6 +162,7 @@ config MIPS_COBALT
 
 	select SYS_SUPPORTS_32BIT_KERNEL
 
 	select SYS_SUPPORTS_32BIT_KERNEL
 
 	select SYS_SUPPORTS_64BIT_KERNEL
 
 	select SYS_SUPPORTS_64BIT_KERNEL
 
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 
+	select USE_GENERIC_EARLY_PRINTK_8250
 
 
 
 config MACH_DECSTATION
 
 config MACH_DECSTATION
 
 	bool "DECstations"
 
 	bool "DECstations"
 
@@ -233,7 +235,6 @@ config MACH_JZ4740
 
 	select IRQ_CPU
 
 	select IRQ_CPU
 
 	select ARCH_REQUIRE_GPIOLIB
 
 	select ARCH_REQUIRE_GPIOLIB
 
 	select SYS_HAS_EARLY_PRINTK
 
 	select SYS_HAS_EARLY_PRINTK
 
-	select HAVE_PWM
 
 	select HAVE_CLK
 
 	select HAVE_CLK
 
 	select GENERIC_IRQ_CHIP
 
 	select GENERIC_IRQ_CHIP
 
 
 
@@ -318,6 +319,7 @@ config MIPS_MALTA
 
 	select SWAP_IO_SPACE
 
 	select SWAP_IO_SPACE
 
 	select SYS_HAS_CPU_MIPS32_R1
 
 	select SYS_HAS_CPU_MIPS32_R1
 
 	select SYS_HAS_CPU_MIPS32_R2
 
 	select SYS_HAS_CPU_MIPS32_R2
 
+	select SYS_HAS_CPU_MIPS32_R3_5
 
 	select SYS_HAS_CPU_MIPS64_R1
 
 	select SYS_HAS_CPU_MIPS64_R1
 
 	select SYS_HAS_CPU_MIPS64_R2
 
 	select SYS_HAS_CPU_MIPS64_R2
 
 	select SYS_HAS_CPU_NEVADA
 
 	select SYS_HAS_CPU_NEVADA
 
@@ -327,6 +329,7 @@ config MIPS_MALTA
 
 	select SYS_SUPPORTS_BIG_ENDIAN
 
 	select SYS_SUPPORTS_BIG_ENDIAN
 
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 
 	select SYS_SUPPORTS_MIPS_CMP
 
 	select SYS_SUPPORTS_MIPS_CMP
 
+	select SYS_SUPPORTS_MIPS_CPS
 
 	select SYS_SUPPORTS_MULTITHREADING
 
 	select SYS_SUPPORTS_MULTITHREADING
 
 	select SYS_SUPPORTS_SMARTMIPS
 
 	select SYS_SUPPORTS_SMARTMIPS
 
 	select SYS_SUPPORTS_ZBOOT
 
 	select SYS_SUPPORTS_ZBOOT
 
@@ -671,6 +674,7 @@ config SNI_RM
 
 	select SYS_SUPPORTS_BIG_ENDIAN
 
 	select SYS_SUPPORTS_BIG_ENDIAN
 
 	select SYS_SUPPORTS_HIGHMEM
 
 	select SYS_SUPPORTS_HIGHMEM
 
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 
+	select USE_GENERIC_EARLY_PRINTK_8250
 
 	help
 
 	help
 
 	  The SNI RM200/300/400 are MIPS-based machines manufactured by
 
 	  The SNI RM200/300/400 are MIPS-based machines manufactured by
 
 	  Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
 
 	  Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
 
@@ -775,7 +779,6 @@ config NLM_XLP_BOARD
 
 	select CEVT_R4K
 
 	select CEVT_R4K
 
 	select CSRC_R4K
 
 	select CSRC_R4K
 
 	select IRQ_CPU
 
 	select IRQ_CPU
 
-	select ARCH_SUPPORTS_MSI
 
 	select ZONE_DMA32 if 64BIT
 
 	select ZONE_DMA32 if 64BIT
 
 	select SYNC_R4K
 
 	select SYNC_R4K
 
 	select SYS_HAS_EARLY_PRINTK
 
 	select SYS_HAS_EARLY_PRINTK
 
@@ -861,6 +864,7 @@ config CEVT_R4K
 
 	bool
 
 	bool
 
 
 
 config CEVT_GIC
 
 config CEVT_GIC
 
+	select MIPS_CM
 
 	bool
 
 	bool
 
 
 
 config CEVT_SB1250
 
 config CEVT_SB1250
 
@@ -879,6 +883,7 @@ config CSRC_R4K
 
 	bool
 
 	bool
 
 
 
 config CSRC_GIC
 
 config CSRC_GIC
 
+	select MIPS_CM
 
 	bool
 
 	bool
 
 
 
 config CSRC_SB1250
 
 config CSRC_SB1250
 
@@ -1023,6 +1028,7 @@ config IRQ_GT641XX
 
 	bool
 
 	bool
 
 
 
 config IRQ_GIC
 
 config IRQ_GIC
 
+	select MIPS_CM
 
 	bool
 
 	bool
 
 
 
 config PCI_GT64XXX_PCI0
 
 config PCI_GT64XXX_PCI0
 
@@ -1141,6 +1147,18 @@ choice
 
 	prompt "CPU type"
 
 	prompt "CPU type"
 
 	default CPU_R4X00
 
 	default CPU_R4X00
 
 
 
+config CPU_LOONGSON3
 
+	bool "Loongson 3 CPU"
 
+	depends on SYS_HAS_CPU_LOONGSON3
 
+	select CPU_SUPPORTS_64BIT_KERNEL
 
+	select CPU_SUPPORTS_HIGHMEM
 
+	select CPU_SUPPORTS_HUGEPAGES
 
+	select WEAK_ORDERING
 
+	select WEAK_REORDERING_BEYOND_LLSC
 
+	help
 
+		The Loongson 3 processor implements the MIPS64R2 instruction
 
+		set with many extensions.
 
+
 
 config CPU_LOONGSON2E
 
 config CPU_LOONGSON2E
 
 	bool "Loongson 2E"
 
 	bool "Loongson 2E"
 
 	depends on SYS_HAS_CPU_LOONGSON2E
 
 	depends on SYS_HAS_CPU_LOONGSON2E
 
@@ -1196,6 +1214,7 @@ config CPU_MIPS32_R2
 
 	select CPU_HAS_PREFETCH
 
 	select CPU_HAS_PREFETCH
 
 	select CPU_SUPPORTS_32BIT_KERNEL
 
 	select CPU_SUPPORTS_32BIT_KERNEL
 
 	select CPU_SUPPORTS_HIGHMEM
 
 	select CPU_SUPPORTS_HIGHMEM
 
+	select CPU_SUPPORTS_MSA
 
 	select HAVE_KVM
 
 	select HAVE_KVM
 
 	help
 
 	help
 
 	  Choose this option to build a kernel for release 2 or later of the
 
 	  Choose this option to build a kernel for release 2 or later of the
 
@@ -1231,6 +1250,7 @@ config CPU_MIPS64_R2
 
 	select CPU_SUPPORTS_64BIT_KERNEL
 
 	select CPU_SUPPORTS_64BIT_KERNEL
 
 	select CPU_SUPPORTS_HIGHMEM
 
 	select CPU_SUPPORTS_HIGHMEM
 
 	select CPU_SUPPORTS_HUGEPAGES
 
 	select CPU_SUPPORTS_HUGEPAGES
 
+	select CPU_SUPPORTS_MSA
 
 	help
 
 	help
 
 	  Choose this option to build a kernel for release 2 or later of the
 
 	  Choose this option to build a kernel for release 2 or later of the
 
 	  MIPS64 architecture.  Many modern embedded systems with a 64-bit
 
 	  MIPS64 architecture.  Many modern embedded systems with a 64-bit
 
@@ -1389,7 +1409,6 @@ config CPU_CAVIUM_OCTEON
 
 	select LIBFDT
 
 	select LIBFDT
 
 	select USE_OF
 
 	select USE_OF
 
 	select USB_EHCI_BIG_ENDIAN_MMIO
 
 	select USB_EHCI_BIG_ENDIAN_MMIO
 
-	select SYS_HAS_DMA_OPS
 
 	select MIPS_L1_CACHE_SHIFT_7
 
 	select MIPS_L1_CACHE_SHIFT_7
 
 	help
 
 	help
 
 	  The Cavium Octeon processor is a highly integrated chip containing
 
 	  The Cavium Octeon processor is a highly integrated chip containing
 
@@ -1441,6 +1460,26 @@ config CPU_XLP
 
 	  Netlogic Microsystems XLP processors.
 
 	  Netlogic Microsystems XLP processors.
 
 endchoice
 
 endchoice
 
 
 
+config CPU_MIPS32_3_5_FEATURES
 
+	bool "MIPS32 Release 3.5 Features"
 
+	depends on SYS_HAS_CPU_MIPS32_R3_5
 
+	depends on CPU_MIPS32_R2
 
+	help
 
+	  Choose this option to build a kernel for release 2 or later of the
 
+	  MIPS32 architecture including features from the 3.5 release such as
 
+	  support for Enhanced Virtual Addressing (EVA).
 
+
 
+config CPU_MIPS32_3_5_EVA
 
+	bool "Enhanced Virtual Addressing (EVA)"
 
+	depends on CPU_MIPS32_3_5_FEATURES
 
+	select EVA
 
+	default y
 
+	help
 
+	  Choose this option if you want to enable the Enhanced Virtual
 
+	  Addressing (EVA) on your MIPS32 core (such as proAptiv).
 
+	  One of its primary benefits is an increase in the maximum size
 
+	  of lowmem (up to 3GB). If unsure, say 'N' here.
 
+
 
 if CPU_LOONGSON2F
 
 if CPU_LOONGSON2F
 
 config CPU_NOP_WORKAROUNDS
 
 config CPU_NOP_WORKAROUNDS
 
 	bool
 
 	bool
 
@@ -1516,6 +1555,10 @@ config CPU_BMIPS5000
 
 	select SYS_SUPPORTS_SMP
 
 	select SYS_SUPPORTS_SMP
 
 	select SYS_SUPPORTS_HOTPLUG_CPU
 
 	select SYS_SUPPORTS_HOTPLUG_CPU
 
 
 
+config SYS_HAS_CPU_LOONGSON3
 
+	bool
 
+	select CPU_SUPPORTS_CPUFREQ
 
+
 
 config SYS_HAS_CPU_LOONGSON2E
 
 config SYS_HAS_CPU_LOONGSON2E
 
 	bool
 
 	bool
 
 
 
@@ -1534,6 +1577,9 @@ config SYS_HAS_CPU_MIPS32_R1
 
 config SYS_HAS_CPU_MIPS32_R2
 
 config SYS_HAS_CPU_MIPS32_R2
 
 	bool
 
 	bool
 
 
 
+config SYS_HAS_CPU_MIPS32_R3_5
 
+	bool
 
+
 
 config SYS_HAS_CPU_MIPS64_R1
 
 config SYS_HAS_CPU_MIPS64_R1
 
 	bool
 
 	bool
 
 
 
@@ -1650,6 +1696,9 @@ config CPU_MIPSR2
 
 	bool
 
 	bool
 
 	default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
 
 	default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
 
 
 
+config EVA
 
+	bool
 
+
 
 config SYS_SUPPORTS_32BIT_KERNEL
 
 config SYS_SUPPORTS_32BIT_KERNEL
 
 	bool
 
 	bool
 
 config SYS_SUPPORTS_64BIT_KERNEL
 
 config SYS_SUPPORTS_64BIT_KERNEL
 
@@ -1722,7 +1771,7 @@ choice
 
 
 
 config PAGE_SIZE_4KB
 
 config PAGE_SIZE_4KB
 
 	bool "4kB"
 
 	bool "4kB"
 
-	depends on !CPU_LOONGSON2
 
+	depends on !CPU_LOONGSON2 && !CPU_LOONGSON3
 
 	help
 
 	help
 
 	 This option select the standard 4kB Linux page size.  On some
 
 	 This option select the standard 4kB Linux page size.  On some
 
 	 R3000-family processors this is the only available page size.  Using
 
 	 R3000-family processors this is the only available page size.  Using
 
@@ -1863,6 +1912,7 @@ config MIPS_MT_SMP
 
 	select CPU_MIPSR2_IRQ_VI
 
 	select CPU_MIPSR2_IRQ_VI
 
 	select CPU_MIPSR2_IRQ_EI
 
 	select CPU_MIPSR2_IRQ_EI
 
 	select SYNC_R4K
 
 	select SYNC_R4K
 
+	select MIPS_GIC_IPI
 
 	select MIPS_MT
 
 	select MIPS_MT
 
 	select SMP
 
 	select SMP
 
 	select SMP_UP
 
 	select SMP_UP
 
@@ -1880,6 +1930,7 @@ config MIPS_MT_SMTC
 
 	bool "Use all TCs on all VPEs for SMP (DEPRECATED)"
 
 	bool "Use all TCs on all VPEs for SMP (DEPRECATED)"
 
 	depends on CPU_MIPS32_R2
 
 	depends on CPU_MIPS32_R2
 
 	depends on SYS_SUPPORTS_MULTITHREADING
 
 	depends on SYS_SUPPORTS_MULTITHREADING
 
+	depends on !MIPS_CPS
 
 	select CPU_MIPSR2_IRQ_VI
 
 	select CPU_MIPSR2_IRQ_VI
 
 	select CPU_MIPSR2_IRQ_EI
 
 	select CPU_MIPSR2_IRQ_EI
 
 	select MIPS_MT
 
 	select MIPS_MT
 
@@ -1987,13 +2038,45 @@ config MIPS_VPE_APSP_API_MT
 
 	depends on MIPS_VPE_APSP_API && !MIPS_CMP
 
 	depends on MIPS_VPE_APSP_API && !MIPS_CMP
 
 
 
 config MIPS_CMP
 
 config MIPS_CMP
 
-	bool "MIPS CMP support"
 
-	depends on SYS_SUPPORTS_MIPS_CMP && MIPS_MT_SMP
 
+	bool "MIPS CMP framework support (DEPRECATED)"
 
+	depends on SYS_SUPPORTS_MIPS_CMP && !MIPS_MT_SMTC
 
+	select MIPS_GIC_IPI
 
 	select SYNC_R4K
 
 	select SYNC_R4K
 
 	select WEAK_ORDERING
 
 	select WEAK_ORDERING
 
 	default n
 
 	default n
 
 	help
 
 	help
 
-	  Enable Coherency Manager processor (CMP) support.
 
+	  Select this if you are using a bootloader which implements the "CMP
 
+	  framework" protocol (ie. YAMON) and want your kernel to make use of
 
+	  its ability to start secondary CPUs.
 
+
 
+	  Unless you have a specific need, you should use CONFIG_MIPS_CPS
 
+	  instead of this.
 
+
 
+config MIPS_CPS
 
+	bool "MIPS Coherent Processing System support"
 
+	depends on SYS_SUPPORTS_MIPS_CPS
 
+	select MIPS_CM
 
+	select MIPS_CPC
 
+	select MIPS_GIC_IPI
 
+	select SMP
 
+	select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
 
+	select SYS_SUPPORTS_SMP
 
+	select WEAK_ORDERING
 
+	help
 
+	  Select this if you wish to run an SMP kernel across multiple cores
 
+	  within a MIPS Coherent Processing System. When this option is
 
+	  enabled the kernel will probe for other cores and boot them with
 
+	  no external assistance. It is safe to enable this when hardware
 
+	  support is unavailable.
 
+
 
+config MIPS_GIC_IPI
 
+	bool
 
+
 
+config MIPS_CM
 
+	bool
 
+
 
+config MIPS_CPC
 
+	bool
 
 
 
 config SB1_PASS_1_WORKAROUNDS
 
 config SB1_PASS_1_WORKAROUNDS
 
 	bool
 
 	bool
 
@@ -2036,6 +2119,21 @@ config CPU_MICROMIPS
 
 	  When this option is enabled the kernel will be built using the
 
 	  When this option is enabled the kernel will be built using the
 
 	  microMIPS ISA
 
 	  microMIPS ISA
 
 
 
+config CPU_HAS_MSA
 
+	bool "Support for the MIPS SIMD Architecture"
 
+	depends on CPU_SUPPORTS_MSA
 
+	default y
 
+	help
 
+	  MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
 
+	  and a set of SIMD instructions to operate on them. When this option
 
+	  is enabled the kernel will support allocating & switching MSA
 
+	  vector register contexts. If you know that your kernel will only be
 
+	  running on CPUs which do not support MSA or that your userland will
 
+	  not be making use of it then you may wish to say N here to reduce
 
+	  the size & complexity of your kernel.
 
+
 
+	  If unsure, say Y.
 
+
 
 config CPU_HAS_WB
 
 config CPU_HAS_WB
 
 	bool
 
 	bool
 
 
 
@@ -2087,7 +2185,7 @@ config CPU_R4400_WORKAROUNDS
 
 #
 
 #
 
 config HIGHMEM
 
 config HIGHMEM
 
 	bool "High Memory Support"
 
 	bool "High Memory Support"
 
-	depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM
 
+	depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
 
 
 
 config CPU_SUPPORTS_HIGHMEM
 
 config CPU_SUPPORTS_HIGHMEM
 
 	bool
 
 	bool
 
@@ -2101,6 +2199,9 @@ config SYS_SUPPORTS_SMARTMIPS
 
 config SYS_SUPPORTS_MICROMIPS
 
 config SYS_SUPPORTS_MICROMIPS
 
 	bool
 
 	bool
 
 
 
+config CPU_SUPPORTS_MSA
 
+	bool
 
+
 
 config ARCH_FLATMEM_ENABLE
 
 config ARCH_FLATMEM_ENABLE
 
 	def_bool y
 
 	def_bool y
 
 	depends on !NUMA && !CPU_LOONGSON2
 
 	depends on !NUMA && !CPU_LOONGSON2
 
@@ -2174,6 +2275,9 @@ config SMP_UP
 
 config SYS_SUPPORTS_MIPS_CMP
 
 config SYS_SUPPORTS_MIPS_CMP
 
 	bool
 
 	bool
 
 
 
+config SYS_SUPPORTS_MIPS_CPS
 
+	bool
 
+
 
 config SYS_SUPPORTS_SMP
 
 config SYS_SUPPORTS_SMP
 
 	bool
 
 	bool
 
 
 
@@ -2406,6 +2510,17 @@ config PCI
 
 	  your box. Other bus systems are ISA, EISA, or VESA. If you have PCI,
 
 	  your box. Other bus systems are ISA, EISA, or VESA. If you have PCI,
 
 	  say Y, otherwise N.
 
 	  say Y, otherwise N.
 
 
 
+config HT_PCI
 
+	bool "Support for HT-linked PCI"
 
+	default y
 
+	depends on CPU_LOONGSON3
 
+	select PCI
 
+	select PCI_DOMAINS
 
+	help
 
+	  Loongson family machines use Hyper-Transport bus for inter-core
 
+	  connection and device connection. The PCI bus is a subordinate
 
+	  linked at HT. Choose Y for Loongson-3 based machines.
 
+
 
 config PCI_DOMAINS
 
 config PCI_DOMAINS
 
 	bool
 
 	bool

+ 7 - 3
arch/mips/Kconfig.debug
Vizualizați fișierul 

@@ -21,13 +21,17 @@ config EARLY_PRINTK
 
 	  unless you want to debug such a crash.
 
 	  unless you want to debug such a crash.
 
 
 
 config EARLY_PRINTK_8250
 
 config EARLY_PRINTK_8250
 
-	bool "8250/16550 and compatible serial early printk driver"
 
-	depends on EARLY_PRINTK
 
-	default n
 
+	bool
 
+	depends on EARLY_PRINTK && USE_GENERIC_EARLY_PRINTK_8250
 
+	default y
 
 	help
 
 	help
 
+	  "8250/16550 and compatible serial early printk driver"
 
 	  If you say Y here, it will be possible to use a 8250/16550 serial
 
 	  If you say Y here, it will be possible to use a 8250/16550 serial
 
 	  port as the boot console.
 
 	  port as the boot console.
 
 
 
+config USE_GENERIC_EARLY_PRINTK_8250
 
+	bool
 
+
 
 config CMDLINE_BOOL
 
 config CMDLINE_BOOL
 
 	bool "Built-in kernel command line"
 
 	bool "Built-in kernel command line"
 
 	default n
 
 	default n

+ 5 - 0
arch/mips/Makefile
Vizualizați fișierul 

@@ -119,6 +119,11 @@ cflags-$(CONFIG_CPU_MICROMIPS) += $(call cc-option,-mmicromips)
 
 cflags-$(CONFIG_SB1XXX_CORELIS)	+= $(call cc-option,-mno-sched-prolog) \
 
 cflags-$(CONFIG_SB1XXX_CORELIS)	+= $(call cc-option,-mno-sched-prolog) \
 
 				   -fno-omit-frame-pointer
 
 				   -fno-omit-frame-pointer
 
 
 
+ifeq ($(CONFIG_CPU_HAS_MSA),y)
 
+toolchain-msa			:= $(call cc-option-yn,-mhard-float -mfp64 -mmsa)
 
+cflags-$(toolchain-msa)		+= -DTOOLCHAIN_SUPPORTS_MSA
 
+endif
 
+
 
 #
 
 #
 
 # CPU-dependent compiler/assembler options for optimization.
 
 # CPU-dependent compiler/assembler options for optimization.
 
 #
 
 #

+ 8 - 16
arch/mips/alchemy/Kconfig
Vizualizați fișierul 

@@ -16,36 +16,29 @@ config ALCHEMY_GPIO_INDIRECT
 
 choice
 
 choice
 
 	prompt "Machine type"
 
 	prompt "Machine type"
 
 	depends on MIPS_ALCHEMY
 
 	depends on MIPS_ALCHEMY
 
-	default MIPS_DB1000
 
+	default MIPS_DB1XXX
 
 
 
 config MIPS_MTX1
 
 config MIPS_MTX1
 
 	bool "4G Systems MTX-1 board"
 
 	bool "4G Systems MTX-1 board"
 
-	select DMA_NONCOHERENT
 
 	select HW_HAS_PCI
 
 	select HW_HAS_PCI
 
 	select ALCHEMY_GPIOINT_AU1000
 
 	select ALCHEMY_GPIOINT_AU1000
 
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 
 	select SYS_HAS_EARLY_PRINTK
 
 	select SYS_HAS_EARLY_PRINTK
 
 
 
-config MIPS_DB1000
 
-	bool "Alchemy DB1000/DB1500/DB1100 PB1500/1100 boards"
 
-	select ALCHEMY_GPIOINT_AU1000
 
-	select DMA_NONCOHERENT
 
-	select HW_HAS_PCI
 
-	select SYS_SUPPORTS_BIG_ENDIAN
 
-	select SYS_SUPPORTS_LITTLE_ENDIAN
 
-	select SYS_HAS_EARLY_PRINTK
 
-
 
-config MIPS_DB1235
 
-	bool "Alchemy DB1200/PB1200/DB1300/DB1550/PB1550 boards"
 
+config MIPS_DB1XXX
 
+	bool "Alchemy DB1XXX / PB1XXX boards"
 
 	select ARCH_REQUIRE_GPIOLIB
 
 	select ARCH_REQUIRE_GPIOLIB
 
 	select HW_HAS_PCI
 
 	select HW_HAS_PCI
 
-	select DMA_COHERENT
 
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 
 	select SYS_HAS_EARLY_PRINTK
 
 	select SYS_HAS_EARLY_PRINTK
 
+	help
 
+	  Select this option if you have one of the following Alchemy
 
+	  development boards:  DB1000 DB1500 DB1100 DB1550 DB1200 DB1300
 
+			       PB1500 PB1100 PB1550 PB1200
 
+	  Board type is autodetected during boot.
 
 
 
 config MIPS_XXS1500
 
 config MIPS_XXS1500
 
 	bool "MyCable XXS1500 board"
 
 	bool "MyCable XXS1500 board"
 
-	select DMA_NONCOHERENT
 
 	select ALCHEMY_GPIOINT_AU1000
 
 	select ALCHEMY_GPIOINT_AU1000
 
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 
 	select SYS_HAS_EARLY_PRINTK
 
 	select SYS_HAS_EARLY_PRINTK
 
@@ -54,7 +47,6 @@ config MIPS_GPR
 
 	bool "Trapeze ITS GPR board"
 
 	bool "Trapeze ITS GPR board"
 
 	select ALCHEMY_GPIOINT_AU1000
 
 	select ALCHEMY_GPIOINT_AU1000
 
 	select HW_HAS_PCI
 
 	select HW_HAS_PCI
 
-	select DMA_NONCOHERENT
 
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 
 	select SYS_HAS_EARLY_PRINTK
 
 	select SYS_HAS_EARLY_PRINTK

+ 5 - 11
arch/mips/alchemy/Platform
Vizualizați fișierul 

@@ -5,18 +5,12 @@ platform-$(CONFIG_MIPS_ALCHEMY) += alchemy/common/
 
 
 
 
 
 #
 
 #
 
-# AMD Alchemy Db1000/Db1500/Pb1500/Db1100/Pb1100 eval boards
 
+# AMD Alchemy Db1000/Db1500/Pb1500/Db1100/Pb1100
 
+#             Db1550/Pb1550/Db1200/Pb1200/Db1300
 
 #
 
 #
 
-platform-$(CONFIG_MIPS_DB1000)	+= alchemy/devboards/
 
-cflags-$(CONFIG_MIPS_DB1000)	+= -I$(srctree)/arch/mips/include/asm/mach-db1x00
 
-load-$(CONFIG_MIPS_DB1000)	+= 0xffffffff80100000
 
-
 
-#
 
-# AMD Alchemy Db1200/Pb1200/Db1550/Pb1550/Db1300 eval boards
 
-#
 
-platform-$(CONFIG_MIPS_DB1235)	+= alchemy/devboards/
 
-cflags-$(CONFIG_MIPS_DB1235)	+= -I$(srctree)/arch/mips/include/asm/mach-db1x00
 
-load-$(CONFIG_MIPS_DB1235)	+= 0xffffffff80100000
 
+platform-$(CONFIG_MIPS_DB1XXX)	+= alchemy/devboards/
 
+cflags-$(CONFIG_MIPS_DB1XXX)	+= -I$(srctree)/arch/mips/include/asm/mach-db1x00
 
+load-$(CONFIG_MIPS_DB1XXX)	+= 0xffffffff80100000
 
 
 
 #
 
 #
 
 # 4G-Systems MTX-1 "MeshCube" wireless router
 
 # 4G-Systems MTX-1 "MeshCube" wireless router

+ 10 - 0
arch/mips/alchemy/common/setup.c
Vizualizați fișierul 

@@ -30,6 +30,7 @@
 
 #include <linux/jiffies.h>
 
 #include <linux/jiffies.h>
 
 #include <linux/module.h>
 
 #include <linux/module.h>
 
 
 
+#include <asm/dma-coherence.h>
 
 #include <asm/mipsregs.h>
 
 #include <asm/mipsregs.h>
 
 #include <asm/time.h>
 
 #include <asm/time.h>
 
 
 
@@ -59,6 +60,15 @@ void __init plat_mem_setup(void)
 
 		/* Clear to obtain best system bus performance */
 
 		/* Clear to obtain best system bus performance */
 
 		clear_c0_config(1 << 19); /* Clear Config[OD] */
 
 		clear_c0_config(1 << 19); /* Clear Config[OD] */
 
 
 
+	hw_coherentio = 0;
 
+	coherentio = 1;
 
+	switch (alchemy_get_cputype()) {
 
+	case ALCHEMY_CPU_AU1000:
 
+	case ALCHEMY_CPU_AU1500:
 
+	case ALCHEMY_CPU_AU1100:
 
+		coherentio = 0;
 
+	}
 
+
 
 	board_setup();	/* board specific setup */
 
 	board_setup();	/* board specific setup */
 
 
 
 	/* IO/MEM resources. */
 
 	/* IO/MEM resources. */

+ 3 - 3
arch/mips/alchemy/common/sleeper.S
Vizualizați fișierul 

@@ -95,7 +95,7 @@ LEAF(alchemy_sleep_au1000)
 
 
 
 	/* cache following instructions, as memory gets put to sleep */
 
 	/* cache following instructions, as memory gets put to sleep */
 
 	la	t0, 1f
 
 	la	t0, 1f
 
-	.set	mips3
 
+	.set	arch=r4000
 
 	cache	0x14, 0(t0)
 
 	cache	0x14, 0(t0)
 
 	cache	0x14, 32(t0)
 
 	cache	0x14, 32(t0)
 
 	cache	0x14, 64(t0)
 
 	cache	0x14, 64(t0)
 
@@ -121,7 +121,7 @@ LEAF(alchemy_sleep_au1550)
 
 
 
 	/* cache following instructions, as memory gets put to sleep */
 
 	/* cache following instructions, as memory gets put to sleep */
 
 	la	t0, 1f
 
 	la	t0, 1f
 
-	.set	mips3
 
+	.set	arch=r4000
 
 	cache	0x14, 0(t0)
 
 	cache	0x14, 0(t0)
 
 	cache	0x14, 32(t0)
 
 	cache	0x14, 32(t0)
 
 	cache	0x14, 64(t0)
 
 	cache	0x14, 64(t0)
 
@@ -163,7 +163,7 @@ LEAF(alchemy_sleep_au1300)
 
 	la	t1, 4f
 
 	la	t1, 4f
 
 	subu	t2, t1, t0
 
 	subu	t2, t1, t0
 
 
 
-	.set	mips3
 
+	.set	arch=r4000
 
 
 
 1:	cache	0x14, 0(t0)
 
 1:	cache	0x14, 0(t0)
 
 	subu	t2, t2, 32
 
 	subu	t2, t2, 32

+ 1 - 3
arch/mips/alchemy/devboards/Makefile
Vizualizați fișierul 

@@ -2,7 +2,5 @@
 
 # Alchemy Develboards
 
 # Alchemy Develboards
 
 #
 
 #
 
 
 
-obj-y += bcsr.o platform.o
 
+obj-y += bcsr.o platform.o db1000.o db1200.o db1300.o db1550.o db1xxx.o
 
 obj-$(CONFIG_PM)		+= pm.o
 
 obj-$(CONFIG_PM)		+= pm.o
 
-obj-$(CONFIG_MIPS_DB1000)	+= db1000.o
 
-obj-$(CONFIG_MIPS_DB1235)	+= db1235.o db1200.o db1300.o db1550.o

+ 12 - 35
arch/mips/alchemy/devboards/db1000.c
Vizualizați fișierul 

@@ -41,42 +41,27 @@
 
 
 
 #define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT)
 
 #define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT)
 
 
 
-struct pci_dev;
 
+const char *get_system_type(void);
 
 
 
-static const char *board_type_str(void)
 
+int __init db1000_board_setup(void)
 
 {
 
 {
 
+	/* initialize board register space */
 
+	bcsr_init(DB1000_BCSR_PHYS_ADDR,
 
+		  DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
 
+
 
 	switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
 
 	switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
 
 	case BCSR_WHOAMI_DB1000:
 
 	case BCSR_WHOAMI_DB1000:
 
-		return "DB1000";
 
 	case BCSR_WHOAMI_DB1500:
 
 	case BCSR_WHOAMI_DB1500:
 
-		return "DB1500";
 
 	case BCSR_WHOAMI_DB1100:
 
 	case BCSR_WHOAMI_DB1100:
 
-		return "DB1100";
 
 	case BCSR_WHOAMI_PB1500:
 
 	case BCSR_WHOAMI_PB1500:
 
 	case BCSR_WHOAMI_PB1500R2:
 
 	case BCSR_WHOAMI_PB1500R2:
 
-		return "PB1500";
 
 	case BCSR_WHOAMI_PB1100:
 
 	case BCSR_WHOAMI_PB1100:
 
-		return "PB1100";
 
-	default:
 
-		return "(unknown)";
 
+		pr_info("AMD Alchemy %s Board\n", get_system_type());
 
+		return 0;
 
 	}
 
 	}
 
+	return -ENODEV;
 
 }
 
 }
 
 
 
-const char *get_system_type(void)
 
-{
 
-	return board_type_str();
 
-}
 
-
 
-void __init board_setup(void)
 
-{
 
-	/* initialize board register space */
 
-	bcsr_init(DB1000_BCSR_PHYS_ADDR,
 
-		  DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
 
-
 
-	printk(KERN_INFO "AMD Alchemy %s Board\n", board_type_str());
 
-}
 
-
 
-
 
 static int db1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
 
 static int db1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
 
 {
 
 {
 
 	if ((slot < 12) || (slot > 13) || pin == 0)
 
 	if ((slot < 12) || (slot > 13) || pin == 0)
 
@@ -114,17 +99,10 @@ static struct platform_device db1500_pci_host_dev = {
 
 	.resource	= alchemy_pci_host_res,
 
 	.resource	= alchemy_pci_host_res,
 
 };
 
 };
 
 
 
-static int __init db1500_pci_init(void)
 
+int __init db1500_pci_setup(void)
 
 {
 
 {
 
-	int id = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
 
-	if ((id == BCSR_WHOAMI_DB1500) || (id == BCSR_WHOAMI_PB1500) ||
 
-	    (id == BCSR_WHOAMI_PB1500R2))
 
-		return platform_device_register(&db1500_pci_host_dev);
 
-	return 0;
 
+	return platform_device_register(&db1500_pci_host_dev);
 
 }
 
 }
 
-/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
 
-arch_initcall(db1500_pci_init);
 
-
 
 
 
 static struct resource au1100_lcd_resources[] = {
 
 static struct resource au1100_lcd_resources[] = {
 
 	[0] = {
 
 	[0] = {
 
@@ -513,7 +491,7 @@ static struct platform_device *db1100_devs[] = {
 
 	&db1000_irda_dev,
 
 	&db1000_irda_dev,
 
 };
 
 };
 
 
 
-static int __init db1000_dev_init(void)
 
+int __init db1000_dev_setup(void)
 
 {
 
 {
 
 	int board = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
 
 	int board = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
 
 	int c0, c1, d0, d1, s0, s1, flashsize = 32,  twosocks = 1;
 
 	int c0, c1, d0, d1, s0, s1, flashsize = 32,  twosocks = 1;
 
@@ -623,4 +601,3 @@ static int __init db1000_dev_init(void)
 
 	db1x_register_norflash(flashsize << 20, 4 /* 32bit */, F_SWAPPED);
 
 	db1x_register_norflash(flashsize << 20, 4 /* 32bit */, F_SWAPPED);
 
 	return 0;
 
 	return 0;
 
 }
 
 }
 
-device_initcall(db1000_dev_init);

+ 70 - 8
arch/mips/alchemy/devboards/db1200.c
Vizualizați fișierul 

@@ -35,16 +35,63 @@
 
 #include <linux/spi/spi.h>
 
 #include <linux/spi/spi.h>
 
 #include <linux/spi/flash.h>
 
 #include <linux/spi/flash.h>
 
 #include <linux/smc91x.h>
 
 #include <linux/smc91x.h>
 
+#include <linux/ata_platform.h>
 
 #include <asm/mach-au1x00/au1000.h>
 
 #include <asm/mach-au1x00/au1000.h>
 
 #include <asm/mach-au1x00/au1100_mmc.h>
 
 #include <asm/mach-au1x00/au1100_mmc.h>
 
 #include <asm/mach-au1x00/au1xxx_dbdma.h>
 
 #include <asm/mach-au1x00/au1xxx_dbdma.h>
 
+#include <asm/mach-au1x00/au1xxx_psc.h>
 
 #include <asm/mach-au1x00/au1200fb.h>
 
 #include <asm/mach-au1x00/au1200fb.h>
 
 #include <asm/mach-au1x00/au1550_spi.h>
 
 #include <asm/mach-au1x00/au1550_spi.h>
 
 #include <asm/mach-db1x00/bcsr.h>
 
 #include <asm/mach-db1x00/bcsr.h>
 
-#include <asm/mach-db1x00/db1200.h>
 
 
 
 #include "platform.h"
 
 #include "platform.h"
 
 
 
+#define BCSR_INT_IDE		0x0001
 
+#define BCSR_INT_ETH		0x0002
 
+#define BCSR_INT_PC0		0x0004
 
+#define BCSR_INT_PC0STSCHG	0x0008
 
+#define BCSR_INT_PC1		0x0010
 
+#define BCSR_INT_PC1STSCHG	0x0020
 
+#define BCSR_INT_DC		0x0040
 
+#define BCSR_INT_FLASHBUSY	0x0080
 
+#define BCSR_INT_PC0INSERT	0x0100
 
+#define BCSR_INT_PC0EJECT	0x0200
 
+#define BCSR_INT_PC1INSERT	0x0400
 
+#define BCSR_INT_PC1EJECT	0x0800
 
+#define BCSR_INT_SD0INSERT	0x1000
 
+#define BCSR_INT_SD0EJECT	0x2000
 
+#define BCSR_INT_SD1INSERT	0x4000
 
+#define BCSR_INT_SD1EJECT	0x8000
 
+
 
+#define DB1200_IDE_PHYS_ADDR	0x18800000
 
+#define DB1200_IDE_REG_SHIFT	5
 
+#define DB1200_IDE_PHYS_LEN	(16 << DB1200_IDE_REG_SHIFT)
 
+#define DB1200_ETH_PHYS_ADDR	0x19000300
 
+#define DB1200_NAND_PHYS_ADDR	0x20000000
 
+
 
+#define PB1200_IDE_PHYS_ADDR	0x0C800000
 
+#define PB1200_ETH_PHYS_ADDR	0x0D000300
 
+#define PB1200_NAND_PHYS_ADDR	0x1C000000
 
+
 
+#define DB1200_INT_BEGIN	(AU1000_MAX_INTR + 1)
 
+#define DB1200_IDE_INT		(DB1200_INT_BEGIN + 0)
 
+#define DB1200_ETH_INT		(DB1200_INT_BEGIN + 1)
 
+#define DB1200_PC0_INT		(DB1200_INT_BEGIN + 2)
 
+#define DB1200_PC0_STSCHG_INT	(DB1200_INT_BEGIN + 3)
 
+#define DB1200_PC1_INT		(DB1200_INT_BEGIN + 4)
 
+#define DB1200_PC1_STSCHG_INT	(DB1200_INT_BEGIN + 5)
 
+#define DB1200_DC_INT		(DB1200_INT_BEGIN + 6)
 
+#define DB1200_FLASHBUSY_INT	(DB1200_INT_BEGIN + 7)
 
+#define DB1200_PC0_INSERT_INT	(DB1200_INT_BEGIN + 8)
 
+#define DB1200_PC0_EJECT_INT	(DB1200_INT_BEGIN + 9)
 
+#define DB1200_PC1_INSERT_INT	(DB1200_INT_BEGIN + 10)
 
+#define DB1200_PC1_EJECT_INT	(DB1200_INT_BEGIN + 11)
 
+#define DB1200_SD0_INSERT_INT	(DB1200_INT_BEGIN + 12)
 
+#define DB1200_SD0_EJECT_INT	(DB1200_INT_BEGIN + 13)
 
+#define PB1200_SD1_INSERT_INT	(DB1200_INT_BEGIN + 14)
 
+#define PB1200_SD1_EJECT_INT	(DB1200_INT_BEGIN + 15)
 
+#define DB1200_INT_END		(DB1200_INT_BEGIN + 15)
 
+
 
 const char *get_system_type(void);
 
 const char *get_system_type(void);
 
 
 
 static int __init db1200_detect_board(void)
 
 static int __init db1200_detect_board(void)
 
@@ -89,6 +136,15 @@ int __init db1200_board_setup(void)
 
 		return -ENODEV;
 
 		return -ENODEV;
 
 
 
 	whoami = bcsr_read(BCSR_WHOAMI);
 
 	whoami = bcsr_read(BCSR_WHOAMI);
 
+	switch (BCSR_WHOAMI_BOARD(whoami)) {
 
+	case BCSR_WHOAMI_PB1200_DDR1:
 
+	case BCSR_WHOAMI_PB1200_DDR2:
 
+	case BCSR_WHOAMI_DB1200:
 
+		break;
 
+	default:
 
+		return -ENODEV;
 
+	}
 
+
 
 	printk(KERN_INFO "Alchemy/AMD/RMI %s Board, CPLD Rev %d"
 
 	printk(KERN_INFO "Alchemy/AMD/RMI %s Board, CPLD Rev %d"
 
 		"  Board-ID %d	Daughtercard ID %d\n", get_system_type(),
 
 		"  Board-ID %d	Daughtercard ID %d\n", get_system_type(),
 
 		(whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
 
 		(whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
 
@@ -275,32 +331,38 @@ static struct platform_device db1200_eth_dev = {
 
 
 
 /**********************************************************************/
 
 /**********************************************************************/
 
 
 
+static struct pata_platform_info db1200_ide_info = {
 
+	.ioport_shift	= DB1200_IDE_REG_SHIFT,
 
+};
 
+
 
+#define IDE_ALT_START	(14 << DB1200_IDE_REG_SHIFT)
 
 static struct resource db1200_ide_res[] = {
 
 static struct resource db1200_ide_res[] = {
 
 	[0] = {
 
 	[0] = {
 
 		.start	= DB1200_IDE_PHYS_ADDR,
 
 		.start	= DB1200_IDE_PHYS_ADDR,
 
-		.end	= DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1,
 
+		.end	= DB1200_IDE_PHYS_ADDR + IDE_ALT_START - 1,
 
 		.flags	= IORESOURCE_MEM,
 
 		.flags	= IORESOURCE_MEM,
 
 	},
 
 	},
 
 	[1] = {
 
 	[1] = {
 
+		.start	= DB1200_IDE_PHYS_ADDR + IDE_ALT_START,
 
+		.end	= DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1,
 
+		.flags	= IORESOURCE_MEM,
 
+	},
 
+	[2] = {
 
 		.start	= DB1200_IDE_INT,
 
 		.start	= DB1200_IDE_INT,
 
 		.end	= DB1200_IDE_INT,
 
 		.end	= DB1200_IDE_INT,
 
 		.flags	= IORESOURCE_IRQ,
 
 		.flags	= IORESOURCE_IRQ,
 
 	},
 
 	},
 
-	[2] = {
 
-		.start	= AU1200_DSCR_CMD0_DMA_REQ1,
 
-		.end	= AU1200_DSCR_CMD0_DMA_REQ1,
 
-		.flags	= IORESOURCE_DMA,
 
-	},
 
 };
 
 };
 
 
 
 static u64 au1200_ide_dmamask = DMA_BIT_MASK(32);
 
 static u64 au1200_ide_dmamask = DMA_BIT_MASK(32);
 
 
 
 static struct platform_device db1200_ide_dev = {
 
 static struct platform_device db1200_ide_dev = {
 
-	.name		= "au1200-ide",
 
+	.name		= "pata_platform",
 
 	.id		= 0,
 
 	.id		= 0,
 
 	.dev = {
 
 	.dev = {
 
 		.dma_mask		= &au1200_ide_dmamask,
 
 		.dma_mask		= &au1200_ide_dmamask,
 
 		.coherent_dma_mask	= DMA_BIT_MASK(32),
 
 		.coherent_dma_mask	= DMA_BIT_MASK(32),
 
+		.platform_data		= &db1200_ide_info,
 
 	},
 
 	},
 
 	.num_resources	= ARRAY_SIZE(db1200_ide_res),
 
 	.num_resources	= ARRAY_SIZE(db1200_ide_res),
 
 	.resource	= db1200_ide_res,
 
 	.resource	= db1200_ide_res,

+ 38 - 2
arch/mips/alchemy/devboards/db1300.c
Vizualizați fișierul 

@@ -26,12 +26,44 @@
 
 #include <asm/mach-au1x00/au1200fb.h>
 
 #include <asm/mach-au1x00/au1200fb.h>
 
 #include <asm/mach-au1x00/au1xxx_dbdma.h>
 
 #include <asm/mach-au1x00/au1xxx_dbdma.h>
 
 #include <asm/mach-au1x00/au1xxx_psc.h>
 
 #include <asm/mach-au1x00/au1xxx_psc.h>
 
-#include <asm/mach-db1x00/db1300.h>
 
 #include <asm/mach-db1x00/bcsr.h>
 
 #include <asm/mach-db1x00/bcsr.h>
 
 #include <asm/mach-au1x00/prom.h>
 
 #include <asm/mach-au1x00/prom.h>
 
 
 
 #include "platform.h"
 
 #include "platform.h"
 
 
 
+/* FPGA (external mux) interrupt sources */
 
+#define DB1300_FIRST_INT	(ALCHEMY_GPIC_INT_LAST + 1)
 
+#define DB1300_IDE_INT		(DB1300_FIRST_INT + 0)
 
+#define DB1300_ETH_INT		(DB1300_FIRST_INT + 1)
 
+#define DB1300_CF_INT		(DB1300_FIRST_INT + 2)
 
+#define DB1300_VIDEO_INT	(DB1300_FIRST_INT + 4)
 
+#define DB1300_HDMI_INT		(DB1300_FIRST_INT + 5)
 
+#define DB1300_DC_INT		(DB1300_FIRST_INT + 6)
 
+#define DB1300_FLASH_INT	(DB1300_FIRST_INT + 7)
 
+#define DB1300_CF_INSERT_INT	(DB1300_FIRST_INT + 8)
 
+#define DB1300_CF_EJECT_INT	(DB1300_FIRST_INT + 9)
 
+#define DB1300_AC97_INT		(DB1300_FIRST_INT + 10)
 
+#define DB1300_AC97_PEN_INT	(DB1300_FIRST_INT + 11)
 
+#define DB1300_SD1_INSERT_INT	(DB1300_FIRST_INT + 12)
 
+#define DB1300_SD1_EJECT_INT	(DB1300_FIRST_INT + 13)
 
+#define DB1300_OTG_VBUS_OC_INT	(DB1300_FIRST_INT + 14)
 
+#define DB1300_HOST_VBUS_OC_INT (DB1300_FIRST_INT + 15)
 
+#define DB1300_LAST_INT		(DB1300_FIRST_INT + 15)
 
+
 
+/* SMSC9210 CS */
 
+#define DB1300_ETH_PHYS_ADDR	0x19000000
 
+#define DB1300_ETH_PHYS_END	0x197fffff
 
+
 
+/* ATA CS */
 
+#define DB1300_IDE_PHYS_ADDR	0x18800000
 
+#define DB1300_IDE_REG_SHIFT	5
 
+#define DB1300_IDE_PHYS_LEN	(16 << DB1300_IDE_REG_SHIFT)
 
+
 
+/* NAND CS */
 
+#define DB1300_NAND_PHYS_ADDR	0x20000000
 
+#define DB1300_NAND_PHYS_END	0x20000fff
 
+
 
+
 
 static struct i2c_board_info db1300_i2c_devs[] __initdata = {
 
 static struct i2c_board_info db1300_i2c_devs[] __initdata = {
 
 	{ I2C_BOARD_INFO("wm8731", 0x1b), },	/* I2S audio codec */
 
 	{ I2C_BOARD_INFO("wm8731", 0x1b), },	/* I2S audio codec */
 
 	{ I2C_BOARD_INFO("ne1619", 0x2d), },	/* adm1025-compat hwmon */
 
 	{ I2C_BOARD_INFO("ne1619", 0x2d), },	/* adm1025-compat hwmon */
 
@@ -759,11 +791,15 @@ int __init db1300_board_setup(void)
 
 {
 
 {
 
 	unsigned short whoami;
 
 	unsigned short whoami;
 
 
 
-	db1300_gpio_config();
 
 	bcsr_init(DB1300_BCSR_PHYS_ADDR,
 
 	bcsr_init(DB1300_BCSR_PHYS_ADDR,
 
 		  DB1300_BCSR_PHYS_ADDR + DB1300_BCSR_HEXLED_OFS);
 
 		  DB1300_BCSR_PHYS_ADDR + DB1300_BCSR_HEXLED_OFS);
 
 
 
 	whoami = bcsr_read(BCSR_WHOAMI);
 
 	whoami = bcsr_read(BCSR_WHOAMI);
 
+	if (BCSR_WHOAMI_BOARD(whoami) != BCSR_WHOAMI_DB1300)
 
+		return -ENODEV;
 
+
 
+	db1300_gpio_config();
 
+
 
 	printk(KERN_INFO "NetLogic DBAu1300 Development Platform.\n\t"
 
 	printk(KERN_INFO "NetLogic DBAu1300 Development Platform.\n\t"
 
 		"BoardID %d   CPLD Rev %d   DaughtercardID %d\n",
 
 		"BoardID %d   CPLD Rev %d   DaughtercardID %d\n",
 
 		BCSR_WHOAMI_BOARD(whoami), BCSR_WHOAMI_CPLD(whoami),
 
 		BCSR_WHOAMI_BOARD(whoami), BCSR_WHOAMI_CPLD(whoami),

+ 8 - 2
arch/mips/alchemy/devboards/db1550.c
Vizualizați fișierul 

@@ -62,10 +62,16 @@ int __init db1550_board_setup(void)
 
 		  DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS);
 
 		  DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS);
 
 
 
 	whoami = bcsr_read(BCSR_WHOAMI); /* PB1550 hexled offset differs */
 
 	whoami = bcsr_read(BCSR_WHOAMI); /* PB1550 hexled offset differs */
 
-	if ((BCSR_WHOAMI_BOARD(whoami) == BCSR_WHOAMI_PB1550_SDR) ||
 
-	    (BCSR_WHOAMI_BOARD(whoami) == BCSR_WHOAMI_PB1550_DDR))
 
+	switch (BCSR_WHOAMI_BOARD(whoami)) {
 
+	case BCSR_WHOAMI_PB1550_SDR:
 
+	case BCSR_WHOAMI_PB1550_DDR:
 
 		bcsr_init(PB1550_BCSR_PHYS_ADDR,
 
 		bcsr_init(PB1550_BCSR_PHYS_ADDR,
 
 			  PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS);
 
 			  PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS);
 
+	case BCSR_WHOAMI_DB1550:
 
+		break;
 
+	default:
 
+		return -ENODEV;
 
+	}
 
 
 
 	pr_info("Alchemy/AMD %s Board, CPLD Rev %d Board-ID %d	"	\
 
 	pr_info("Alchemy/AMD %s Board, CPLD Rev %d Board-ID %d	"	\
 
 		"Daughtercard ID %d\n", get_system_type(),
 
 		"Daughtercard ID %d\n", get_system_type(),

+ 34 - 7
arch/mips/alchemy/devboards/db1235.c → arch/mips/alchemy/devboards/db1xxx.c
Vizualizați fișierul 

@@ -1,12 +1,13 @@
 
 /*
 
 /*
 
- * DB1200/PB1200 / DB1550 / DB1300 board support.
 
- *
 
- * These 4 boards can reliably be supported in a single kernel image.
 
+ * Alchemy DB/PB1xxx board support.
 
  */
 
  */
 
 
 
 #include <asm/mach-au1x00/au1000.h>
 
 #include <asm/mach-au1x00/au1000.h>
 
 #include <asm/mach-db1x00/bcsr.h>
 
 #include <asm/mach-db1x00/bcsr.h>
 
 
 
+int __init db1000_board_setup(void);
 
+int __init db1000_dev_setup(void);
 
+int __init db1500_pci_setup(void);
 
 int __init db1200_board_setup(void);
 
 int __init db1200_board_setup(void);
 
 int __init db1200_dev_setup(void);
 
 int __init db1200_dev_setup(void);
 
 int __init db1300_board_setup(void);
 
 int __init db1300_board_setup(void);
 
@@ -18,6 +19,17 @@ int __init db1550_pci_setup(int);
 
 static const char *board_type_str(void)
 
 static const char *board_type_str(void)
 
 {
 
 {
 
 	switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
 
 	switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
 
+	case BCSR_WHOAMI_DB1000:
 
+		return "DB1000";
 
+	case BCSR_WHOAMI_DB1500:
 
+		return "DB1500";
 
+	case BCSR_WHOAMI_DB1100:
 
+		return "DB1100";
 
+	case BCSR_WHOAMI_PB1500:
 
+	case BCSR_WHOAMI_PB1500R2:
 
+		return "PB1500";
 
+	case BCSR_WHOAMI_PB1100:
 
+		return "PB1100";
 
 	case BCSR_WHOAMI_PB1200_DDR1:
 
 	case BCSR_WHOAMI_PB1200_DDR1:
 
 	case BCSR_WHOAMI_PB1200_DDR2:
 
 	case BCSR_WHOAMI_PB1200_DDR2:
 
 		return "PB1200";
 
 		return "PB1200";
 
@@ -45,6 +57,11 @@ void __init board_setup(void)
 
 	int ret;
 
 	int ret;
 
 
 
 	switch (alchemy_get_cputype()) {
 
 	switch (alchemy_get_cputype()) {
 
+	case ALCHEMY_CPU_AU1000:
 
+	case ALCHEMY_CPU_AU1500:
 
+	case ALCHEMY_CPU_AU1100:
 
+		ret = db1000_board_setup();
 
+		break;
 
 	case ALCHEMY_CPU_AU1550:
 
 	case ALCHEMY_CPU_AU1550:
 
 		ret = db1550_board_setup();
 
 		ret = db1550_board_setup();
 
 		break;
 
 		break;
 
@@ -62,7 +79,7 @@ void __init board_setup(void)
 
 		panic("cannot initialize board support");
 
 		panic("cannot initialize board support");
 
 }
 
 }
 
 
 
-int __init db1235_arch_init(void)
 
+static int __init db1xxx_arch_init(void)
 
 {
 
 {
 
 	int id = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
 
 	int id = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
 
 	if (id == BCSR_WHOAMI_DB1550)
 
 	if (id == BCSR_WHOAMI_DB1550)
 
@@ -70,14 +87,24 @@ int __init db1235_arch_init(void)
 
 	else if ((id == BCSR_WHOAMI_PB1550_SDR) ||
 
 	else if ((id == BCSR_WHOAMI_PB1550_SDR) ||
 
 		 (id == BCSR_WHOAMI_PB1550_DDR))
 
 		 (id == BCSR_WHOAMI_PB1550_DDR))
 
 		return db1550_pci_setup(1);
 
 		return db1550_pci_setup(1);
 
+	else if ((id == BCSR_WHOAMI_DB1500) || (id == BCSR_WHOAMI_PB1500) ||
 
+		 (id == BCSR_WHOAMI_PB1500R2))
 
+		return db1500_pci_setup();
 
 
 
 	return 0;
 
 	return 0;
 
 }
 
 }
 
-arch_initcall(db1235_arch_init);
 
+arch_initcall(db1xxx_arch_init);
 
 
 
-int __init db1235_dev_init(void)
 
+static int __init db1xxx_dev_init(void)
 
 {
 
 {
 
 	switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
 
 	switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
 
+	case BCSR_WHOAMI_DB1000:
 
+	case BCSR_WHOAMI_DB1500:
 
+	case BCSR_WHOAMI_DB1100:
 
+	case BCSR_WHOAMI_PB1500:
 
+	case BCSR_WHOAMI_PB1500R2:
 
+	case BCSR_WHOAMI_PB1100:
 
+		return db1000_dev_setup();
 
 	case BCSR_WHOAMI_PB1200_DDR1:
 
 	case BCSR_WHOAMI_PB1200_DDR1:
 
 	case BCSR_WHOAMI_PB1200_DDR2:
 
 	case BCSR_WHOAMI_PB1200_DDR2:
 
 	case BCSR_WHOAMI_DB1200:
 
 	case BCSR_WHOAMI_DB1200:
 
@@ -91,4 +118,4 @@ int __init db1235_dev_init(void)
 
 	}
 
 	}
 
 	return 0;
 
 	return 0;
 
 }
 
 }
 
-device_initcall(db1235_dev_init);
 
+device_initcall(db1xxx_dev_init);

+ 1 - 0
arch/mips/ar7/time.c
Vizualizați fișierul 

@@ -18,6 +18,7 @@
 
  * Setting up the clock on the MIPS boards.
 
  * Setting up the clock on the MIPS boards.
 
  */
 
  */
 
 
 
+#include <linux/init.h>
 
 #include <linux/time.h>
 
 #include <linux/time.h>
 
 #include <linux/err.h>
 
 #include <linux/err.h>
 
 #include <linux/clk.h>
 
 #include <linux/clk.h>

+ 1 - 1
arch/mips/bcm47xx/Makefile
Vizualizați fișierul 

@@ -4,4 +4,4 @@
 
 #
 
 #
 
 
 
 obj-y				+= irq.o nvram.o prom.o serial.o setup.o time.o sprom.o
 
 obj-y				+= irq.o nvram.o prom.o serial.o setup.o time.o sprom.o
 
-obj-y				+= board.o buttons.o leds.o
 
+obj-y				+= board.o buttons.o leds.o workarounds.o

+ 3 - 0
arch/mips/bcm47xx/bcm47xx_private.h
Vizualizați fișierul 

@@ -9,4 +9,7 @@ int __init bcm47xx_buttons_register(void);
 
 /* leds.c */
 
 /* leds.c */
 
 void __init bcm47xx_leds_register(void);
 
 void __init bcm47xx_leds_register(void);
 
 
 
+/* workarounds.c */
 
+void __init bcm47xx_workarounds(void);
 
+
 
 #endif
 
 #endif

+ 24 - 1
arch/mips/bcm47xx/board.c
Vizualizați fișierul 

@@ -72,7 +72,11 @@ struct bcm47xx_board_type_list1 bcm47xx_board_list_hardware_version[] __initcons
 
 	{{BCM47XX_BOARD_ASUS_WL500W, "Asus WL500W"}, "WL500gW-"},
 
 	{{BCM47XX_BOARD_ASUS_WL500W, "Asus WL500W"}, "WL500gW-"},
 
 	{{BCM47XX_BOARD_ASUS_WL520GC, "Asus WL520GC"}, "WL520GC-"},
 
 	{{BCM47XX_BOARD_ASUS_WL520GC, "Asus WL520GC"}, "WL520GC-"},
 
 	{{BCM47XX_BOARD_ASUS_WL520GU, "Asus WL520GU"}, "WL520GU-"},
 
 	{{BCM47XX_BOARD_ASUS_WL520GU, "Asus WL520GU"}, "WL520GU-"},
 
+	{{BCM47XX_BOARD_BELKIN_F7D3301, "Belkin F7D3301"}, "F7D3301"},
 
+	{{BCM47XX_BOARD_BELKIN_F7D3302, "Belkin F7D3302"}, "F7D3302"},
 
 	{{BCM47XX_BOARD_BELKIN_F7D4301, "Belkin F7D4301"}, "F7D4301"},
 
 	{{BCM47XX_BOARD_BELKIN_F7D4301, "Belkin F7D4301"}, "F7D4301"},
 
+	{{BCM47XX_BOARD_BELKIN_F7D4302, "Belkin F7D4302"}, "F7D4302"},
 
+	{{BCM47XX_BOARD_BELKIN_F7D4401, "Belkin F7D4401"}, "F7D4401"},
 
 	{ {0}, NULL},
 
 	{ {0}, NULL},
 
 };
 
 };
 
 
 
@@ -176,7 +180,16 @@ struct bcm47xx_board_type_list3 bcm47xx_board_list_board[] __initconst = {
 
 	{{BCM47XX_BOARD_PHICOMM_M1, "Phicomm M1"}, "0x0590", "80", "0x1104"},
 
 	{{BCM47XX_BOARD_PHICOMM_M1, "Phicomm M1"}, "0x0590", "80", "0x1104"},
 
 	{{BCM47XX_BOARD_ZTE_H218N, "ZTE H218N"}, "0x053d", "1234", "0x1305"},
 
 	{{BCM47XX_BOARD_ZTE_H218N, "ZTE H218N"}, "0x053d", "1234", "0x1305"},
 
 	{{BCM47XX_BOARD_NETGEAR_WNR3500L, "Netgear WNR3500L"}, "0x04CF", "3500", "02"},
 
 	{{BCM47XX_BOARD_NETGEAR_WNR3500L, "Netgear WNR3500L"}, "0x04CF", "3500", "02"},
 
-	{{BCM47XX_BOARD_LINKSYS_WRT54GSV1, "Linksys WRT54GS V1"}, "0x0101", "42", "0x10"},
 
+	{{BCM47XX_BOARD_LINKSYS_WRT54G, "Linksys WRT54G/GS/GL"}, "0x0101", "42", "0x10"},
 
+	{{BCM47XX_BOARD_LINKSYS_WRT54G, "Linksys WRT54G/GS/GL"}, "0x0467", "42", "0x10"},
 
+	{{BCM47XX_BOARD_LINKSYS_WRT54G, "Linksys WRT54G/GS/GL"}, "0x0708", "42", "0x10"},
 
+	{ {0}, NULL},
 
+};
 
+
 
+/* boardtype, boardrev */
 
+static const
 
+struct bcm47xx_board_type_list2 bcm47xx_board_list_board_type_rev[] __initconst = {
 
+	{{BCM47XX_BOARD_SIEMENS_SE505V2, "Siemens SE505 V2"}, "0x0101", "0x10"},
 
 	{ {0}, NULL},
 
 	{ {0}, NULL},
 
 };
 
 };
 
 
 
@@ -273,6 +286,16 @@ static __init const struct bcm47xx_board_type *bcm47xx_board_get_nvram(void)
 
 				return &e3->board;
 
 				return &e3->board;
 
 		}
 
 		}
 
 	}
 
 	}
 
+
 
+	if (bcm47xx_nvram_getenv("boardtype", buf1, sizeof(buf1)) >= 0 &&
 
+	    bcm47xx_nvram_getenv("boardrev", buf2, sizeof(buf2)) >= 0 &&
 
+	    bcm47xx_nvram_getenv("boardnum", buf3, sizeof(buf3)) ==  -ENOENT) {
 
+		for (e2 = bcm47xx_board_list_board_type_rev; e2->value1; e2++) {
 
+			if (!strcmp(buf1, e2->value1) &&
 
+			    !strcmp(buf2, e2->value2))
 
+				return &e2->board;
 
+		}
 
+	}
 
 	return bcm47xx_board_unknown;
 
 	return bcm47xx_board_unknown;
 
 }
 
 }

+ 31 - 0
arch/mips/bcm47xx/buttons.c
Vizualizați fișierul 

@@ -258,6 +258,18 @@ bcm47xx_buttons_linksys_wrt310nv1[] __initconst = {
 
 	BCM47XX_GPIO_KEY(8, KEY_UNKNOWN),
 
 	BCM47XX_GPIO_KEY(8, KEY_UNKNOWN),
 
 };
 
 };
 
 
 
+static const struct gpio_keys_button
 
+bcm47xx_buttons_linksys_wrt54g3gv2[] __initconst = {
 
+	BCM47XX_GPIO_KEY(5, KEY_WIMAX),
 
+	BCM47XX_GPIO_KEY(6, KEY_RESTART),
 
+};
 
+
 
+static const struct gpio_keys_button
 
+bcm47xx_buttons_linksys_wrt54gsv1[] __initconst = {
 
+	BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON),
 
+	BCM47XX_GPIO_KEY(6, KEY_RESTART),
 
+};
 
+
 
 static const struct gpio_keys_button
 
 static const struct gpio_keys_button
 
 bcm47xx_buttons_linksys_wrt610nv1[] __initconst = {
 
 bcm47xx_buttons_linksys_wrt610nv1[] __initconst = {
 
 	BCM47XX_GPIO_KEY(6, KEY_RESTART),
 
 	BCM47XX_GPIO_KEY(6, KEY_RESTART),
 
@@ -270,6 +282,12 @@ bcm47xx_buttons_linksys_wrt610nv2[] __initconst = {
 
 	BCM47XX_GPIO_KEY(6, KEY_RESTART),
 
 	BCM47XX_GPIO_KEY(6, KEY_RESTART),
 
 };
 
 };
 
 
 
+static const struct gpio_keys_button
 
+bcm47xx_buttons_linksys_wrtsl54gs[] __initconst = {
 
+	BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON),
 
+	BCM47XX_GPIO_KEY(6, KEY_RESTART),
 
+};
 
+
 
 /* Motorola */
 
 /* Motorola */
 
 
 
 static const struct gpio_keys_button
 
 static const struct gpio_keys_button
 
@@ -402,7 +420,11 @@ int __init bcm47xx_buttons_register(void)
 
 		err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wlhdd);
 
 		err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wlhdd);
 
 		break;
 
 		break;
 
 
 
+	case BCM47XX_BOARD_BELKIN_F7D3301:
 
+	case BCM47XX_BOARD_BELKIN_F7D3302:
 
 	case BCM47XX_BOARD_BELKIN_F7D4301:
 
 	case BCM47XX_BOARD_BELKIN_F7D4301:
 
+	case BCM47XX_BOARD_BELKIN_F7D4302:
 
+	case BCM47XX_BOARD_BELKIN_F7D4401:
 
 		err = bcm47xx_copy_bdata(bcm47xx_buttons_belkin_f7d4301);
 
 		err = bcm47xx_copy_bdata(bcm47xx_buttons_belkin_f7d4301);
 
 		break;
 
 		break;
 
 
 
@@ -479,12 +501,21 @@ int __init bcm47xx_buttons_register(void)
 
 	case BCM47XX_BOARD_LINKSYS_WRT310NV1:
 
 	case BCM47XX_BOARD_LINKSYS_WRT310NV1:
 
 		err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt310nv1);
 
 		err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt310nv1);
 
 		break;
 
 		break;
 
+	case BCM47XX_BOARD_LINKSYS_WRT54G:
 
+		err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt54gsv1);
 
+		break;
 
+	case BCM47XX_BOARD_LINKSYS_WRT54G3GV2:
 
+		err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt54g3gv2);
 
+		break;
 
 	case BCM47XX_BOARD_LINKSYS_WRT610NV1:
 
 	case BCM47XX_BOARD_LINKSYS_WRT610NV1:
 
 		err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt610nv1);
 
 		err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt610nv1);
 
 		break;
 
 		break;
 
 	case BCM47XX_BOARD_LINKSYS_WRT610NV2:
 
 	case BCM47XX_BOARD_LINKSYS_WRT610NV2:
 
 		err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt610nv2);
 
 		err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt610nv2);
 
 		break;
 
 		break;
 
+	case BCM47XX_BOARD_LINKSYS_WRTSL54GS:
 
+		err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrtsl54gs);
 
+		break;
 
 
 
 	case BCM47XX_BOARD_MOTOROLA_WE800G:
 
 	case BCM47XX_BOARD_MOTOROLA_WE800G:
 
 		err = bcm47xx_copy_bdata(bcm47xx_buttons_motorola_we800g);
 
 		err = bcm47xx_copy_bdata(bcm47xx_buttons_motorola_we800g);

+ 49 - 0
arch/mips/bcm47xx/leds.c
Vizualizați fișierul 

@@ -291,6 +291,21 @@ bcm47xx_leds_linksys_wrt310nv1[] __initconst = {
 
 	BCM47XX_GPIO_LED(9, "blue", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
 
 	BCM47XX_GPIO_LED(9, "blue", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
 
 };
 
 };
 
 
 
+static const struct gpio_led
 
+bcm47xx_leds_linksys_wrt54gsv1[] __initconst = {
 
+	BCM47XX_GPIO_LED(0, "unk", "dmz", 1, LEDS_GPIO_DEFSTATE_OFF),
 
+	BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON),
 
+	BCM47XX_GPIO_LED(5, "white", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
 
+	BCM47XX_GPIO_LED(7, "orange", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
 
+};
 
+
 
+static const struct gpio_led
 
+bcm47xx_leds_linksys_wrt54g3gv2[] __initconst = {
 
+	BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON),
 
+	BCM47XX_GPIO_LED(2, "green", "3g", 0, LEDS_GPIO_DEFSTATE_OFF),
 
+	BCM47XX_GPIO_LED(3, "blue", "3g", 0, LEDS_GPIO_DEFSTATE_OFF),
 
+};
 
+
 
 static const struct gpio_led
 
 static const struct gpio_led
 
 bcm47xx_leds_linksys_wrt610nv1[] __initconst = {
 
 bcm47xx_leds_linksys_wrt610nv1[] __initconst = {
 
 	BCM47XX_GPIO_LED(0, "unk", "usb",  1, LEDS_GPIO_DEFSTATE_OFF),
 
 	BCM47XX_GPIO_LED(0, "unk", "usb",  1, LEDS_GPIO_DEFSTATE_OFF),
 
@@ -308,6 +323,15 @@ bcm47xx_leds_linksys_wrt610nv2[] __initconst = {
 
 	BCM47XX_GPIO_LED(7, "unk", "usb", 0, LEDS_GPIO_DEFSTATE_OFF),
 
 	BCM47XX_GPIO_LED(7, "unk", "usb", 0, LEDS_GPIO_DEFSTATE_OFF),
 
 };
 
 };
 
 
 
+static const struct gpio_led
 
+bcm47xx_leds_linksys_wrtsl54gs[] __initconst = {
 
+	BCM47XX_GPIO_LED(0, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
 
+	BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON),
 
+	BCM47XX_GPIO_LED(2, "white", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
 
+	BCM47XX_GPIO_LED(3, "orange", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
 
+	BCM47XX_GPIO_LED(7, "unk", "dmz", 1, LEDS_GPIO_DEFSTATE_OFF),
 
+};
 
+
 
 /* Motorola */
 
 /* Motorola */
 
 
 
 static const struct gpio_led
 
 static const struct gpio_led
 
@@ -359,6 +383,14 @@ bcm47xx_leds_netgear_wnr834bv2[] __initconst = {
 
 	BCM47XX_GPIO_LED(7, "unk", "connected", 0, LEDS_GPIO_DEFSTATE_OFF),
 
 	BCM47XX_GPIO_LED(7, "unk", "connected", 0, LEDS_GPIO_DEFSTATE_OFF),
 
 };
 
 };
 
 
 
+/* Siemens */
 
+static const struct gpio_led
 
+bcm47xx_leds_siemens_se505v2[] __initconst = {
 
+	BCM47XX_GPIO_LED(0, "unk", "dmz", 1, LEDS_GPIO_DEFSTATE_OFF),
 
+	BCM47XX_GPIO_LED(3, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
 
+	BCM47XX_GPIO_LED(5, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
 
+};
 
+
 
 /* SimpleTech */
 
 /* SimpleTech */
 
 
 
 static const struct gpio_led
 
 static const struct gpio_led
 
@@ -425,7 +457,11 @@ void __init bcm47xx_leds_register(void)
 
 		bcm47xx_set_pdata(bcm47xx_leds_asus_wlhdd);
 
 		bcm47xx_set_pdata(bcm47xx_leds_asus_wlhdd);
 
 		break;
 
 		break;
 
 
 
+	case BCM47XX_BOARD_BELKIN_F7D3301:
 
+	case BCM47XX_BOARD_BELKIN_F7D3302:
 
 	case BCM47XX_BOARD_BELKIN_F7D4301:
 
 	case BCM47XX_BOARD_BELKIN_F7D4301:
 
+	case BCM47XX_BOARD_BELKIN_F7D4302:
 
+	case BCM47XX_BOARD_BELKIN_F7D4401:
 
 		bcm47xx_set_pdata(bcm47xx_leds_belkin_f7d4301);
 
 		bcm47xx_set_pdata(bcm47xx_leds_belkin_f7d4301);
 
 		break;
 
 		break;
 
 
 
@@ -502,12 +538,21 @@ void __init bcm47xx_leds_register(void)
 
 	case BCM47XX_BOARD_LINKSYS_WRT310NV1:
 
 	case BCM47XX_BOARD_LINKSYS_WRT310NV1:
 
 		bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt310nv1);
 
 		bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt310nv1);
 
 		break;
 
 		break;
 
+	case BCM47XX_BOARD_LINKSYS_WRT54G:
 
+		bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt54gsv1);
 
+		break;
 
+	case BCM47XX_BOARD_LINKSYS_WRT54G3GV2:
 
+		bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt54g3gv2);
 
+		break;
 
 	case BCM47XX_BOARD_LINKSYS_WRT610NV1:
 
 	case BCM47XX_BOARD_LINKSYS_WRT610NV1:
 
 		bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt610nv1);
 
 		bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt610nv1);
 
 		break;
 
 		break;
 
 	case BCM47XX_BOARD_LINKSYS_WRT610NV2:
 
 	case BCM47XX_BOARD_LINKSYS_WRT610NV2:
 
 		bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt610nv2);
 
 		bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt610nv2);
 
 		break;
 
 		break;
 
+	case BCM47XX_BOARD_LINKSYS_WRTSL54GS:
 
+		bcm47xx_set_pdata(bcm47xx_leds_linksys_wrtsl54gs);
 
+		break;
 
 
 
 	case BCM47XX_BOARD_MOTOROLA_WE800G:
 
 	case BCM47XX_BOARD_MOTOROLA_WE800G:
 
 		bcm47xx_set_pdata(bcm47xx_leds_motorola_we800g);
 
 		bcm47xx_set_pdata(bcm47xx_leds_motorola_we800g);
 
@@ -529,6 +574,10 @@ void __init bcm47xx_leds_register(void)
 
 		bcm47xx_set_pdata(bcm47xx_leds_netgear_wnr834bv2);
 
 		bcm47xx_set_pdata(bcm47xx_leds_netgear_wnr834bv2);
 
 		break;
 
 		break;
 
 
 
+	case BCM47XX_BOARD_SIEMENS_SE505V2:
 
+		bcm47xx_set_pdata(bcm47xx_leds_siemens_se505v2);
 
+		break;
 
+
 
 	case BCM47XX_BOARD_SIMPLETECH_SIMPLESHARE:
 
 	case BCM47XX_BOARD_SIMPLETECH_SIMPLESHARE:
 
 		bcm47xx_set_pdata(bcm47xx_leds_simpletech_simpleshare);
 
 		bcm47xx_set_pdata(bcm47xx_leds_simpletech_simpleshare);
 
 		break;
 
 		break;

+ 2 - 1
arch/mips/bcm47xx/setup.c
Vizualizați fișierul 

@@ -212,7 +212,7 @@ void __init plat_mem_setup(void)
 
 {
 
 {
 
 	struct cpuinfo_mips *c = &current_cpu_data;
 
 	struct cpuinfo_mips *c = &current_cpu_data;
 
 
 
-	if (c->cputype == CPU_74K) {
 
+	if ((c->cputype == CPU_74K) || (c->cputype == CPU_1074K)) {
 
 		printk(KERN_INFO "bcm47xx: using bcma bus\n");
 
 		printk(KERN_INFO "bcm47xx: using bcma bus\n");
 
 #ifdef CONFIG_BCM47XX_BCMA
 
 #ifdef CONFIG_BCM47XX_BCMA
 
 		bcm47xx_bus_type = BCM47XX_BUS_TYPE_BCMA;
 
 		bcm47xx_bus_type = BCM47XX_BUS_TYPE_BCMA;
 
@@ -282,6 +282,7 @@ static int __init bcm47xx_register_bus_complete(void)
 
 	}
 
 	}
 
 	bcm47xx_buttons_register();
 
 	bcm47xx_buttons_register();
 
 	bcm47xx_leds_register();
 
 	bcm47xx_leds_register();
 
+	bcm47xx_workarounds();
 
 
 
 	fixed_phy_add(PHY_POLL, 0, &bcm47xx_fixed_phy_status);
 
 	fixed_phy_add(PHY_POLL, 0, &bcm47xx_fixed_phy_status);
 
 	return 0;
 
 	return 0;

+ 31 - 0
arch/mips/bcm47xx/workarounds.c
Vizualizați fișierul 

@@ -0,0 +1,31 @@
 
+#include "bcm47xx_private.h"
 
+
 
+#include <linux/gpio.h>
 
+#include <bcm47xx_board.h>
 
+#include <bcm47xx.h>
 
+
 
+static void __init bcm47xx_workarounds_netgear_wnr3500l(void)
 
+{
 
+	const int usb_power = 12;
 
+	int err;
 
+
 
+	err = gpio_request_one(usb_power, GPIOF_OUT_INIT_HIGH, "usb_power");
 
+	if (err)
 
+		pr_err("Failed to request USB power gpio: %d\n", err);
 
+	else
 
+		gpio_free(usb_power);
 
+}
 
+
 
+void __init bcm47xx_workarounds(void)
 
+{
 
+	enum bcm47xx_board board = bcm47xx_board_get();
 
+
 
+	switch (board) {
 
+	case BCM47XX_BOARD_NETGEAR_WNR3500L:
 
+		bcm47xx_workarounds_netgear_wnr3500l();
 
+		break;
 
+	default:
 
+		/* No workaround(s) needed */
 
+		break;
 
+	}
 
+}

+ 1 - 2
arch/mips/bcm63xx/cpu.c
Vizualizați fișierul 

@@ -299,14 +299,13 @@ static unsigned int detect_memory_size(void)
 
 void __init bcm63xx_cpu_init(void)
 
 void __init bcm63xx_cpu_init(void)
 
 {
 
 {
 
 	unsigned int tmp;
 
 	unsigned int tmp;
 
-	struct cpuinfo_mips *c = &current_cpu_data;
 
 	unsigned int cpu = smp_processor_id();
 
 	unsigned int cpu = smp_processor_id();
 
 	u32 chipid_reg;
 
 	u32 chipid_reg;
 
 
 
 	/* soc registers location depends on cpu type */
 
 	/* soc registers location depends on cpu type */
 
 	chipid_reg = 0;
 
 	chipid_reg = 0;
 
 
 
-	switch (c->cputype) {
 
+	switch (current_cpu_type()) {
 
 	case CPU_BMIPS3300:
 
 	case CPU_BMIPS3300:
 
 		if ((read_c0_prid() & PRID_IMP_MASK) != PRID_IMP_BMIPS3300_ALT)
 
 		if ((read_c0_prid() & PRID_IMP_MASK) != PRID_IMP_BMIPS3300_ALT)
 
 			__cpu_name[cpu] = "Broadcom BCM6338";
 
 			__cpu_name[cpu] = "Broadcom BCM6338";

+ 0 - 359
arch/mips/configs/db1000_defconfig
Vizualizați fișierul 

@@ -1,359 +0,0 @@
 
-CONFIG_MIPS=y
 
-CONFIG_MIPS_ALCHEMY=y
 
-CONFIG_MIPS_DB1000=y
 
-CONFIG_SCHED_OMIT_FRAME_POINTER=y
 
-CONFIG_TICK_ONESHOT=y
 
-CONFIG_NO_HZ=y
 
-CONFIG_HIGH_RES_TIMERS=y
 
-CONFIG_HZ_100=y
 
-CONFIG_HZ=100
 
-CONFIG_PREEMPT_NONE=y
 
-CONFIG_EXPERIMENTAL=y
 
-CONFIG_BROKEN_ON_SMP=y
 
-CONFIG_INIT_ENV_ARG_LIMIT=32
 
-CONFIG_CROSS_COMPILE=""
 
-CONFIG_LOCALVERSION="-db1x00"
 
-CONFIG_LOCALVERSION_AUTO=y
 
-CONFIG_KERNEL_LZMA=y
 
-CONFIG_DEFAULT_HOSTNAME="db1x00"
 
-CONFIG_SWAP=y
 
-CONFIG_SYSVIPC=y
 
-CONFIG_SYSVIPC_SYSCTL=y
 
-CONFIG_FHANDLE=y
 
-CONFIG_AUDIT=y
 
-CONFIG_TINY_RCU=y
 
-CONFIG_LOG_BUF_SHIFT=18
 
-CONFIG_NAMESPACES=y
 
-CONFIG_UTS_NS=y
 
-CONFIG_IPC_NS=y
 
-CONFIG_USER_NS=y
 
-CONFIG_PID_NS=y
 
-CONFIG_NET_NS=y
 
-CONFIG_SYSCTL=y
 
-CONFIG_EXPERT=y
 
-CONFIG_KALLSYMS=y
 
-CONFIG_KALLSYMS_ALL=y
 
-CONFIG_HOTPLUG=y
 
-CONFIG_PRINTK=y
 
-CONFIG_BUG=y
 
-CONFIG_ELF_CORE=y
 
-CONFIG_BASE_FULL=y
 
-CONFIG_FUTEX=y
 
-CONFIG_EPOLL=y
 
-CONFIG_SIGNALFD=y
 
-CONFIG_TIMERFD=y
 
-CONFIG_EVENTFD=y
 
-CONFIG_SHMEM=y
 
-CONFIG_AIO=y
 
-CONFIG_EMBEDDED=y
 
-CONFIG_HAVE_PERF_EVENTS=y
 
-CONFIG_PERF_USE_VMALLOC=y
 
-CONFIG_PCI_QUIRKS=y
 
-CONFIG_SLAB=y
 
-CONFIG_SLABINFO=y
 
-CONFIG_BLOCK=y
 
-CONFIG_LBDAF=y
 
-CONFIG_BLK_DEV_BSG=y
 
-CONFIG_BLK_DEV_BSGLIB=y
 
-CONFIG_IOSCHED_NOOP=y
 
-CONFIG_DEFAULT_NOOP=y
 
-CONFIG_DEFAULT_IOSCHED="noop"
 
-CONFIG_FREEZER=y
 
-CONFIG_PCI=y
 
-CONFIG_PCI_DOMAINS=y
 
-CONFIG_PCCARD=y
 
-CONFIG_PCMCIA=y
 
-CONFIG_PCMCIA_LOAD_CIS=y
 
-CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
 
-CONFIG_BINFMT_ELF=y
 
-CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
 
-CONFIG_SUSPEND=y
 
-CONFIG_SUSPEND_FREEZER=y
 
-CONFIG_PM_SLEEP=y
 
-CONFIG_PM_RUNTIME=y
 
-CONFIG_PM=y
 
-CONFIG_NET=y
 
-CONFIG_PACKET=y
 
-CONFIG_UNIX=y
 
-CONFIG_XFRM=y
 
-CONFIG_INET=y
 
-CONFIG_IP_MULTICAST=y
 
-CONFIG_IP_PNP=y
 
-CONFIG_IP_PNP_DHCP=y
 
-CONFIG_IP_PNP_BOOTP=y
 
-CONFIG_IP_PNP_RARP=y
 
-CONFIG_NET_IPIP=y
 
-CONFIG_INET_TUNNEL=y
 
-CONFIG_INET_LRO=y
 
-CONFIG_TCP_CONG_CUBIC=y
 
-CONFIG_DEFAULT_TCP_CONG="cubic"
 
-CONFIG_IPV6=y
 
-CONFIG_INET6_XFRM_MODE_TRANSPORT=y
 
-CONFIG_INET6_XFRM_MODE_TUNNEL=y
 
-CONFIG_INET6_XFRM_MODE_BEET=y
 
-CONFIG_IPV6_SIT=y
 
-CONFIG_IPV6_NDISC_NODETYPE=y
 
-CONFIG_STP=y
 
-CONFIG_GARP=y
 
-CONFIG_BRIDGE=y
 
-CONFIG_BRIDGE_IGMP_SNOOPING=y
 
-CONFIG_VLAN_8021Q=y
 
-CONFIG_VLAN_8021Q_GVRP=y
 
-CONFIG_LLC=y
 
-CONFIG_LLC2=y
 
-CONFIG_DNS_RESOLVER=y
 
-CONFIG_BT=y
 
-CONFIG_BT_L2CAP=y
 
-CONFIG_BT_SCO=y
 
-CONFIG_BT_RFCOMM=y
 
-CONFIG_BT_RFCOMM_TTY=y
 
-CONFIG_BT_BNEP=y
 
-CONFIG_BT_BNEP_MC_FILTER=y
 
-CONFIG_BT_BNEP_PROTO_FILTER=y
 
-CONFIG_BT_HIDP=y
 
-CONFIG_BT_HCIBTUSB=y
 
-CONFIG_UEVENT_HELPER_PATH=""
 
-CONFIG_STANDALONE=y
 
-CONFIG_PREVENT_FIRMWARE_BUILD=y
 
-CONFIG_FW_LOADER=y
 
-CONFIG_MTD=y
 
-CONFIG_MTD_CMDLINE_PARTS=y
 
-CONFIG_MTD_CHAR=y
 
-CONFIG_MTD_BLKDEVS=y
 
-CONFIG_MTD_BLOCK=y
 
-CONFIG_MTD_CFI=y
 
-CONFIG_MTD_GEN_PROBE=y
 
-CONFIG_MTD_CFI_ADV_OPTIONS=y
 
-CONFIG_MTD_CFI_NOSWAP=y
 
-CONFIG_MTD_CFI_GEOMETRY=y
 
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
 
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
 
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
 
-CONFIG_MTD_CFI_I1=y
 
-CONFIG_MTD_CFI_I2=y
 
-CONFIG_MTD_CFI_I4=y
 
-CONFIG_MTD_CFI_I8=y
 
-CONFIG_MTD_CFI_INTELEXT=y
 
-CONFIG_MTD_CFI_AMDSTD=y
 
-CONFIG_MTD_CFI_UTIL=y
 
-CONFIG_MTD_PHYSMAP=y
 
-CONFIG_SCSI_MOD=y
 
-CONFIG_SCSI=y
 
-CONFIG_SCSI_DMA=y
 
-CONFIG_SCSI_PROC_FS=y
 
-CONFIG_BLK_DEV_SD=y
 
-CONFIG_CHR_DEV_SG=y
 
-CONFIG_SCSI_MULTI_LUN=y
 
-CONFIG_SCSI_CONSTANTS=y
 
-CONFIG_ATA=y
 
-CONFIG_ATA_VERBOSE_ERROR=y
 
-CONFIG_ATA_SFF=y
 
-CONFIG_ATA_BMDMA=y
 
-CONFIG_PATA_HPT37X=y
 
-CONFIG_PATA_PCMCIA=y
 
-CONFIG_MD=y
 
-CONFIG_BLK_DEV_DM=y
 
-CONFIG_FIREWIRE=y
 
-CONFIG_FIREWIRE_OHCI=y
 
-CONFIG_FIREWIRE_OHCI_DEBUG=y
 
-CONFIG_FIREWIRE_NET=y
 
-CONFIG_NETDEVICES=y
 
-CONFIG_MII=y
 
-CONFIG_PHYLIB=y
 
-CONFIG_NET_ETHERNET=y
 
-CONFIG_MIPS_AU1X00_ENET=y
 
-CONFIG_NET_PCMCIA=y
 
-CONFIG_PCMCIA_3C589=y
 
-CONFIG_PCMCIA_PCNET=y
 
-CONFIG_PPP=y
 
-CONFIG_PPP_MULTILINK=y
 
-CONFIG_PPP_FILTER=y
 
-CONFIG_PPP_ASYNC=y
 
-CONFIG_PPP_SYNC_TTY=y
 
-CONFIG_PPP_DEFLATE=y
 
-CONFIG_PPP_BSDCOMP=y
 
-CONFIG_PPP_MPPE=y
 
-CONFIG_PPPOE=y
 
-CONFIG_INPUT=y
 
-CONFIG_INPUT_EVDEV=y
 
-CONFIG_INPUT_MISC=y
 
-CONFIG_INPUT_UINPUT=y
 
-CONFIG_VT=y
 
-CONFIG_CONSOLE_TRANSLATIONS=y
 
-CONFIG_VT_CONSOLE=y
 
-CONFIG_HW_CONSOLE=y
 
-CONFIG_UNIX98_PTYS=y
 
-CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
 
-CONFIG_DEVKMEM=y
 
-CONFIG_SERIAL_8250=y
 
-CONFIG_SERIAL_8250_CONSOLE=y
 
-CONFIG_SERIAL_8250_NR_UARTS=4
 
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
 
-CONFIG_SERIAL_CORE=y
 
-CONFIG_SERIAL_CORE_CONSOLE=y
 
-CONFIG_TTY_PRINTK=y
 
-CONFIG_DEVPORT=y
 
-CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
 
-CONFIG_FB=y
 
-CONFIG_FB_CFB_FILLRECT=y
 
-CONFIG_FB_CFB_COPYAREA=y
 
-CONFIG_FB_CFB_IMAGEBLIT=y
 
-CONFIG_FB_AU1100=y
 
-CONFIG_DUMMY_CONSOLE=y
 
-CONFIG_FRAMEBUFFER_CONSOLE=y
 
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
 
-CONFIG_FONTS=y
 
-CONFIG_FONT_8x16=y
 
-CONFIG_SOUND=y
 
-CONFIG_SND=y
 
-CONFIG_SND_TIMER=y
 
-CONFIG_SND_PCM=y
 
-CONFIG_SND_JACK=y
 
-CONFIG_SND_SEQUENCER=y
 
-CONFIG_SND_HRTIMER=y
 
-CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
 
-CONFIG_SND_DYNAMIC_MINORS=y
 
-CONFIG_SND_VMASTER=y
 
-CONFIG_SND_AC97_CODEC=y
 
-CONFIG_SND_SOC=y
 
-CONFIG_SND_SOC_AC97_BUS=y
 
-CONFIG_SND_SOC_AU1XAUDIO=y
 
-CONFIG_SND_SOC_AU1XAC97C=y
 
-CONFIG_SND_SOC_DB1000=y
 
-CONFIG_SND_SOC_AC97_CODEC=y
 
-CONFIG_AC97_BUS=y
 
-CONFIG_HID_SUPPORT=y
 
-CONFIG_HID=y
 
-CONFIG_HIDRAW=y
 
-CONFIG_USB_HID=y
 
-CONFIG_USB_SUPPORT=y
 
-CONFIG_USB=y
 
-CONFIG_USB_EHCI_HCD=y
 
-CONFIG_USB_EHCI_ROOT_HUB_TT=y
 
-CONFIG_USB_EHCI_TT_NEWSCHED=y
 
-CONFIG_USB_OHCI_HCD=y
 
-CONFIG_USB_OHCI_HCD_PLATFORM=y
 
-CONFIG_USB_UHCI_HCD=y
 
-CONFIG_USB_STORAGE=y
 
-CONFIG_NEW_LEDS=y
 
-CONFIG_LEDS_CLASS=y
 
-CONFIG_LEDS_TRIGGERS=y
 
-CONFIG_RTC_LIB=y
 
-CONFIG_RTC_CLASS=y
 
-CONFIG_RTC_HCTOSYS=y
 
-CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
 
-CONFIG_RTC_INTF_SYSFS=y
 
-CONFIG_RTC_INTF_PROC=y
 
-CONFIG_RTC_INTF_DEV=y
 
-CONFIG_RTC_DRV_AU1XXX=y
 
-CONFIG_EXT4_FS=y
 
-CONFIG_EXT4_USE_FOR_EXT23=y
 
-CONFIG_EXT4_FS_XATTR=y
 
-CONFIG_EXT4_FS_POSIX_ACL=y
 
-CONFIG_EXT4_FS_SECURITY=y
 
-CONFIG_JBD2=y
 
-CONFIG_FS_MBCACHE=y
 
-CONFIG_FS_POSIX_ACL=y
 
-CONFIG_EXPORTFS=y
 
-CONFIG_FILE_LOCKING=y
 
-CONFIG_FSNOTIFY=y
 
-CONFIG_DNOTIFY=y
 
-CONFIG_INOTIFY_USER=y
 
-CONFIG_GENERIC_ACL=y
 
-CONFIG_PROC_FS=y
 
-CONFIG_PROC_KCORE=y
 
-CONFIG_PROC_SYSCTL=y
 
-CONFIG_SYSFS=y
 
-CONFIG_TMPFS=y
 
-CONFIG_TMPFS_POSIX_ACL=y
 
-CONFIG_TMPFS_XATTR=y
 
-CONFIG_MISC_FILESYSTEMS=y
 
-CONFIG_JFFS2_FS=y
 
-CONFIG_JFFS2_FS_DEBUG=0
 
-CONFIG_JFFS2_FS_WRITEBUFFER=y
 
-CONFIG_JFFS2_SUMMARY=y
 
-CONFIG_JFFS2_FS_XATTR=y
 
-CONFIG_JFFS2_FS_POSIX_ACL=y
 
-CONFIG_JFFS2_FS_SECURITY=y
 
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
 
-CONFIG_JFFS2_ZLIB=y
 
-CONFIG_JFFS2_LZO=y
 
-CONFIG_JFFS2_RTIME=y
 
-CONFIG_JFFS2_RUBIN=y
 
-CONFIG_JFFS2_CMODE_PRIORITY=y
 
-CONFIG_SQUASHFS=y
 
-CONFIG_SQUASHFS_ZLIB=y
 
-CONFIG_SQUASHFS_LZO=y
 
-CONFIG_SQUASHFS_XZ=y
 
-CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
 
-CONFIG_NETWORK_FILESYSTEMS=y
 
-CONFIG_NFS_FS=y
 
-CONFIG_NFS_V3=y
 
-CONFIG_NFS_V4=y
 
-CONFIG_NFS_V4_1=y
 
-CONFIG_PNFS_FILE_LAYOUT=y
 
-CONFIG_PNFS_BLOCK=y
 
-CONFIG_ROOT_NFS=y
 
-CONFIG_NFS_USE_KERNEL_DNS=y
 
-CONFIG_NFS_USE_NEW_IDMAPPER=y
 
-CONFIG_NFSD=y
 
-CONFIG_NFSD_V2_ACL=y
 
-CONFIG_NFSD_V3=y
 
-CONFIG_NFSD_V3_ACL=y
 
-CONFIG_NFSD_V4=y
 
-CONFIG_LOCKD=y
 
-CONFIG_LOCKD_V4=y
 
-CONFIG_NFS_ACL_SUPPORT=y
 
-CONFIG_NFS_COMMON=y
 
-CONFIG_SUNRPC=y
 
-CONFIG_SUNRPC_GSS=y
 
-CONFIG_SUNRPC_BACKCHANNEL=y
 
-CONFIG_MSDOS_PARTITION=y
 
-CONFIG_NLS=y
 
-CONFIG_NLS_DEFAULT="iso8859-1"
 
-CONFIG_NLS_CODEPAGE_437=y
 
-CONFIG_NLS_CODEPAGE_850=y
 
-CONFIG_NLS_CODEPAGE_1250=y
 
-CONFIG_NLS_ASCII=y
 
-CONFIG_NLS_ISO8859_1=y
 
-CONFIG_NLS_ISO8859_15=y
 
-CONFIG_NLS_UTF8=y
 
-CONFIG_HAVE_ARCH_KGDB=y
 
-CONFIG_EARLY_PRINTK=y
 
-CONFIG_CMDLINE_BOOL=y
 
-CONFIG_CMDLINE="noirqdebug rootwait root=/dev/sda1 rootfstype=ext4 console=ttyS0,115200 video=au1100fb:panel:CRT_800x600_16"
 
-CONFIG_DEBUG_ZBOOT=y
 
-CONFIG_KEYS=y
 
-CONFIG_KEYS_DEBUG_PROC_KEYS=y
 
-CONFIG_SECURITYFS=y
 
-CONFIG_DEFAULT_SECURITY_DAC=y
 
-CONFIG_DEFAULT_SECURITY=""
 
-CONFIG_CRYPTO=y
 
-CONFIG_CRYPTO_ALGAPI=y
 
-CONFIG_CRYPTO_ALGAPI2=y
 
-CONFIG_CRYPTO_AEAD2=y
 
-CONFIG_CRYPTO_BLKCIPHER=y
 
-CONFIG_CRYPTO_BLKCIPHER2=y
 
-CONFIG_CRYPTO_HASH=y
 
-CONFIG_CRYPTO_HASH2=y
 
-CONFIG_CRYPTO_RNG=y
 
-CONFIG_CRYPTO_RNG2=y
 
-CONFIG_CRYPTO_PCOMP2=y
 
-CONFIG_CRYPTO_MANAGER=y
 
-CONFIG_CRYPTO_MANAGER2=y
 
-CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
 
-CONFIG_CRYPTO_WORKQUEUE=y
 
-CONFIG_CRYPTO_ECB=y
 
-CONFIG_CRYPTO_SHA1=y
 
-CONFIG_CRYPTO_AES=y
 
-CONFIG_CRYPTO_ANSI_CPRNG=y
 
-CONFIG_BITREVERSE=y
 
-CONFIG_CRC_CCITT=y
 
-CONFIG_CRC16=y
 
-CONFIG_CRC_ITU_T=y
 
-CONFIG_CRC32=y
 
-CONFIG_ZLIB_INFLATE=y
 
-CONFIG_ZLIB_DEFLATE=y
 
-CONFIG_LZO_COMPRESS=y
 
-CONFIG_LZO_DECOMPRESS=y
 
-CONFIG_XZ_DEC=y

+ 0 - 434
arch/mips/configs/db1235_defconfig
Vizualizați fișierul 

@@ -1,434 +0,0 @@
 
-CONFIG_MIPS_ALCHEMY=y
 
-CONFIG_MIPS_DB1235=y
 
-CONFIG_COMPACTION=y
 
-CONFIG_KSM=y
 
-CONFIG_HZ_100=y
 
-CONFIG_EXPERIMENTAL=y
 
-CONFIG_LOCALVERSION="-db1235"
 
-CONFIG_KERNEL_LZMA=y
 
-CONFIG_DEFAULT_HOSTNAME="db1235"
 
-CONFIG_SYSVIPC=y
 
-CONFIG_POSIX_MQUEUE=y
 
-CONFIG_BSD_PROCESS_ACCT=y
 
-CONFIG_BSD_PROCESS_ACCT_V3=y
 
-CONFIG_FHANDLE=y
 
-CONFIG_TASKSTATS=y
 
-CONFIG_TASK_DELAY_ACCT=y
 
-CONFIG_AUDIT=y
 
-CONFIG_AUDIT_LOGINUID_IMMUTABLE=y
 
-CONFIG_NO_HZ=y
 
-CONFIG_HIGH_RES_TIMERS=y
 
-CONFIG_LOG_BUF_SHIFT=16
 
-CONFIG_NAMESPACES=y
 
-CONFIG_EMBEDDED=y
 
-CONFIG_SLAB=y
 
-CONFIG_JUMP_LABEL=y
 
-CONFIG_PARTITION_ADVANCED=y
 
-CONFIG_LDM_PARTITION=y
 
-CONFIG_EFI_PARTITION=y
 
-CONFIG_PCI=y
 
-CONFIG_PCCARD=y
 
-CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
 
-CONFIG_PM_RUNTIME=y
 
-CONFIG_NET=y
 
-CONFIG_PACKET=y
 
-CONFIG_UNIX=y
 
-CONFIG_UNIX_DIAG=y
 
-CONFIG_XFRM_USER=y
 
-CONFIG_INET=y
 
-CONFIG_IP_MULTICAST=y
 
-CONFIG_IP_ADVANCED_ROUTER=y
 
-CONFIG_IP_MULTIPLE_TABLES=y
 
-CONFIG_IP_ROUTE_MULTIPATH=y
 
-CONFIG_IP_ROUTE_VERBOSE=y
 
-CONFIG_IP_PNP=y
 
-CONFIG_IP_PNP_DHCP=y
 
-CONFIG_IP_PNP_BOOTP=y
 
-CONFIG_IP_PNP_RARP=y
 
-CONFIG_NET_IPIP=y
 
-CONFIG_NET_IPGRE_DEMUX=y
 
-CONFIG_NET_IPGRE=y
 
-CONFIG_NET_IPGRE_BROADCAST=y
 
-CONFIG_IP_MROUTE=y
 
-CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
 
-CONFIG_IP_PIMSM_V1=y
 
-CONFIG_IP_PIMSM_V2=y
 
-CONFIG_ARPD=y
 
-CONFIG_SYN_COOKIES=y
 
-CONFIG_NET_IPVTI=y
 
-CONFIG_INET_AH=y
 
-CONFIG_INET_ESP=y
 
-CONFIG_INET_IPCOMP=y
 
-CONFIG_INET_UDP_DIAG=y
 
-CONFIG_TCP_CONG_ADVANCED=y
 
-CONFIG_TCP_CONG_HSTCP=y
 
-CONFIG_TCP_CONG_HYBLA=y
 
-CONFIG_TCP_CONG_SCALABLE=y
 
-CONFIG_TCP_CONG_LP=y
 
-CONFIG_TCP_CONG_VENO=y
 
-CONFIG_TCP_CONG_YEAH=y
 
-CONFIG_TCP_CONG_ILLINOIS=y
 
-CONFIG_DEFAULT_HYBLA=y
 
-CONFIG_TCP_MD5SIG=y
 
-CONFIG_IPV6_PRIVACY=y
 
-CONFIG_IPV6_ROUTER_PREF=y
 
-CONFIG_IPV6_ROUTE_INFO=y
 
-CONFIG_IPV6_OPTIMISTIC_DAD=y
 
-CONFIG_INET6_AH=y
 
-CONFIG_INET6_ESP=y
 
-CONFIG_INET6_IPCOMP=y
 
-CONFIG_IPV6_MIP6=y
 
-CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=y
 
-CONFIG_IPV6_SIT_6RD=y
 
-CONFIG_IPV6_TUNNEL=y
 
-CONFIG_IPV6_MULTIPLE_TABLES=y
 
-CONFIG_IPV6_SUBTREES=y
 
-CONFIG_IPV6_MROUTE=y
 
-CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
 
-CONFIG_IPV6_PIMSM_V2=y
 
-CONFIG_NETFILTER=y
 
-CONFIG_NF_CONNTRACK=y
 
-CONFIG_NF_CONNTRACK_EVENTS=y
 
-CONFIG_NF_CONNTRACK_TIMEOUT=y
 
-CONFIG_NF_CONNTRACK_TIMESTAMP=y
 
-CONFIG_NF_CT_PROTO_DCCP=y
 
-CONFIG_NF_CT_PROTO_SCTP=y
 
-CONFIG_NF_CT_PROTO_UDPLITE=y
 
-CONFIG_NF_CONNTRACK_AMANDA=y
 
-CONFIG_NF_CONNTRACK_FTP=y
 
-CONFIG_NF_CONNTRACK_H323=y
 
-CONFIG_NF_CONNTRACK_IRC=y
 
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
 
-CONFIG_NF_CONNTRACK_SNMP=y
 
-CONFIG_NF_CONNTRACK_PPTP=y
 
-CONFIG_NF_CONNTRACK_SANE=y
 
-CONFIG_NF_CONNTRACK_SIP=y
 
-CONFIG_NF_CONNTRACK_TFTP=y
 
-CONFIG_NF_CT_NETLINK=y
 
-CONFIG_NF_CT_NETLINK_TIMEOUT=y
 
-CONFIG_NF_CT_NETLINK_HELPER=y
 
-CONFIG_NETFILTER_NETLINK_QUEUE_CT=y
 
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
 
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
 
-CONFIG_NETFILTER_XT_TARGET_HMARK=y
 
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
 
-CONFIG_NETFILTER_XT_TARGET_LED=y
 
-CONFIG_NETFILTER_XT_TARGET_LOG=y
 
-CONFIG_NETFILTER_XT_TARGET_MARK=y
 
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
 
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
 
-CONFIG_NETFILTER_XT_TARGET_TEE=y
 
-CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
 
-CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y
 
-CONFIG_NETFILTER_XT_MATCH_CLUSTER=y
 
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
 
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
 
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
 
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
 
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
 
-CONFIG_NETFILTER_XT_MATCH_CPU=y
 
-CONFIG_NETFILTER_XT_MATCH_DCCP=y
 
-CONFIG_NETFILTER_XT_MATCH_DEVGROUP=y
 
-CONFIG_NETFILTER_XT_MATCH_DSCP=y
 
-CONFIG_NETFILTER_XT_MATCH_ESP=y
 
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
 
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
 
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
 
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
 
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
 
-CONFIG_NETFILTER_XT_MATCH_MAC=y
 
-CONFIG_NETFILTER_XT_MATCH_MARK=y
 
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
 
-CONFIG_NETFILTER_XT_MATCH_NFACCT=y
 
-CONFIG_NETFILTER_XT_MATCH_OSF=y
 
-CONFIG_NETFILTER_XT_MATCH_OWNER=y
 
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
 
-CONFIG_NETFILTER_XT_MATCH_PHYSDEV=y
 
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
 
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
 
-CONFIG_NETFILTER_XT_MATCH_RATEEST=y
 
-CONFIG_NETFILTER_XT_MATCH_REALM=y
 
-CONFIG_NETFILTER_XT_MATCH_RECENT=y
 
-CONFIG_NETFILTER_XT_MATCH_SCTP=y
 
-CONFIG_NETFILTER_XT_MATCH_STATE=y
 
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
 
-CONFIG_NETFILTER_XT_MATCH_STRING=y
 
-CONFIG_NETFILTER_XT_MATCH_TCPMSS=y
 
-CONFIG_NETFILTER_XT_MATCH_TIME=y
 
-CONFIG_NETFILTER_XT_MATCH_U32=y
 
-CONFIG_NF_CONNTRACK_IPV4=y
 
-CONFIG_IP_NF_IPTABLES=y
 
-CONFIG_IP_NF_MATCH_AH=y
 
-CONFIG_IP_NF_MATCH_ECN=y
 
-CONFIG_IP_NF_MATCH_RPFILTER=y
 
-CONFIG_IP_NF_MATCH_TTL=y
 
-CONFIG_IP_NF_FILTER=y
 
-CONFIG_IP_NF_TARGET_REJECT=y
 
-CONFIG_IP_NF_TARGET_ULOG=y
 
-CONFIG_NF_NAT=y
 
-CONFIG_IP_NF_TARGET_MASQUERADE=y
 
-CONFIG_IP_NF_TARGET_NETMAP=y
 
-CONFIG_IP_NF_TARGET_REDIRECT=y
 
-CONFIG_IP_NF_MANGLE=y
 
-CONFIG_IP_NF_TARGET_CLUSTERIP=y
 
-CONFIG_IP_NF_TARGET_ECN=y
 
-CONFIG_IP_NF_TARGET_TTL=y
 
-CONFIG_IP_NF_RAW=y
 
-CONFIG_IP_NF_ARPTABLES=y
 
-CONFIG_IP_NF_ARPFILTER=y
 
-CONFIG_IP_NF_ARP_MANGLE=y
 
-CONFIG_NF_CONNTRACK_IPV6=y
 
-CONFIG_IP6_NF_IPTABLES=y
 
-CONFIG_IP6_NF_MATCH_AH=y
 
-CONFIG_IP6_NF_MATCH_EUI64=y
 
-CONFIG_IP6_NF_MATCH_FRAG=y
 
-CONFIG_IP6_NF_MATCH_OPTS=y
 
-CONFIG_IP6_NF_MATCH_HL=y
 
-CONFIG_IP6_NF_MATCH_IPV6HEADER=y
 
-CONFIG_IP6_NF_MATCH_MH=y
 
-CONFIG_IP6_NF_MATCH_RPFILTER=y
 
-CONFIG_IP6_NF_MATCH_RT=y
 
-CONFIG_IP6_NF_TARGET_HL=y
 
-CONFIG_IP6_NF_FILTER=y
 
-CONFIG_IP6_NF_TARGET_REJECT=y
 
-CONFIG_IP6_NF_MANGLE=y
 
-CONFIG_IP6_NF_RAW=y
 
-CONFIG_BRIDGE_NF_EBTABLES=y
 
-CONFIG_BRIDGE_EBT_BROUTE=y
 
-CONFIG_BRIDGE_EBT_T_FILTER=y
 
-CONFIG_BRIDGE_EBT_T_NAT=y
 
-CONFIG_BRIDGE_EBT_802_3=y
 
-CONFIG_BRIDGE_EBT_AMONG=y
 
-CONFIG_BRIDGE_EBT_ARP=y
 
-CONFIG_BRIDGE_EBT_IP=y
 
-CONFIG_BRIDGE_EBT_IP6=y
 
-CONFIG_BRIDGE_EBT_LIMIT=y
 
-CONFIG_BRIDGE_EBT_MARK=y
 
-CONFIG_BRIDGE_EBT_PKTTYPE=y
 
-CONFIG_BRIDGE_EBT_STP=y
 
-CONFIG_BRIDGE_EBT_VLAN=y
 
-CONFIG_BRIDGE_EBT_ARPREPLY=y
 
-CONFIG_BRIDGE_EBT_DNAT=y
 
-CONFIG_BRIDGE_EBT_MARK_T=y
 
-CONFIG_BRIDGE_EBT_REDIRECT=y
 
-CONFIG_BRIDGE_EBT_SNAT=y
 
-CONFIG_BRIDGE_EBT_LOG=y
 
-CONFIG_BRIDGE_EBT_NFLOG=y
 
-CONFIG_L2TP=y
 
-CONFIG_L2TP_V3=y
 
-CONFIG_L2TP_IP=y
 
-CONFIG_L2TP_ETH=y
 
-CONFIG_BRIDGE=y
 
-CONFIG_VLAN_8021Q=y
 
-CONFIG_VLAN_8021Q_GVRP=y
 
-CONFIG_LLC2=y
 
-CONFIG_NET_SCHED=y
 
-CONFIG_NET_SCH_CBQ=y
 
-CONFIG_NET_SCH_HTB=y
 
-CONFIG_NET_SCH_HFSC=y
 
-CONFIG_NET_SCH_PRIO=y
 
-CONFIG_NET_SCH_MULTIQ=y
 
-CONFIG_NET_SCH_RED=y
 
-CONFIG_NET_SCH_SFB=y
 
-CONFIG_NET_SCH_SFQ=y
 
-CONFIG_NET_SCH_TEQL=y
 
-CONFIG_NET_SCH_TBF=y
 
-CONFIG_NET_SCH_GRED=y
 
-CONFIG_NET_SCH_DSMARK=y
 
-CONFIG_NET_SCH_NETEM=y
 
-CONFIG_NET_SCH_DRR=y
 
-CONFIG_NET_SCH_MQPRIO=y
 
-CONFIG_NET_SCH_CHOKE=y
 
-CONFIG_NET_SCH_QFQ=y
 
-CONFIG_NET_SCH_CODEL=y
 
-CONFIG_NET_SCH_FQ_CODEL=y
 
-CONFIG_NET_SCH_INGRESS=y
 
-CONFIG_NET_SCH_PLUG=y
 
-CONFIG_NET_CLS_BASIC=y
 
-CONFIG_NET_CLS_TCINDEX=y
 
-CONFIG_NET_CLS_ROUTE4=y
 
-CONFIG_NET_CLS_FW=y
 
-CONFIG_NET_CLS_U32=y
 
-CONFIG_CLS_U32_PERF=y
 
-CONFIG_CLS_U32_MARK=y
 
-CONFIG_NET_CLS_RSVP=y
 
-CONFIG_NET_CLS_RSVP6=y
 
-CONFIG_NET_CLS_FLOW=y
 
-CONFIG_NET_EMATCH=y
 
-CONFIG_NET_EMATCH_CMP=y
 
-CONFIG_NET_EMATCH_NBYTE=y
 
-CONFIG_NET_EMATCH_U32=y
 
-CONFIG_NET_EMATCH_META=y
 
-CONFIG_NET_EMATCH_TEXT=y
 
-CONFIG_NET_CLS_ACT=y
 
-CONFIG_NET_ACT_POLICE=y
 
-CONFIG_NET_ACT_GACT=y
 
-CONFIG_GACT_PROB=y
 
-CONFIG_NET_ACT_MIRRED=y
 
-CONFIG_NET_ACT_NAT=y
 
-CONFIG_NET_ACT_PEDIT=y
 
-CONFIG_NET_ACT_SIMP=y
 
-CONFIG_NET_ACT_SKBEDIT=y
 
-CONFIG_NET_ACT_CSUM=y
 
-CONFIG_NET_CLS_IND=y
 
-CONFIG_BT=y
 
-CONFIG_BT_RFCOMM=y
 
-CONFIG_BT_RFCOMM_TTY=y
 
-CONFIG_BT_BNEP=y
 
-CONFIG_BT_BNEP_MC_FILTER=y
 
-CONFIG_BT_BNEP_PROTO_FILTER=y
 
-CONFIG_BT_HIDP=y
 
-CONFIG_BT_HCIBTUSB=y
 
-CONFIG_CFG80211=y
 
-CONFIG_CFG80211_CERTIFICATION_ONUS=y
 
-CONFIG_CFG80211_WEXT=y
 
-CONFIG_MAC80211=y
 
-CONFIG_MAC80211_LEDS=y
 
-CONFIG_RFKILL=y
 
-CONFIG_RFKILL_INPUT=y
 
-CONFIG_DEVTMPFS=y
 
-CONFIG_DEVTMPFS_MOUNT=y
 
-CONFIG_MTD=y
 
-CONFIG_MTD_CHAR=y
 
-CONFIG_MTD_BLOCK=y
 
-CONFIG_MTD_CFI=y
 
-CONFIG_MTD_CFI_AMDSTD=y
 
-CONFIG_MTD_PHYSMAP=y
 
-CONFIG_MTD_M25P80=y
 
-CONFIG_MTD_NAND=y
 
-CONFIG_MTD_NAND_PLATFORM=y
 
-CONFIG_EEPROM_AT24=y
 
-CONFIG_EEPROM_AT25=y
 
-CONFIG_IDE=y
 
-CONFIG_BLK_DEV_IDE_AU1XXX=y
 
-CONFIG_BLK_DEV_SD=y
 
-CONFIG_CHR_DEV_SG=y
 
-CONFIG_SCSI_MULTI_LUN=y
 
-CONFIG_ATA=y
 
-CONFIG_PATA_HPT37X=y
 
-CONFIG_PATA_PCMCIA=y
 
-CONFIG_PATA_PLATFORM=y
 
-CONFIG_NETDEVICES=y
 
-CONFIG_MIPS_AU1X00_ENET=y
 
-CONFIG_SMC91X=y
 
-CONFIG_SMSC911X=y
 
-CONFIG_AMD_PHY=y
 
-CONFIG_SMSC_PHY=y
 
-CONFIG_RT2X00=y
 
-CONFIG_RT73USB=y
 
-CONFIG_INPUT_EVDEV=y
 
-CONFIG_INPUT_TOUCHSCREEN=y
 
-CONFIG_TOUCHSCREEN_WM97XX=y
 
-CONFIG_INPUT_MISC=y
 
-CONFIG_INPUT_UINPUT=y
 
-CONFIG_SERIAL_8250=y
 
-CONFIG_SERIAL_8250_CONSOLE=y
 
-CONFIG_TTY_PRINTK=y
 
-CONFIG_I2C=y
 
-CONFIG_I2C_CHARDEV=y
 
-CONFIG_I2C_AU1550=y
 
-CONFIG_SPI=y
 
-CONFIG_SPI_AU1550=y
 
-CONFIG_GPIO_SYSFS=y
 
-CONFIG_SENSORS_ADM1025=y
 
-CONFIG_SENSORS_LM70=y
 
-CONFIG_SOUND=y
 
-CONFIG_SND=y
 
-CONFIG_SND_HRTIMER=y
 
-CONFIG_SND_DYNAMIC_MINORS=y
 
-CONFIG_SND_SOC=y
 
-CONFIG_SND_SOC_AU1XPSC=y
 
-CONFIG_SND_SOC_DB1200=y
 
-CONFIG_HIDRAW=y
 
-CONFIG_UHID=y
 
-CONFIG_USB_HIDDEV=y
 
-CONFIG_USB=y
 
-CONFIG_USB_DYNAMIC_MINORS=y
 
-CONFIG_USB_EHCI_HCD=y
 
-CONFIG_USB_EHCI_HCD_PLATFORM=y
 
-CONFIG_USB_EHCI_ROOT_HUB_TT=y
 
-CONFIG_USB_OHCI_HCD=y
 
-CONFIG_USB_OHCI_HCD_PLATFORM=y
 
-CONFIG_USB_STORAGE=y
 
-CONFIG_MMC=y
 
-CONFIG_MMC_AU1X=y
 
-CONFIG_NEW_LEDS=y
 
-CONFIG_LEDS_CLASS=y
 
-CONFIG_RTC_CLASS=y
 
-CONFIG_RTC_DRV_AU1XXX=y
 
-CONFIG_EXT4_FS=y
 
-CONFIG_EXT4_FS_POSIX_ACL=y
 
-CONFIG_EXT4_FS_SECURITY=y
 
-CONFIG_XFS_FS=y
 
-CONFIG_XFS_POSIX_ACL=y
 
-CONFIG_VFAT_FS=y
 
-CONFIG_TMPFS=y
 
-CONFIG_TMPFS_POSIX_ACL=y
 
-CONFIG_CONFIGFS_FS=y
 
-CONFIG_JFFS2_FS=y
 
-CONFIG_JFFS2_SUMMARY=y
 
-CONFIG_JFFS2_FS_XATTR=y
 
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
 
-CONFIG_JFFS2_LZO=y
 
-CONFIG_JFFS2_CMODE_FAVOURLZO=y
 
-CONFIG_SQUASHFS=y
 
-CONFIG_SQUASHFS_LZO=y
 
-CONFIG_SQUASHFS_XZ=y
 
-CONFIG_NFS_FS=y
 
-CONFIG_NFS_V3_ACL=y
 
-CONFIG_NFS_V4=y
 
-CONFIG_NFS_V4_1=y
 
-CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
 
-CONFIG_ROOT_NFS=y
 
-CONFIG_NFSD=y
 
-CONFIG_NFSD_V3_ACL=y
 
-CONFIG_NFSD_V4=y
 
-CONFIG_NLS_CODEPAGE_437=y
 
-CONFIG_NLS_CODEPAGE_850=y
 
-CONFIG_NLS_CODEPAGE_852=y
 
-CONFIG_NLS_CODEPAGE_1250=y
 
-CONFIG_NLS_ASCII=y
 
-CONFIG_NLS_ISO8859_1=y
 
-CONFIG_NLS_ISO8859_2=y
 
-CONFIG_NLS_ISO8859_15=y
 
-CONFIG_NLS_UTF8=y
 
-CONFIG_MAGIC_SYSRQ=y
 
-CONFIG_STRIP_ASM_SYMS=y
 
-CONFIG_SECURITYFS=y
 
-CONFIG_CRYPTO_USER=y
 
-CONFIG_CRYPTO_NULL=y
 
-CONFIG_CRYPTO_CRYPTD=y
 
-CONFIG_CRYPTO_CCM=y
 
-CONFIG_CRYPTO_GCM=y
 
-CONFIG_CRYPTO_CTS=y
 
-CONFIG_CRYPTO_LRW=y
 
-CONFIG_CRYPTO_PCBC=y
 
-CONFIG_CRYPTO_XTS=y
 
-CONFIG_CRYPTO_XCBC=y
 
-CONFIG_CRYPTO_VMAC=y
 
-CONFIG_CRYPTO_MD4=y
 
-CONFIG_CRYPTO_MICHAEL_MIC=y
 
-CONFIG_CRYPTO_RMD128=y
 
-CONFIG_CRYPTO_RMD160=y
 
-CONFIG_CRYPTO_RMD256=y
 
-CONFIG_CRYPTO_RMD320=y
 
-CONFIG_CRYPTO_SHA256=y
 
-CONFIG_CRYPTO_SHA512=y
 
-CONFIG_CRYPTO_TGR192=y
 
-CONFIG_CRYPTO_WP512=y
 
-CONFIG_CRYPTO_ANUBIS=y
 
-CONFIG_CRYPTO_BLOWFISH=y
 
-CONFIG_CRYPTO_CAMELLIA=y
 
-CONFIG_CRYPTO_CAST5=y
 
-CONFIG_CRYPTO_CAST6=y
 
-CONFIG_CRYPTO_FCRYPT=y
 
-CONFIG_CRYPTO_KHAZAD=y
 
-CONFIG_CRYPTO_SALSA20=y
 
-CONFIG_CRYPTO_SEED=y
 
-CONFIG_CRYPTO_SERPENT=y
 
-CONFIG_CRYPTO_TEA=y
 
-CONFIG_CRYPTO_TWOFISH=y
 
-CONFIG_CRYPTO_ZLIB=y
 
-CONFIG_CRYPTO_LZO=y
 
-CONFIG_CRYPTO_USER_API_HASH=y
 
-CONFIG_CRYPTO_USER_API_SKCIPHER=y

+ 245 - 0
arch/mips/configs/db1xxx_defconfig
Vizualizați fișierul 

@@ -0,0 +1,245 @@
 
+CONFIG_MIPS_ALCHEMY=y
 
+CONFIG_MIPS_DB1XXX=y
 
+CONFIG_CMA=y
 
+CONFIG_CMA_DEBUG=y
 
+CONFIG_HZ_100=y
 
+CONFIG_LOCALVERSION="-db1xxx"
 
+CONFIG_KERNEL_XZ=y
 
+CONFIG_DEFAULT_HOSTNAME="db1xxx"
 
+CONFIG_SYSVIPC=y
 
+CONFIG_POSIX_MQUEUE=y
 
+CONFIG_FHANDLE=y
 
+CONFIG_AUDIT=y
 
+CONFIG_NO_HZ=y
 
+CONFIG_HIGH_RES_TIMERS=y
 
+CONFIG_LOG_BUF_SHIFT=16
 
+CONFIG_CGROUPS=y
 
+CONFIG_CGROUP_FREEZER=y
 
+CONFIG_CGROUP_DEVICE=y
 
+CONFIG_CPUSETS=y
 
+CONFIG_CGROUP_CPUACCT=y
 
+CONFIG_RESOURCE_COUNTERS=y
 
+CONFIG_MEMCG=y
 
+CONFIG_MEMCG_SWAP=y
 
+CONFIG_MEMCG_KMEM=y
 
+CONFIG_CGROUP_SCHED=y
 
+CONFIG_CFS_BANDWIDTH=y
 
+CONFIG_RT_GROUP_SCHED=y
 
+CONFIG_BLK_CGROUP=y
 
+CONFIG_KALLSYMS_ALL=y
 
+CONFIG_EMBEDDED=y
 
+CONFIG_SLAB=y
 
+CONFIG_BLK_DEV_BSGLIB=y
 
+CONFIG_PARTITION_ADVANCED=y
 
+CONFIG_DEFAULT_NOOP=y
 
+CONFIG_PCI=y
 
+CONFIG_PCI_REALLOC_ENABLE_AUTO=y
 
+CONFIG_PCCARD=y
 
+CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
 
+CONFIG_PM_RUNTIME=y
 
+CONFIG_NET=y
 
+CONFIG_PACKET=y
 
+CONFIG_PACKET_DIAG=y
 
+CONFIG_UNIX=y
 
+CONFIG_UNIX_DIAG=y
 
+CONFIG_XFRM_USER=y
 
+CONFIG_XFRM_SUB_POLICY=y
 
+CONFIG_XFRM_MIGRATE=y
 
+CONFIG_INET=y
 
+CONFIG_IP_MULTICAST=y
 
+CONFIG_IP_ADVANCED_ROUTER=y
 
+CONFIG_IP_FIB_TRIE_STATS=y
 
+CONFIG_NET_IPIP=y
 
+CONFIG_NET_IPGRE_DEMUX=y
 
+CONFIG_NET_IPGRE=y
 
+CONFIG_NET_IPGRE_BROADCAST=y
 
+CONFIG_SYN_COOKIES=y
 
+CONFIG_INET_AH=y
 
+CONFIG_INET_ESP=y
 
+CONFIG_INET_IPCOMP=y
 
+CONFIG_INET_UDP_DIAG=y
 
+CONFIG_TCP_CONG_ADVANCED=y
 
+CONFIG_TCP_CONG_VENO=y
 
+CONFIG_DEFAULT_VENO=y
 
+CONFIG_IPV6_ROUTER_PREF=y
 
+CONFIG_IPV6_ROUTE_INFO=y
 
+CONFIG_IPV6_OPTIMISTIC_DAD=y
 
+CONFIG_INET6_AH=y
 
+CONFIG_INET6_ESP=y
 
+CONFIG_INET6_IPCOMP=y
 
+CONFIG_IPV6_MIP6=y
 
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=y
 
+CONFIG_IPV6_VTI=y
 
+CONFIG_IPV6_SIT_6RD=y
 
+CONFIG_IPV6_GRE=y
 
+CONFIG_IPV6_MULTIPLE_TABLES=y
 
+CONFIG_IPV6_SUBTREES=y
 
+CONFIG_IPV6_MROUTE=y
 
+CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
 
+CONFIG_IPV6_PIMSM_V2=y
 
+CONFIG_BRIDGE=y
 
+CONFIG_NETLINK_MMAP=y
 
+CONFIG_NETLINK_DIAG=y
 
+CONFIG_IRDA=y
 
+CONFIG_IRLAN=y
 
+CONFIG_IRCOMM=y
 
+CONFIG_IRDA_ULTRA=y
 
+CONFIG_IRDA_CACHE_LAST_LSAP=y
 
+CONFIG_IRDA_FAST_RR=y
 
+CONFIG_AU1000_FIR=y
 
+CONFIG_BT=y
 
+CONFIG_BT_RFCOMM=y
 
+CONFIG_BT_RFCOMM_TTY=y
 
+CONFIG_BT_BNEP=y
 
+CONFIG_BT_BNEP_MC_FILTER=y
 
+CONFIG_BT_BNEP_PROTO_FILTER=y
 
+CONFIG_BT_HIDP=y
 
+CONFIG_BT_HCIBTUSB=y
 
+CONFIG_CFG80211=y
 
+CONFIG_CFG80211_WEXT=y
 
+CONFIG_MAC80211=y
 
+CONFIG_DEVTMPFS=y
 
+CONFIG_DEVTMPFS_MOUNT=y
 
+CONFIG_MTD=y
 
+CONFIG_MTD_CMDLINE_PARTS=y
 
+CONFIG_MTD_BLOCK=y
 
+CONFIG_MTD_CFI=y
 
+CONFIG_MTD_CFI_ADV_OPTIONS=y
 
+CONFIG_MTD_CFI_AMDSTD=y
 
+CONFIG_MTD_PHYSMAP=y
 
+CONFIG_MTD_M25P80=y
 
+CONFIG_MTD_SST25L=y
 
+CONFIG_MTD_NAND=y
 
+CONFIG_MTD_NAND_ECC_BCH=y
 
+CONFIG_MTD_NAND_AU1550=y
 
+CONFIG_MTD_NAND_PLATFORM=y
 
+CONFIG_EEPROM_AT24=y
 
+CONFIG_EEPROM_AT25=y
 
+CONFIG_SCSI_TGT=y
 
+CONFIG_BLK_DEV_SD=y
 
+CONFIG_CHR_DEV_SG=y
 
+CONFIG_SCSI_MULTI_LUN=y
 
+CONFIG_ATA=y
 
+CONFIG_PATA_HPT37X=y
 
+CONFIG_PATA_HPT3X2N=y
 
+CONFIG_PATA_PCMCIA=y
 
+CONFIG_PATA_PLATFORM=y
 
+CONFIG_NETDEVICES=y
 
+CONFIG_NLMON=y
 
+CONFIG_PCMCIA_3C589=y
 
+CONFIG_MIPS_AU1X00_ENET=y
 
+CONFIG_SMC91X=y
 
+CONFIG_SMSC911X=y
 
+CONFIG_AMD_PHY=y
 
+CONFIG_SMSC_PHY=y
 
+CONFIG_INPUT_EVDEV=y
 
+CONFIG_KEYBOARD_GPIO=y
 
+CONFIG_INPUT_TOUCHSCREEN=y
 
+CONFIG_TOUCHSCREEN_ADS7846=y
 
+CONFIG_TOUCHSCREEN_WM97XX=y
 
+CONFIG_INPUT_MISC=y
 
+CONFIG_INPUT_UINPUT=y
 
+CONFIG_SERIAL_8250=y
 
+CONFIG_SERIAL_8250_CONSOLE=y
 
+CONFIG_TTY_PRINTK=y
 
+CONFIG_I2C=y
 
+CONFIG_I2C_CHARDEV=y
 
+CONFIG_I2C_AU1550=y
 
+CONFIG_SPI=y
 
+CONFIG_SPI_AU1550=y
 
+CONFIG_SPI_GPIO=y
 
+CONFIG_SENSORS_ADM1025=y
 
+CONFIG_SENSORS_LM70=y
 
+CONFIG_FB=y
 
+CONFIG_FB_AU1100=y
 
+CONFIG_FB_AU1200=y
 
+CONFIG_FRAMEBUFFER_CONSOLE=y
 
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
 
+CONFIG_SOUND=y
 
+CONFIG_SND=y
 
+CONFIG_SND_SEQUENCER=y
 
+CONFIG_SND_HRTIMER=y
 
+CONFIG_SND_DYNAMIC_MINORS=y
 
+CONFIG_SND_AC97_POWER_SAVE=y
 
+CONFIG_SND_AC97_POWER_SAVE_DEFAULT=1
 
+CONFIG_SND_SOC=y
 
+CONFIG_SND_SOC_AU1XPSC=y
 
+CONFIG_SND_SOC_AU1XAUDIO=y
 
+CONFIG_SND_SOC_DB1000=y
 
+CONFIG_SND_SOC_DB1200=y
 
+CONFIG_HIDRAW=y
 
+CONFIG_UHID=y
 
+CONFIG_HID_LOGITECH=y
 
+CONFIG_HID_LOGITECH_DJ=y
 
+CONFIG_USB_HIDDEV=y
 
+CONFIG_USB=y
 
+CONFIG_USB_DYNAMIC_MINORS=y
 
+CONFIG_USB_OTG=y
 
+CONFIG_USB_EHCI_HCD=y
 
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
 
+CONFIG_USB_EHCI_HCD_PLATFORM=y
 
+CONFIG_USB_OHCI_HCD=y
 
+CONFIG_USB_OHCI_HCD_PLATFORM=y
 
+CONFIG_USB_STORAGE=y
 
+CONFIG_MMC=y
 
+CONFIG_MMC_CLKGATE=y
 
+CONFIG_SDIO_UART=y
 
+CONFIG_MMC_AU1X=y
 
+CONFIG_NEW_LEDS=y
 
+CONFIG_LEDS_CLASS=y
 
+CONFIG_LEDS_TRIGGERS=y
 
+CONFIG_RTC_CLASS=y
 
+CONFIG_RTC_DRV_AU1XXX=y
 
+CONFIG_FIRMWARE_MEMMAP=y
 
+CONFIG_EXT4_FS=y
 
+CONFIG_EXT4_FS_POSIX_ACL=y
 
+CONFIG_EXT4_FS_SECURITY=y
 
+CONFIG_XFS_FS=y
 
+CONFIG_XFS_POSIX_ACL=y
 
+CONFIG_FANOTIFY=y
 
+CONFIG_FUSE_FS=y
 
+CONFIG_CUSE=y
 
+CONFIG_VFAT_FS=y
 
+CONFIG_TMPFS=y
 
+CONFIG_TMPFS_POSIX_ACL=y
 
+CONFIG_CONFIGFS_FS=y
 
+CONFIG_JFFS2_FS=y
 
+CONFIG_JFFS2_SUMMARY=y
 
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
 
+CONFIG_JFFS2_LZO=y
 
+CONFIG_JFFS2_RUBIN=y
 
+CONFIG_SQUASHFS=y
 
+CONFIG_SQUASHFS_FILE_DIRECT=y
 
+CONFIG_SQUASHFS_XATTR=y
 
+CONFIG_SQUASHFS_LZO=y
 
+CONFIG_SQUASHFS_XZ=y
 
+CONFIG_F2FS_FS=y
 
+CONFIG_F2FS_FS_SECURITY=y
 
+CONFIG_NFS_FS=y
 
+CONFIG_NFS_V3_ACL=y
 
+CONFIG_NFS_V4=y
 
+CONFIG_NFS_V4_1=y
 
+CONFIG_NFS_V4_2=y
 
+CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="local"
 
+CONFIG_NFS_V4_1_MIGRATION=y
 
+CONFIG_NFSD=y
 
+CONFIG_NFSD_V3_ACL=y
 
+CONFIG_NFSD_V4=y
 
+CONFIG_NLS_CODEPAGE_437=y
 
+CONFIG_NLS_CODEPAGE_850=y
 
+CONFIG_NLS_CODEPAGE_852=y
 
+CONFIG_NLS_CODEPAGE_1250=y
 
+CONFIG_NLS_ASCII=y
 
+CONFIG_NLS_ISO8859_1=y
 
+CONFIG_NLS_ISO8859_2=y
 
+CONFIG_NLS_ISO8859_15=y
 
+CONFIG_NLS_UTF8=y
 
+CONFIG_MAGIC_SYSRQ=y
 
+CONFIG_SECURITYFS=y
 
+CONFIG_CRYPTO_USER=y
 
+CONFIG_CRYPTO_CRYPTD=y
 
+CONFIG_CRYPTO_USER_API_HASH=y
 
+CONFIG_CRYPTO_USER_API_SKCIPHER=y
 
+CONFIG_CRC32_SLICEBY4=y
 
+CONFIG_FONTS=y
 
+CONFIG_FONT_8x8=y

+ 362 - 0
arch/mips/configs/loongson3_defconfig
Vizualizați fișierul 

@@ -0,0 +1,362 @@
 
+CONFIG_MACH_LOONGSON=y
 
+CONFIG_SWIOTLB=y
 
+CONFIG_LEMOTE_MACH3A=y
 
+CONFIG_CPU_LOONGSON3=y
 
+CONFIG_64BIT=y
 
+CONFIG_PAGE_SIZE_16KB=y
 
+CONFIG_KSM=y
 
+CONFIG_SMP=y
 
+CONFIG_NR_CPUS=4
 
+CONFIG_HZ_256=y
 
+CONFIG_PREEMPT=y
 
+CONFIG_KEXEC=y
 
+# CONFIG_LOCALVERSION_AUTO is not set
 
+CONFIG_KERNEL_LZMA=y
 
+CONFIG_SYSVIPC=y
 
+CONFIG_POSIX_MQUEUE=y
 
+CONFIG_AUDIT=y
 
+CONFIG_NO_HZ=y
 
+CONFIG_HIGH_RES_TIMERS=y
 
+CONFIG_BSD_PROCESS_ACCT=y
 
+CONFIG_BSD_PROCESS_ACCT_V3=y
 
+CONFIG_TASKSTATS=y
 
+CONFIG_TASK_DELAY_ACCT=y
 
+CONFIG_TASK_XACCT=y
 
+CONFIG_TASK_IO_ACCOUNTING=y
 
+CONFIG_LOG_BUF_SHIFT=14
 
+CONFIG_CPUSETS=y
 
+CONFIG_RESOURCE_COUNTERS=y
 
+CONFIG_MEMCG=y
 
+CONFIG_MEMCG_SWAP=y
 
+CONFIG_BLK_CGROUP=y
 
+CONFIG_SCHED_AUTOGROUP=y
 
+CONFIG_SYSFS_DEPRECATED=y
 
+CONFIG_RELAY=y
 
+CONFIG_BLK_DEV_INITRD=y
 
+CONFIG_RD_BZIP2=y
 
+CONFIG_RD_LZMA=y
 
+CONFIG_SYSCTL_SYSCALL=y
 
+CONFIG_EMBEDDED=y
 
+CONFIG_MODULES=y
 
+CONFIG_MODULE_FORCE_LOAD=y
 
+CONFIG_MODULE_UNLOAD=y
 
+CONFIG_MODULE_FORCE_UNLOAD=y
 
+CONFIG_MODVERSIONS=y
 
+CONFIG_BLK_DEV_INTEGRITY=y
 
+CONFIG_PARTITION_ADVANCED=y
 
+CONFIG_IOSCHED_DEADLINE=m
 
+CONFIG_CFQ_GROUP_IOSCHED=y
 
+CONFIG_PCI=y
 
+CONFIG_HT_PCI=y
 
+CONFIG_PCIEPORTBUS=y
 
+CONFIG_HOTPLUG_PCI_PCIE=y
 
+# CONFIG_PCIEAER is not set
 
+CONFIG_PCIEASPM_PERFORMANCE=y
 
+CONFIG_HOTPLUG_PCI=y
 
+CONFIG_HOTPLUG_PCI_SHPC=m
 
+CONFIG_BINFMT_MISC=m
 
+CONFIG_MIPS32_COMPAT=y
 
+CONFIG_MIPS32_O32=y
 
+CONFIG_MIPS32_N32=y
 
+CONFIG_PM_RUNTIME=y
 
+CONFIG_PACKET=y
 
+CONFIG_UNIX=y
 
+CONFIG_XFRM_USER=y
 
+CONFIG_NET_KEY=y
 
+CONFIG_INET=y
 
+CONFIG_IP_MULTICAST=y
 
+CONFIG_IP_ADVANCED_ROUTER=y
 
+CONFIG_IP_MULTIPLE_TABLES=y
 
+CONFIG_IP_ROUTE_MULTIPATH=y
 
+CONFIG_IP_ROUTE_VERBOSE=y
 
+CONFIG_NETFILTER=y
 
+CONFIG_NETFILTER_NETLINK_LOG=m
 
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
 
+CONFIG_NETFILTER_XT_TARGET_MARK=m
 
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
 
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
 
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
 
+CONFIG_NETFILTER_XT_MATCH_ESP=m
 
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
 
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
 
+CONFIG_NETFILTER_XT_MATCH_MAC=m
 
+CONFIG_NETFILTER_XT_MATCH_MARK=m
 
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
 
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
 
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
 
+CONFIG_NETFILTER_XT_MATCH_REALM=m
 
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
 
+CONFIG_NETFILTER_XT_MATCH_STRING=m
 
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
 
+CONFIG_IP_VS=m
 
+CONFIG_IP_NF_IPTABLES=m
 
+CONFIG_IP_NF_MATCH_AH=m
 
+CONFIG_IP_NF_MATCH_ECN=m
 
+CONFIG_IP_NF_MATCH_TTL=m
 
+CONFIG_IP_NF_FILTER=m
 
+CONFIG_IP_NF_TARGET_REJECT=m
 
+CONFIG_IP_NF_TARGET_ULOG=m
 
+CONFIG_IP_NF_MANGLE=m
 
+CONFIG_IP_NF_TARGET_ECN=m
 
+CONFIG_IP_NF_TARGET_TTL=m
 
+CONFIG_IP_NF_RAW=m
 
+CONFIG_IP_NF_ARPTABLES=m
 
+CONFIG_IP_NF_ARPFILTER=m
 
+CONFIG_IP_NF_ARP_MANGLE=m
 
+CONFIG_IP_SCTP=m
 
+CONFIG_L2TP=m
 
+CONFIG_BRIDGE=m
 
+CONFIG_CFG80211=m
 
+CONFIG_CFG80211_WEXT=y
 
+CONFIG_MAC80211=m
 
+CONFIG_RFKILL=m
 
+CONFIG_RFKILL_INPUT=y
 
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 
+CONFIG_DEVTMPFS=y
 
+CONFIG_DEVTMPFS_MOUNT=y
 
+CONFIG_MTD=m
 
+CONFIG_BLK_DEV_LOOP=y
 
+CONFIG_BLK_DEV_CRYPTOLOOP=y
 
+CONFIG_BLK_DEV_RAM=y
 
+CONFIG_BLK_DEV_RAM_SIZE=8192
 
+CONFIG_RAID_ATTRS=m
 
+CONFIG_SCSI_TGT=y
 
+CONFIG_BLK_DEV_SD=y
 
+CONFIG_BLK_DEV_SR=y
 
+CONFIG_CHR_DEV_SG=y
 
+CONFIG_CHR_DEV_SCH=m
 
+CONFIG_SCSI_MULTI_LUN=y
 
+CONFIG_SCSI_CONSTANTS=y
 
+CONFIG_SCSI_LOGGING=y
 
+CONFIG_SCSI_SPI_ATTRS=m
 
+CONFIG_SCSI_FC_ATTRS=m
 
+CONFIG_ISCSI_TCP=m
 
+CONFIG_MEGARAID_NEWGEN=y
 
+CONFIG_MEGARAID_MM=y
 
+CONFIG_MEGARAID_MAILBOX=y
 
+CONFIG_MEGARAID_LEGACY=y
 
+CONFIG_MEGARAID_SAS=y
 
+CONFIG_ATA=y
 
+CONFIG_SATA_AHCI=y
 
+CONFIG_PATA_ATIIXP=y
 
+CONFIG_MD=y
 
+CONFIG_BLK_DEV_MD=m
 
+CONFIG_MD_LINEAR=m
 
+CONFIG_MD_RAID0=m
 
+CONFIG_MD_RAID1=m
 
+CONFIG_MD_RAID10=m
 
+CONFIG_MD_RAID456=m
 
+CONFIG_MD_MULTIPATH=m
 
+CONFIG_BLK_DEV_DM=m
 
+CONFIG_DM_CRYPT=m
 
+CONFIG_DM_SNAPSHOT=m
 
+CONFIG_DM_MIRROR=m
 
+CONFIG_DM_ZERO=m
 
+CONFIG_TARGET_CORE=m
 
+CONFIG_TCM_IBLOCK=m
 
+CONFIG_TCM_FILEIO=m
 
+CONFIG_TCM_PSCSI=m
 
+CONFIG_LOOPBACK_TARGET=m
 
+CONFIG_ISCSI_TARGET=m
 
+CONFIG_NETDEVICES=y
 
+CONFIG_TUN=m
 
+# CONFIG_NET_VENDOR_3COM is not set
 
+# CONFIG_NET_VENDOR_ADAPTEC is not set
 
+# CONFIG_NET_VENDOR_ALTEON is not set
 
+# CONFIG_NET_VENDOR_AMD is not set
 
+# CONFIG_NET_VENDOR_ARC is not set
 
+# CONFIG_NET_VENDOR_ATHEROS is not set
 
+# CONFIG_NET_CADENCE is not set
 
+# CONFIG_NET_VENDOR_BROADCOM is not set
 
+# CONFIG_NET_VENDOR_BROCADE is not set
 
+# CONFIG_NET_VENDOR_CHELSIO is not set
 
+# CONFIG_NET_VENDOR_CIRRUS is not set
 
+# CONFIG_NET_VENDOR_CISCO is not set
 
+# CONFIG_NET_VENDOR_DEC is not set
 
+# CONFIG_NET_VENDOR_DLINK is not set
 
+# CONFIG_NET_VENDOR_EMULEX is not set
 
+# CONFIG_NET_VENDOR_EXAR is not set
 
+# CONFIG_NET_VENDOR_HP is not set
 
+CONFIG_E1000=y
 
+CONFIG_E1000E=y
 
+CONFIG_IGB=y
 
+CONFIG_IXGB=y
 
+CONFIG_IXGBE=y
 
+# CONFIG_NET_VENDOR_I825XX is not set
 
+# CONFIG_NET_VENDOR_MARVELL is not set
 
+# CONFIG_NET_VENDOR_MELLANOX is not set
 
+# CONFIG_NET_VENDOR_MICREL is not set
 
+# CONFIG_NET_VENDOR_MYRI is not set
 
+# CONFIG_NET_VENDOR_NATSEMI is not set
 
+# CONFIG_NET_VENDOR_NVIDIA is not set
 
+# CONFIG_NET_VENDOR_OKI is not set
 
+# CONFIG_NET_PACKET_ENGINE is not set
 
+# CONFIG_NET_VENDOR_QLOGIC is not set
 
+CONFIG_8139CP=m
 
+CONFIG_8139TOO=m
 
+CONFIG_R8169=y
 
+# CONFIG_NET_VENDOR_RDC is not set
 
+# CONFIG_NET_VENDOR_SEEQ is not set
 
+# CONFIG_NET_VENDOR_SILAN is not set
 
+# CONFIG_NET_VENDOR_SIS is not set
 
+# CONFIG_NET_VENDOR_SMSC is not set
 
+# CONFIG_NET_VENDOR_STMICRO is not set
 
+# CONFIG_NET_VENDOR_SUN is not set
 
+# CONFIG_NET_VENDOR_TEHUTI is not set
 
+# CONFIG_NET_VENDOR_TI is not set
 
+# CONFIG_NET_VENDOR_TOSHIBA is not set
 
+# CONFIG_NET_VENDOR_VIA is not set
 
+# CONFIG_NET_VENDOR_WIZNET is not set
 
+CONFIG_PPP=m
 
+CONFIG_PPP_BSDCOMP=m
 
+CONFIG_PPP_DEFLATE=m
 
+CONFIG_PPP_FILTER=y
 
+CONFIG_PPP_MPPE=m
 
+CONFIG_PPP_MULTILINK=y
 
+CONFIG_PPPOE=m
 
+CONFIG_PPPOL2TP=m
 
+CONFIG_PPP_ASYNC=m
 
+CONFIG_PPP_SYNC_TTY=m
 
+CONFIG_ATH_CARDS=m
 
+CONFIG_ATH9K=m
 
+CONFIG_HOSTAP=m
 
+CONFIG_INPUT_POLLDEV=m
 
+CONFIG_INPUT_SPARSEKMAP=y
 
+CONFIG_INPUT_EVDEV=y
 
+CONFIG_KEYBOARD_XTKBD=m
 
+CONFIG_MOUSE_PS2_SENTELIC=y
 
+CONFIG_MOUSE_SERIAL=m
 
+CONFIG_INPUT_MISC=y
 
+CONFIG_INPUT_UINPUT=m
 
+CONFIG_SERIO_SERPORT=m
 
+CONFIG_SERIO_RAW=m
 
+CONFIG_LEGACY_PTY_COUNT=16
 
+CONFIG_SERIAL_NONSTANDARD=y
 
+CONFIG_SERIAL_8250=y
 
+CONFIG_SERIAL_8250_CONSOLE=y
 
+CONFIG_SERIAL_8250_NR_UARTS=16
 
+CONFIG_SERIAL_8250_EXTENDED=y
 
+CONFIG_SERIAL_8250_MANY_PORTS=y
 
+CONFIG_SERIAL_8250_SHARE_IRQ=y
 
+CONFIG_SERIAL_8250_RSA=y
 
+CONFIG_HW_RANDOM=y
 
+CONFIG_RAW_DRIVER=m
 
+CONFIG_I2C_CHARDEV=y
 
+CONFIG_I2C_PIIX4=y
 
+CONFIG_SENSORS_LM75=m
 
+CONFIG_SENSORS_LM93=m
 
+CONFIG_SENSORS_W83627HF=m
 
+CONFIG_MEDIA_SUPPORT=m
 
+CONFIG_MEDIA_CAMERA_SUPPORT=y
 
+CONFIG_MEDIA_USB_SUPPORT=y
 
+CONFIG_USB_VIDEO_CLASS=m
 
+CONFIG_DRM=y
 
+CONFIG_DRM_RADEON=y
 
+CONFIG_VIDEO_OUTPUT_CONTROL=y
 
+CONFIG_FB_RADEON=y
 
+CONFIG_LCD_CLASS_DEVICE=y
 
+CONFIG_LCD_PLATFORM=m
 
+CONFIG_BACKLIGHT_GENERIC=m
 
+# CONFIG_VGA_CONSOLE is not set
 
+CONFIG_FRAMEBUFFER_CONSOLE=y
 
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
 
+CONFIG_LOGO=y
 
+CONFIG_SOUND=y
 
+CONFIG_SND=m
 
+CONFIG_SND_SEQUENCER=m
 
+CONFIG_SND_SEQ_DUMMY=m
 
+# CONFIG_SND_ISA is not set
 
+CONFIG_SND_HDA_INTEL=m
 
+CONFIG_SND_HDA_PATCH_LOADER=y
 
+CONFIG_SND_HDA_CODEC_REALTEK=m
 
+CONFIG_SND_HDA_CODEC_CONEXANT=m
 
+# CONFIG_SND_USB is not set
 
+CONFIG_HID_A4TECH=m
 
+CONFIG_HID_SUNPLUS=m
 
+CONFIG_USB=y
 
+CONFIG_USB_MON=y
 
+CONFIG_USB_XHCI_HCD=m
 
+CONFIG_USB_EHCI_HCD=y
 
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
 
+CONFIG_USB_OHCI_HCD=y
 
+CONFIG_USB_UHCI_HCD=m
 
+CONFIG_USB_STORAGE=m
 
+CONFIG_USB_SERIAL=m
 
+CONFIG_USB_SERIAL_OPTION=m
 
+CONFIG_RTC_CLASS=y
 
+CONFIG_RTC_DRV_CMOS=y
 
+CONFIG_DMADEVICES=y
 
+CONFIG_PM_DEVFREQ=y
 
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
 
+CONFIG_DEVFREQ_GOV_PERFORMANCE=y
 
+CONFIG_DEVFREQ_GOV_POWERSAVE=y
 
+CONFIG_DEVFREQ_GOV_USERSPACE=y
 
+CONFIG_EXT2_FS=y
 
+CONFIG_EXT2_FS_XATTR=y
 
+CONFIG_EXT2_FS_POSIX_ACL=y
 
+CONFIG_EXT2_FS_SECURITY=y
 
+CONFIG_EXT3_FS=y
 
+CONFIG_EXT3_FS_POSIX_ACL=y
 
+CONFIG_EXT3_FS_SECURITY=y
 
+CONFIG_EXT4_FS=y
 
+CONFIG_EXT4_FS_POSIX_ACL=y
 
+CONFIG_EXT4_FS_SECURITY=y
 
+CONFIG_QUOTA=y
 
+# CONFIG_PRINT_QUOTA_WARNING is not set
 
+CONFIG_AUTOFS4_FS=y
 
+CONFIG_FUSE_FS=m
 
+CONFIG_ISO9660_FS=m
 
+CONFIG_JOLIET=y
 
+CONFIG_MSDOS_FS=m
 
+CONFIG_VFAT_FS=m
 
+CONFIG_FAT_DEFAULT_CODEPAGE=936
 
+CONFIG_FAT_DEFAULT_IOCHARSET="gb2312"
 
+CONFIG_PROC_KCORE=y
 
+CONFIG_TMPFS=y
 
+CONFIG_TMPFS_POSIX_ACL=y
 
+CONFIG_CONFIGFS_FS=y
 
+CONFIG_CRAMFS=m
 
+CONFIG_SQUASHFS=y
 
+CONFIG_SQUASHFS_XATTR=y
 
+CONFIG_NFS_FS=m
 
+CONFIG_NFS_V3_ACL=y
 
+CONFIG_NFS_V4=m
 
+CONFIG_NFSD=m
 
+CONFIG_NFSD_V3_ACL=y
 
+CONFIG_NFSD_V4=y
 
+CONFIG_CIFS=m
 
+CONFIG_NLS_CODEPAGE_437=y
 
+CONFIG_NLS_CODEPAGE_936=y
 
+CONFIG_NLS_ASCII=y
 
+CONFIG_NLS_UTF8=y
 
+CONFIG_PRINTK_TIME=y
 
+CONFIG_FRAME_WARN=1024
 
+CONFIG_STRIP_ASM_SYMS=y
 
+CONFIG_MAGIC_SYSRQ=y
 
+# CONFIG_SCHED_DEBUG is not set
 
+# CONFIG_DEBUG_PREEMPT is not set
 
+# CONFIG_RCU_CPU_STALL_VERBOSE is not set
 
+# CONFIG_FTRACE is not set
 
+CONFIG_SECURITY=y
 
+CONFIG_SECURITYFS=y
 
+CONFIG_SECURITY_NETWORK=y
 
+CONFIG_SECURITY_PATH=y
 
+CONFIG_SECURITY_SELINUX=y
 
+CONFIG_SECURITY_SELINUX_BOOTPARAM=y
 
+CONFIG_SECURITY_SELINUX_DISABLE=y
 
+CONFIG_DEFAULT_SECURITY_DAC=y
 
+CONFIG_CRYPTO_AUTHENC=m
 
+CONFIG_CRYPTO_HMAC=y
 
+CONFIG_CRYPTO_MD5=y
 
+CONFIG_CRYPTO_SHA512=m
 
+CONFIG_CRYPTO_TGR192=m
 
+CONFIG_CRYPTO_WP512=m
 
+CONFIG_CRYPTO_ANUBIS=m
 
+CONFIG_CRYPTO_BLOWFISH=m
 
+CONFIG_CRYPTO_CAST5=m
 
+CONFIG_CRYPTO_CAST6=m
 
+CONFIG_CRYPTO_KHAZAD=m
 
+CONFIG_CRYPTO_SERPENT=m
 
+CONFIG_CRYPTO_TEA=m
 
+CONFIG_CRYPTO_TWOFISH=m
 
+CONFIG_CRYPTO_DEFLATE=m

+ 3 - 6
arch/mips/configs/malta_defconfig
Vizualizați fișierul 

@@ -1,7 +1,9 @@
 
 CONFIG_MIPS_MALTA=y
 
 CONFIG_MIPS_MALTA=y
 
 CONFIG_CPU_LITTLE_ENDIAN=y
 
 CONFIG_CPU_LITTLE_ENDIAN=y
 
 CONFIG_CPU_MIPS32_R2=y
 
 CONFIG_CPU_MIPS32_R2=y
 
+CONFIG_PAGE_SIZE_16KB=y
 
 CONFIG_MIPS_MT_SMP=y
 
 CONFIG_MIPS_MT_SMP=y
 
+CONFIG_NR_CPUS=8
 
 CONFIG_HZ_100=y
 
 CONFIG_HZ_100=y
 
 CONFIG_SYSVIPC=y
 
 CONFIG_SYSVIPC=y
 
 CONFIG_NO_HZ=y
 
 CONFIG_NO_HZ=y
 
@@ -42,7 +44,6 @@ CONFIG_INET_IPCOMP=m
 
 CONFIG_INET_XFRM_MODE_TRANSPORT=m
 
 CONFIG_INET_XFRM_MODE_TRANSPORT=m
 
 CONFIG_INET_XFRM_MODE_TUNNEL=m
 
 CONFIG_INET_XFRM_MODE_TUNNEL=m
 
 CONFIG_TCP_MD5SIG=y
 
 CONFIG_TCP_MD5SIG=y
 
-CONFIG_IPV6_PRIVACY=y
 
 CONFIG_IPV6_ROUTER_PREF=y
 
 CONFIG_IPV6_ROUTER_PREF=y
 
 CONFIG_IPV6_ROUTE_INFO=y
 
 CONFIG_IPV6_ROUTE_INFO=y
 
 CONFIG_IPV6_OPTIMISTIC_DAD=y
 
 CONFIG_IPV6_OPTIMISTIC_DAD=y
 
@@ -68,7 +69,6 @@ CONFIG_NF_CONNTRACK_SANE=m
 
 CONFIG_NF_CONNTRACK_SIP=m
 
 CONFIG_NF_CONNTRACK_SIP=m
 
 CONFIG_NF_CONNTRACK_TFTP=m
 
 CONFIG_NF_CONNTRACK_TFTP=m
 
 CONFIG_NF_CT_NETLINK=m
 
 CONFIG_NF_CT_NETLINK=m
 
-CONFIG_NETFILTER_TPROXY=m
 
 CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
 
 CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
 
 CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
 
 CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
 
 CONFIG_NETFILTER_XT_TARGET_MARK=m
 
 CONFIG_NETFILTER_XT_TARGET_MARK=m
 
@@ -125,7 +125,6 @@ CONFIG_IP_VS_SH=m
 
 CONFIG_IP_VS_SED=m
 
 CONFIG_IP_VS_SED=m
 
 CONFIG_IP_VS_NQ=m
 
 CONFIG_IP_VS_NQ=m
 
 CONFIG_NF_CONNTRACK_IPV4=m
 
 CONFIG_NF_CONNTRACK_IPV4=m
 
-CONFIG_IP_NF_QUEUE=m
 
 CONFIG_IP_NF_IPTABLES=m
 
 CONFIG_IP_NF_IPTABLES=m
 
 CONFIG_IP_NF_MATCH_AH=m
 
 CONFIG_IP_NF_MATCH_AH=m
 
 CONFIG_IP_NF_MATCH_ECN=m
 
 CONFIG_IP_NF_MATCH_ECN=m
 
@@ -185,7 +184,6 @@ CONFIG_ATALK=m
 
 CONFIG_DEV_APPLETALK=m
 
 CONFIG_DEV_APPLETALK=m
 
 CONFIG_IPDDP=m
 
 CONFIG_IPDDP=m
 
 CONFIG_IPDDP_ENCAP=y
 
 CONFIG_IPDDP_ENCAP=y
 
-CONFIG_IPDDP_DECAP=y
 
 CONFIG_PHONET=m
 
 CONFIG_PHONET=m
 
 CONFIG_NET_SCHED=y
 
 CONFIG_NET_SCHED=y
 
 CONFIG_NET_SCH_CBQ=m
 
 CONFIG_NET_SCH_CBQ=m
 
@@ -226,9 +224,9 @@ CONFIG_MAC80211_RC_DEFAULT_PID=y
 
 CONFIG_MAC80211_MESH=y
 
 CONFIG_MAC80211_MESH=y
 
 CONFIG_RFKILL=m
 
 CONFIG_RFKILL=m
 
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 
+CONFIG_DEVTMPFS=y
 
 CONFIG_CONNECTOR=m
 
 CONFIG_CONNECTOR=m
 
 CONFIG_MTD=y
 
 CONFIG_MTD=y
 
-CONFIG_MTD_CHAR=y
 
 CONFIG_MTD_BLOCK=y
 
 CONFIG_MTD_BLOCK=y
 
 CONFIG_MTD_OOPS=m
 
 CONFIG_MTD_OOPS=m
 
 CONFIG_MTD_CFI=y
 
 CONFIG_MTD_CFI=y
 
@@ -328,7 +326,6 @@ CONFIG_LIBERTAS=m
 
 # CONFIG_INPUT_KEYBOARD is not set
 
 # CONFIG_INPUT_KEYBOARD is not set
 
 # CONFIG_INPUT_MOUSE is not set
 
 # CONFIG_INPUT_MOUSE is not set
 
 # CONFIG_SERIO_I8042 is not set
 
 # CONFIG_SERIO_I8042 is not set
 
-CONFIG_VT_HW_CONSOLE_BINDING=y
 
 CONFIG_SERIAL_8250=y
 
 CONFIG_SERIAL_8250=y
 
 CONFIG_SERIAL_8250_CONSOLE=y
 
 CONFIG_SERIAL_8250_CONSOLE=y
 
 # CONFIG_HWMON is not set
 
 # CONFIG_HWMON is not set

+ 3 - 7
arch/mips/configs/malta_kvm_defconfig
Vizualizați fișierul 

@@ -3,6 +3,7 @@ CONFIG_CPU_LITTLE_ENDIAN=y
 
 CONFIG_CPU_MIPS32_R2=y
 
 CONFIG_CPU_MIPS32_R2=y
 
 CONFIG_PAGE_SIZE_16KB=y
 
 CONFIG_PAGE_SIZE_16KB=y
 
 CONFIG_MIPS_MT_SMP=y
 
 CONFIG_MIPS_MT_SMP=y
 
+CONFIG_NR_CPUS=8
 
 CONFIG_HZ_100=y
 
 CONFIG_HZ_100=y
 
 CONFIG_SYSVIPC=y
 
 CONFIG_SYSVIPC=y
 
 CONFIG_NO_HZ=y
 
 CONFIG_NO_HZ=y
 
@@ -44,7 +45,6 @@ CONFIG_INET_IPCOMP=m
 
 CONFIG_INET_XFRM_MODE_TRANSPORT=m
 
 CONFIG_INET_XFRM_MODE_TRANSPORT=m
 
 CONFIG_INET_XFRM_MODE_TUNNEL=m
 
 CONFIG_INET_XFRM_MODE_TUNNEL=m
 
 CONFIG_TCP_MD5SIG=y
 
 CONFIG_TCP_MD5SIG=y
 
-CONFIG_IPV6_PRIVACY=y
 
 CONFIG_IPV6_ROUTER_PREF=y
 
 CONFIG_IPV6_ROUTER_PREF=y
 
 CONFIG_IPV6_ROUTE_INFO=y
 
 CONFIG_IPV6_ROUTE_INFO=y
 
 CONFIG_IPV6_OPTIMISTIC_DAD=y
 
 CONFIG_IPV6_OPTIMISTIC_DAD=y
 
@@ -70,7 +70,6 @@ CONFIG_NF_CONNTRACK_SANE=m
 
 CONFIG_NF_CONNTRACK_SIP=m
 
 CONFIG_NF_CONNTRACK_SIP=m
 
 CONFIG_NF_CONNTRACK_TFTP=m
 
 CONFIG_NF_CONNTRACK_TFTP=m
 
 CONFIG_NF_CT_NETLINK=m
 
 CONFIG_NF_CT_NETLINK=m
 
-CONFIG_NETFILTER_TPROXY=m
 
 CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
 
 CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
 
 CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
 
 CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
 
 CONFIG_NETFILTER_XT_TARGET_MARK=m
 
 CONFIG_NETFILTER_XT_TARGET_MARK=m
 
@@ -127,7 +126,6 @@ CONFIG_IP_VS_SH=m
 
 CONFIG_IP_VS_SED=m
 
 CONFIG_IP_VS_SED=m
 
 CONFIG_IP_VS_NQ=m
 
 CONFIG_IP_VS_NQ=m
 
 CONFIG_NF_CONNTRACK_IPV4=m
 
 CONFIG_NF_CONNTRACK_IPV4=m
 
-CONFIG_IP_NF_QUEUE=m
 
 CONFIG_IP_NF_IPTABLES=m
 
 CONFIG_IP_NF_IPTABLES=m
 
 CONFIG_IP_NF_MATCH_AH=m
 
 CONFIG_IP_NF_MATCH_AH=m
 
 CONFIG_IP_NF_MATCH_ECN=m
 
 CONFIG_IP_NF_MATCH_ECN=m
 
@@ -187,7 +185,6 @@ CONFIG_ATALK=m
 
 CONFIG_DEV_APPLETALK=m
 
 CONFIG_DEV_APPLETALK=m
 
 CONFIG_IPDDP=m
 
 CONFIG_IPDDP=m
 
 CONFIG_IPDDP_ENCAP=y
 
 CONFIG_IPDDP_ENCAP=y
 
-CONFIG_IPDDP_DECAP=y
 
 CONFIG_PHONET=m
 
 CONFIG_PHONET=m
 
 CONFIG_NET_SCHED=y
 
 CONFIG_NET_SCHED=y
 
 CONFIG_NET_SCH_CBQ=m
 
 CONFIG_NET_SCH_CBQ=m
 
@@ -228,9 +225,9 @@ CONFIG_MAC80211_RC_DEFAULT_PID=y
 
 CONFIG_MAC80211_MESH=y
 
 CONFIG_MAC80211_MESH=y
 
 CONFIG_RFKILL=m
 
 CONFIG_RFKILL=m
 
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 
+CONFIG_DEVTMPFS=y
 
 CONFIG_CONNECTOR=m
 
 CONFIG_CONNECTOR=m
 
 CONFIG_MTD=y
 
 CONFIG_MTD=y
 
-CONFIG_MTD_CHAR=y
 
 CONFIG_MTD_BLOCK=y
 
 CONFIG_MTD_BLOCK=y
 
 CONFIG_MTD_OOPS=m
 
 CONFIG_MTD_OOPS=m
 
 CONFIG_MTD_CFI=y
 
 CONFIG_MTD_CFI=y
 
@@ -300,6 +297,7 @@ CONFIG_IFB=m
 
 CONFIG_MACVLAN=m
 
 CONFIG_MACVLAN=m
 
 CONFIG_TUN=m
 
 CONFIG_TUN=m
 
 CONFIG_VETH=m
 
 CONFIG_VETH=m
 
+CONFIG_VHOST_NET=m
 
 CONFIG_PCNET32=y
 
 CONFIG_PCNET32=y
 
 CONFIG_CHELSIO_T3=m
 
 CONFIG_CHELSIO_T3=m
 
 CONFIG_AX88796=m
 
 CONFIG_AX88796=m
 
@@ -329,7 +327,6 @@ CONFIG_LIBERTAS=m
 
 # CONFIG_INPUT_KEYBOARD is not set
 
 # CONFIG_INPUT_KEYBOARD is not set
 
 # CONFIG_INPUT_MOUSE is not set
 
 # CONFIG_INPUT_MOUSE is not set
 
 # CONFIG_SERIO_I8042 is not set
 
 # CONFIG_SERIO_I8042 is not set
 
-CONFIG_VT_HW_CONSOLE_BINDING=y
 
 CONFIG_SERIAL_8250=y
 
 CONFIG_SERIAL_8250=y
 
 CONFIG_SERIAL_8250_CONSOLE=y
 
 CONFIG_SERIAL_8250_CONSOLE=y
 
 # CONFIG_HWMON is not set
 
 # CONFIG_HWMON is not set
 
@@ -453,4 +450,3 @@ CONFIG_VIRTUALIZATION=y
 
 CONFIG_KVM=m
 
 CONFIG_KVM=m
 
 CONFIG_KVM_MIPS_DYN_TRANS=y
 
 CONFIG_KVM_MIPS_DYN_TRANS=y
 
 CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS=y
 
 CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS=y
 
-CONFIG_VHOST_NET=m

+ 1 - 6
arch/mips/configs/malta_kvm_guest_defconfig
Vizualizați fișierul 

@@ -44,7 +44,6 @@ CONFIG_INET_IPCOMP=m
 
 CONFIG_INET_XFRM_MODE_TRANSPORT=m
 
 CONFIG_INET_XFRM_MODE_TRANSPORT=m
 
 CONFIG_INET_XFRM_MODE_TUNNEL=m
 
 CONFIG_INET_XFRM_MODE_TUNNEL=m
 
 CONFIG_TCP_MD5SIG=y
 
 CONFIG_TCP_MD5SIG=y
 
-CONFIG_IPV6_PRIVACY=y
 
 CONFIG_IPV6_ROUTER_PREF=y
 
 CONFIG_IPV6_ROUTER_PREF=y
 
 CONFIG_IPV6_ROUTE_INFO=y
 
 CONFIG_IPV6_ROUTE_INFO=y
 
 CONFIG_IPV6_OPTIMISTIC_DAD=y
 
 CONFIG_IPV6_OPTIMISTIC_DAD=y
 
@@ -70,7 +69,6 @@ CONFIG_NF_CONNTRACK_SANE=m
 
 CONFIG_NF_CONNTRACK_SIP=m
 
 CONFIG_NF_CONNTRACK_SIP=m
 
 CONFIG_NF_CONNTRACK_TFTP=m
 
 CONFIG_NF_CONNTRACK_TFTP=m
 
 CONFIG_NF_CT_NETLINK=m
 
 CONFIG_NF_CT_NETLINK=m
 
-CONFIG_NETFILTER_TPROXY=m
 
 CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
 
 CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
 
 CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
 
 CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
 
 CONFIG_NETFILTER_XT_TARGET_MARK=m
 
 CONFIG_NETFILTER_XT_TARGET_MARK=m
 
@@ -127,7 +125,6 @@ CONFIG_IP_VS_SH=m
 
 CONFIG_IP_VS_SED=m
 
 CONFIG_IP_VS_SED=m
 
 CONFIG_IP_VS_NQ=m
 
 CONFIG_IP_VS_NQ=m
 
 CONFIG_NF_CONNTRACK_IPV4=m
 
 CONFIG_NF_CONNTRACK_IPV4=m
 
-CONFIG_IP_NF_QUEUE=m
 
 CONFIG_IP_NF_IPTABLES=m
 
 CONFIG_IP_NF_IPTABLES=m
 
 CONFIG_IP_NF_MATCH_AH=m
 
 CONFIG_IP_NF_MATCH_AH=m
 
 CONFIG_IP_NF_MATCH_ECN=m
 
 CONFIG_IP_NF_MATCH_ECN=m
 
@@ -187,7 +184,6 @@ CONFIG_ATALK=m
 
 CONFIG_DEV_APPLETALK=m
 
 CONFIG_DEV_APPLETALK=m
 
 CONFIG_IPDDP=m
 
 CONFIG_IPDDP=m
 
 CONFIG_IPDDP_ENCAP=y
 
 CONFIG_IPDDP_ENCAP=y
 
-CONFIG_IPDDP_DECAP=y
 
 CONFIG_PHONET=m
 
 CONFIG_PHONET=m
 
 CONFIG_NET_SCHED=y
 
 CONFIG_NET_SCHED=y
 
 CONFIG_NET_SCH_CBQ=m
 
 CONFIG_NET_SCH_CBQ=m
 
@@ -228,9 +224,9 @@ CONFIG_MAC80211_RC_DEFAULT_PID=y
 
 CONFIG_MAC80211_MESH=y
 
 CONFIG_MAC80211_MESH=y
 
 CONFIG_RFKILL=m
 
 CONFIG_RFKILL=m
 
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 
+CONFIG_DEVTMPFS=y
 
 CONFIG_CONNECTOR=m
 
 CONFIG_CONNECTOR=m
 
 CONFIG_MTD=y
 
 CONFIG_MTD=y
 
-CONFIG_MTD_CHAR=y
 
 CONFIG_MTD_BLOCK=y
 
 CONFIG_MTD_BLOCK=y
 
 CONFIG_MTD_OOPS=m
 
 CONFIG_MTD_OOPS=m
 
 CONFIG_MTD_CFI=y
 
 CONFIG_MTD_CFI=y
 
@@ -331,7 +327,6 @@ CONFIG_LIBERTAS=m
 
 # CONFIG_INPUT_KEYBOARD is not set
 
 # CONFIG_INPUT_KEYBOARD is not set
 
 # CONFIG_INPUT_MOUSE is not set
 
 # CONFIG_INPUT_MOUSE is not set
 
 # CONFIG_SERIO_I8042 is not set
 
 # CONFIG_SERIO_I8042 is not set
 
-CONFIG_VT_HW_CONSOLE_BINDING=y
 
 CONFIG_SERIAL_8250=y
 
 CONFIG_SERIAL_8250=y
 
 CONFIG_SERIAL_8250_CONSOLE=y
 
 CONFIG_SERIAL_8250_CONSOLE=y
 
 # CONFIG_HWMON is not set
 
 # CONFIG_HWMON is not set

+ 1 - 2
arch/mips/configs/maltaaprp_defconfig
Vizualizați fișierul 

@@ -44,7 +44,6 @@ CONFIG_INET_AH=m
 
 CONFIG_INET_ESP=m
 
 CONFIG_INET_ESP=m
 
 CONFIG_INET_IPCOMP=m
 
 CONFIG_INET_IPCOMP=m
 
 # CONFIG_INET_LRO is not set
 
 # CONFIG_INET_LRO is not set
 
-CONFIG_IPV6_PRIVACY=y
 
 CONFIG_INET6_AH=m
 
 CONFIG_INET6_AH=m
 
 CONFIG_INET6_ESP=m
 
 CONFIG_INET6_ESP=m
 
 CONFIG_INET6_IPCOMP=m
 
 CONFIG_INET6_IPCOMP=m
 
@@ -55,7 +54,6 @@ CONFIG_ATALK=m
 
 CONFIG_DEV_APPLETALK=m
 
 CONFIG_DEV_APPLETALK=m
 
 CONFIG_IPDDP=m
 
 CONFIG_IPDDP=m
 
 CONFIG_IPDDP_ENCAP=y
 
 CONFIG_IPDDP_ENCAP=y
 
-CONFIG_IPDDP_DECAP=y
 
 CONFIG_NET_SCHED=y
 
 CONFIG_NET_SCHED=y
 
 CONFIG_NET_SCH_CBQ=m
 
 CONFIG_NET_SCH_CBQ=m
 
 CONFIG_NET_SCH_HTB=m
 
 CONFIG_NET_SCH_HTB=m
 
@@ -80,6 +78,7 @@ CONFIG_NET_CLS_ACT=y
 
 CONFIG_NET_ACT_POLICE=y
 
 CONFIG_NET_ACT_POLICE=y
 
 CONFIG_NET_CLS_IND=y
 
 CONFIG_NET_CLS_IND=y
 
 # CONFIG_WIRELESS is not set
 
 # CONFIG_WIRELESS is not set
 
+CONFIG_DEVTMPFS=y
 
 CONFIG_BLK_DEV_LOOP=y
 
 CONFIG_BLK_DEV_LOOP=y
 
 CONFIG_BLK_DEV_CRYPTOLOOP=m
 
 CONFIG_BLK_DEV_CRYPTOLOOP=m
 
 CONFIG_IDE=y
 
 CONFIG_IDE=y

+ 2 - 2
arch/mips/configs/maltasmtc_defconfig
Vizualizați fișierul 

@@ -1,6 +1,7 @@
 
 CONFIG_MIPS_MALTA=y
 
 CONFIG_MIPS_MALTA=y
 
 CONFIG_CPU_LITTLE_ENDIAN=y
 
 CONFIG_CPU_LITTLE_ENDIAN=y
 
 CONFIG_CPU_MIPS32_R2=y
 
 CONFIG_CPU_MIPS32_R2=y
 
+CONFIG_PAGE_SIZE_16KB=y
 
 CONFIG_MIPS_MT_SMTC=y
 
 CONFIG_MIPS_MT_SMTC=y
 
 # CONFIG_MIPS_MT_FPAFF is not set
 
 # CONFIG_MIPS_MT_FPAFF is not set
 
 CONFIG_NR_CPUS=9
 
 CONFIG_NR_CPUS=9
 
@@ -45,7 +46,6 @@ CONFIG_INET_AH=m
 
 CONFIG_INET_ESP=m
 
 CONFIG_INET_ESP=m
 
 CONFIG_INET_IPCOMP=m
 
 CONFIG_INET_IPCOMP=m
 
 # CONFIG_INET_LRO is not set
 
 # CONFIG_INET_LRO is not set
 
-CONFIG_IPV6_PRIVACY=y
 
 CONFIG_INET6_AH=m
 
 CONFIG_INET6_AH=m
 
 CONFIG_INET6_ESP=m
 
 CONFIG_INET6_ESP=m
 
 CONFIG_INET6_IPCOMP=m
 
 CONFIG_INET6_IPCOMP=m
 
@@ -56,7 +56,6 @@ CONFIG_ATALK=m
 
 CONFIG_DEV_APPLETALK=m
 
 CONFIG_DEV_APPLETALK=m
 
 CONFIG_IPDDP=m
 
 CONFIG_IPDDP=m
 
 CONFIG_IPDDP_ENCAP=y
 
 CONFIG_IPDDP_ENCAP=y
 
-CONFIG_IPDDP_DECAP=y
 
 CONFIG_NET_SCHED=y
 
 CONFIG_NET_SCHED=y
 
 CONFIG_NET_SCH_CBQ=m
 
 CONFIG_NET_SCH_CBQ=m
 
 CONFIG_NET_SCH_HTB=m
 
 CONFIG_NET_SCH_HTB=m
 
@@ -81,6 +80,7 @@ CONFIG_NET_CLS_ACT=y
 
 CONFIG_NET_ACT_POLICE=y
 
 CONFIG_NET_ACT_POLICE=y
 
 CONFIG_NET_CLS_IND=y
 
 CONFIG_NET_CLS_IND=y
 
 # CONFIG_WIRELESS is not set
 
 # CONFIG_WIRELESS is not set
 
+CONFIG_DEVTMPFS=y
 
 CONFIG_BLK_DEV_LOOP=y
 
 CONFIG_BLK_DEV_LOOP=y
 
 CONFIG_BLK_DEV_CRYPTOLOOP=m
 
 CONFIG_BLK_DEV_CRYPTOLOOP=m
 
 CONFIG_IDE=y
 
 CONFIG_IDE=y

+ 3 - 2
arch/mips/configs/maltasmvp_defconfig
Vizualizați fișierul 

@@ -1,10 +1,11 @@
 
 CONFIG_MIPS_MALTA=y
 
 CONFIG_MIPS_MALTA=y
 
 CONFIG_CPU_LITTLE_ENDIAN=y
 
 CONFIG_CPU_LITTLE_ENDIAN=y
 
 CONFIG_CPU_MIPS32_R2=y
 
 CONFIG_CPU_MIPS32_R2=y
 
+CONFIG_PAGE_SIZE_16KB=y
 
 CONFIG_MIPS_MT_SMP=y
 
 CONFIG_MIPS_MT_SMP=y
 
 CONFIG_SCHED_SMT=y
 
 CONFIG_SCHED_SMT=y
 
 CONFIG_MIPS_CMP=y
 
 CONFIG_MIPS_CMP=y
 
-CONFIG_NR_CPUS=2
 
+CONFIG_NR_CPUS=8
 
 CONFIG_HZ_100=y
 
 CONFIG_HZ_100=y
 
 CONFIG_LOCALVERSION="cmp"
 
 CONFIG_LOCALVERSION="cmp"
 
 CONFIG_SYSVIPC=y
 
 CONFIG_SYSVIPC=y
 
@@ -47,7 +48,6 @@ CONFIG_INET_AH=m
 
 CONFIG_INET_ESP=m
 
 CONFIG_INET_ESP=m
 
 CONFIG_INET_IPCOMP=m
 
 CONFIG_INET_IPCOMP=m
 
 # CONFIG_INET_LRO is not set
 
 # CONFIG_INET_LRO is not set
 
-CONFIG_IPV6_PRIVACY=y
 
 CONFIG_INET6_AH=m
 
 CONFIG_INET6_AH=m
 
 CONFIG_INET6_ESP=m
 
 CONFIG_INET6_ESP=m
 
 CONFIG_INET6_IPCOMP=m
 
 CONFIG_INET6_IPCOMP=m
 
@@ -82,6 +82,7 @@ CONFIG_NET_CLS_ACT=y
 
 CONFIG_NET_ACT_POLICE=y
 
 CONFIG_NET_ACT_POLICE=y
 
 CONFIG_NET_CLS_IND=y
 
 CONFIG_NET_CLS_IND=y
 
 # CONFIG_WIRELESS is not set
 
 # CONFIG_WIRELESS is not set
 
+CONFIG_DEVTMPFS=y
 
 CONFIG_BLK_DEV_LOOP=y
 
 CONFIG_BLK_DEV_LOOP=y
 
 CONFIG_BLK_DEV_CRYPTOLOOP=m
 
 CONFIG_BLK_DEV_CRYPTOLOOP=m
 
 CONFIG_IDE=y
 
 CONFIG_IDE=y

+ 200 - 0
arch/mips/configs/maltasmvp_eva_defconfig
Vizualizați fișierul 

@@ -0,0 +1,200 @@
 
+CONFIG_MIPS_MALTA=y
 
+CONFIG_CPU_LITTLE_ENDIAN=y
 
+CONFIG_CPU_MIPS32_R2=y
 
+CONFIG_CPU_MIPS32_3_5_FEATURES=y
 
+CONFIG_PAGE_SIZE_16KB=y
 
+CONFIG_MIPS_MT_SMP=y
 
+CONFIG_SCHED_SMT=y
 
+CONFIG_MIPS_CMP=y
 
+CONFIG_NR_CPUS=8
 
+CONFIG_HZ_100=y
 
+CONFIG_LOCALVERSION="cmp"
 
+CONFIG_SYSVIPC=y
 
+CONFIG_POSIX_MQUEUE=y
 
+CONFIG_AUDIT=y
 
+CONFIG_NO_HZ=y
 
+CONFIG_IKCONFIG=y
 
+CONFIG_IKCONFIG_PROC=y
 
+CONFIG_LOG_BUF_SHIFT=15
 
+CONFIG_SYSCTL_SYSCALL=y
 
+CONFIG_EMBEDDED=y
 
+CONFIG_SLAB=y
 
+CONFIG_MODULES=y
 
+CONFIG_MODULE_UNLOAD=y
 
+CONFIG_MODVERSIONS=y
 
+CONFIG_MODULE_SRCVERSION_ALL=y
 
+# CONFIG_BLK_DEV_BSG is not set
 
+CONFIG_PCI=y
 
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 
+CONFIG_NET=y
 
+CONFIG_PACKET=y
 
+CONFIG_UNIX=y
 
+CONFIG_XFRM_USER=m
 
+CONFIG_NET_KEY=y
 
+CONFIG_INET=y
 
+CONFIG_IP_MULTICAST=y
 
+CONFIG_IP_ADVANCED_ROUTER=y
 
+CONFIG_IP_MULTIPLE_TABLES=y
 
+CONFIG_IP_ROUTE_MULTIPATH=y
 
+CONFIG_IP_ROUTE_VERBOSE=y
 
+CONFIG_IP_PNP=y
 
+CONFIG_IP_PNP_DHCP=y
 
+CONFIG_IP_PNP_BOOTP=y
 
+CONFIG_NET_IPIP=m
 
+CONFIG_IP_MROUTE=y
 
+CONFIG_IP_PIMSM_V1=y
 
+CONFIG_IP_PIMSM_V2=y
 
+CONFIG_SYN_COOKIES=y
 
+CONFIG_INET_AH=m
 
+CONFIG_INET_ESP=m
 
+CONFIG_INET_IPCOMP=m
 
+# CONFIG_INET_LRO is not set
 
+CONFIG_INET6_AH=m
 
+CONFIG_INET6_ESP=m
 
+CONFIG_INET6_IPCOMP=m
 
+CONFIG_IPV6_TUNNEL=m
 
+CONFIG_BRIDGE=m
 
+CONFIG_VLAN_8021Q=m
 
+CONFIG_ATALK=m
 
+CONFIG_DEV_APPLETALK=m
 
+CONFIG_IPDDP=m
 
+CONFIG_IPDDP_ENCAP=y
 
+CONFIG_NET_SCHED=y
 
+CONFIG_NET_SCH_CBQ=m
 
+CONFIG_NET_SCH_HTB=m
 
+CONFIG_NET_SCH_HFSC=m
 
+CONFIG_NET_SCH_PRIO=m
 
+CONFIG_NET_SCH_RED=m
 
+CONFIG_NET_SCH_SFQ=m
 
+CONFIG_NET_SCH_TEQL=m
 
+CONFIG_NET_SCH_TBF=m
 
+CONFIG_NET_SCH_GRED=m
 
+CONFIG_NET_SCH_DSMARK=m
 
+CONFIG_NET_SCH_NETEM=m
 
+CONFIG_NET_SCH_INGRESS=m
 
+CONFIG_NET_CLS_BASIC=m
 
+CONFIG_NET_CLS_TCINDEX=m
 
+CONFIG_NET_CLS_ROUTE4=m
 
+CONFIG_NET_CLS_FW=m
 
+CONFIG_NET_CLS_U32=m
 
+CONFIG_NET_CLS_RSVP=m
 
+CONFIG_NET_CLS_RSVP6=m
 
+CONFIG_NET_CLS_ACT=y
 
+CONFIG_NET_ACT_POLICE=y
 
+CONFIG_NET_CLS_IND=y
 
+# CONFIG_WIRELESS is not set
 
+CONFIG_DEVTMPFS=y
 
+CONFIG_BLK_DEV_LOOP=y
 
+CONFIG_BLK_DEV_CRYPTOLOOP=m
 
+CONFIG_IDE=y
 
+# CONFIG_IDE_PROC_FS is not set
 
+# CONFIG_IDEPCI_PCIBUS_ORDER is not set
 
+CONFIG_BLK_DEV_GENERIC=y
 
+CONFIG_BLK_DEV_PIIX=y
 
+CONFIG_SCSI=y
 
+CONFIG_BLK_DEV_SD=y
 
+CONFIG_CHR_DEV_SG=y
 
+# CONFIG_SCSI_LOWLEVEL is not set
 
+CONFIG_NETDEVICES=y
 
+# CONFIG_NET_VENDOR_3COM is not set
 
+# CONFIG_NET_VENDOR_ADAPTEC is not set
 
+# CONFIG_NET_VENDOR_ALTEON is not set
 
+CONFIG_PCNET32=y
 
+# CONFIG_NET_VENDOR_ATHEROS is not set
 
+# CONFIG_NET_VENDOR_BROADCOM is not set
 
+# CONFIG_NET_VENDOR_BROCADE is not set
 
+# CONFIG_NET_VENDOR_CHELSIO is not set
 
+# CONFIG_NET_VENDOR_CISCO is not set
 
+# CONFIG_NET_VENDOR_DEC is not set
 
+# CONFIG_NET_VENDOR_DLINK is not set
 
+# CONFIG_NET_VENDOR_EMULEX is not set
 
+# CONFIG_NET_VENDOR_EXAR is not set
 
+# CONFIG_NET_VENDOR_HP is not set
 
+# CONFIG_NET_VENDOR_INTEL is not set
 
+# CONFIG_NET_VENDOR_MARVELL is not set
 
+# CONFIG_NET_VENDOR_MELLANOX is not set
 
+# CONFIG_NET_VENDOR_MICREL is not set
 
+# CONFIG_NET_VENDOR_MYRI is not set
 
+# CONFIG_NET_VENDOR_NATSEMI is not set
 
+# CONFIG_NET_VENDOR_NVIDIA is not set
 
+# CONFIG_NET_VENDOR_OKI is not set
 
+# CONFIG_NET_PACKET_ENGINE is not set
 
+# CONFIG_NET_VENDOR_QLOGIC is not set
 
+# CONFIG_NET_VENDOR_REALTEK is not set
 
+# CONFIG_NET_VENDOR_RDC is not set
 
+# CONFIG_NET_VENDOR_SEEQ is not set
 
+# CONFIG_NET_VENDOR_SILAN is not set
 
+# CONFIG_NET_VENDOR_SIS is not set
 
+# CONFIG_NET_VENDOR_SMSC is not set
 
+# CONFIG_NET_VENDOR_STMICRO is not set
 
+# CONFIG_NET_VENDOR_SUN is not set
 
+# CONFIG_NET_VENDOR_TEHUTI is not set
 
+# CONFIG_NET_VENDOR_TI is not set
 
+# CONFIG_NET_VENDOR_TOSHIBA is not set
 
+# CONFIG_NET_VENDOR_VIA is not set
 
+# CONFIG_NET_VENDOR_WIZNET is not set
 
+# CONFIG_WLAN is not set
 
+# CONFIG_VT is not set
 
+CONFIG_LEGACY_PTY_COUNT=4
 
+CONFIG_SERIAL_8250=y
 
+CONFIG_SERIAL_8250_CONSOLE=y
 
+CONFIG_HW_RANDOM=y
 
+# CONFIG_HWMON is not set
 
+CONFIG_VIDEO_OUTPUT_CONTROL=m
 
+CONFIG_FB=y
 
+CONFIG_FIRMWARE_EDID=y
 
+CONFIG_FB_MATROX=y
 
+CONFIG_FB_MATROX_G=y
 
+CONFIG_USB=y
 
+CONFIG_USB_EHCI_HCD=y
 
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
 
+CONFIG_USB_UHCI_HCD=y
 
+CONFIG_USB_STORAGE=y
 
+CONFIG_NEW_LEDS=y
 
+CONFIG_LEDS_CLASS=y
 
+CONFIG_LEDS_TRIGGERS=y
 
+CONFIG_LEDS_TRIGGER_TIMER=y
 
+CONFIG_LEDS_TRIGGER_IDE_DISK=y
 
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
 
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
 
+CONFIG_RTC_CLASS=y
 
+CONFIG_RTC_DRV_CMOS=y
 
+CONFIG_EXT2_FS=y
 
+CONFIG_EXT3_FS=y
 
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
 
+CONFIG_XFS_FS=y
 
+CONFIG_XFS_QUOTA=y
 
+CONFIG_XFS_POSIX_ACL=y
 
+CONFIG_QUOTA=y
 
+CONFIG_QFMT_V2=y
 
+CONFIG_MSDOS_FS=m
 
+CONFIG_VFAT_FS=m
 
+CONFIG_PROC_KCORE=y
 
+CONFIG_TMPFS=y
 
+CONFIG_NFS_FS=y
 
+CONFIG_ROOT_NFS=y
 
+CONFIG_CIFS=m
 
+CONFIG_CIFS_WEAK_PW_HASH=y
 
+CONFIG_CIFS_XATTR=y
 
+CONFIG_CIFS_POSIX=y
 
+CONFIG_NLS_CODEPAGE_437=m
 
+CONFIG_NLS_ISO8859_1=m
 
+# CONFIG_FTRACE is not set
 
+CONFIG_CRYPTO_NULL=m
 
+CONFIG_CRYPTO_PCBC=m
 
+CONFIG_CRYPTO_HMAC=y
 
+CONFIG_CRYPTO_MICHAEL_MIC=m
 
+CONFIG_CRYPTO_SHA512=m
 
+CONFIG_CRYPTO_TGR192=m
 
+CONFIG_CRYPTO_WP512=m
 
+CONFIG_CRYPTO_ANUBIS=m
 
+CONFIG_CRYPTO_BLOWFISH=m
 
+CONFIG_CRYPTO_CAST5=m
 
+CONFIG_CRYPTO_CAST6=m
 
+CONFIG_CRYPTO_KHAZAD=m
 
+CONFIG_CRYPTO_SERPENT=m
 
+CONFIG_CRYPTO_TEA=m
 
+CONFIG_CRYPTO_TWOFISH=m
 
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
 
+# CONFIG_CRYPTO_HW is not set

+ 1 - 2
arch/mips/configs/maltaup_defconfig
Vizualizați fișierul 

@@ -43,7 +43,6 @@ CONFIG_INET_AH=m
 
 CONFIG_INET_ESP=m
 
 CONFIG_INET_ESP=m
 
 CONFIG_INET_IPCOMP=m
 
 CONFIG_INET_IPCOMP=m
 
 # CONFIG_INET_LRO is not set
 
 # CONFIG_INET_LRO is not set
 
-CONFIG_IPV6_PRIVACY=y
 
 CONFIG_INET6_AH=m
 
 CONFIG_INET6_AH=m
 
 CONFIG_INET6_ESP=m
 
 CONFIG_INET6_ESP=m
 
 CONFIG_INET6_IPCOMP=m
 
 CONFIG_INET6_IPCOMP=m
 
@@ -54,7 +53,6 @@ CONFIG_ATALK=m
 
 CONFIG_DEV_APPLETALK=m
 
 CONFIG_DEV_APPLETALK=m
 
 CONFIG_IPDDP=m
 
 CONFIG_IPDDP=m
 
 CONFIG_IPDDP_ENCAP=y
 
 CONFIG_IPDDP_ENCAP=y
 
-CONFIG_IPDDP_DECAP=y
 
 CONFIG_NET_SCHED=y
 
 CONFIG_NET_SCHED=y
 
 CONFIG_NET_SCH_CBQ=m
 
 CONFIG_NET_SCH_CBQ=m
 
 CONFIG_NET_SCH_HTB=m
 
 CONFIG_NET_SCH_HTB=m
 
@@ -79,6 +77,7 @@ CONFIG_NET_CLS_ACT=y
 
 CONFIG_NET_ACT_POLICE=y
 
 CONFIG_NET_ACT_POLICE=y
 
 CONFIG_NET_CLS_IND=y
 
 CONFIG_NET_CLS_IND=y
 
 # CONFIG_WIRELESS is not set
 
 # CONFIG_WIRELESS is not set
 
+CONFIG_DEVTMPFS=y
 
 CONFIG_BLK_DEV_LOOP=y
 
 CONFIG_BLK_DEV_LOOP=y
 
 CONFIG_BLK_DEV_CRYPTOLOOP=m
 
 CONFIG_BLK_DEV_CRYPTOLOOP=m
 
 CONFIG_IDE=y
 
 CONFIG_IDE=y

+ 135 - 0
arch/mips/include/asm/asm-eva.h
Vizualizați fișierul 

@@ -0,0 +1,135 @@
 
+/*
 
+ * This file is subject to the terms and conditions of the GNU General Public
 
+ * License.  See the file "COPYING" in the main directory of this archive
 
+ * for more details.
 
+ *
 
+ * Copyright (C) 2014 Imagination Technologies Ltd.
 
+ *
 
+ */
 
+
 
+#ifndef __ASM_ASM_EVA_H
 
+#define __ASM_ASM_EVA_H
 
+
 
+#ifndef __ASSEMBLY__
 
+#ifdef CONFIG_EVA
 
+
 
+#define __BUILD_EVA_INSN(insn, reg, addr)				\
 
+				"	.set	push\n"			\
 
+				"	.set	mips0\n"		\
 
+				"	.set	eva\n"			\
 
+				"	"insn" "reg", "addr "\n"	\
 
+				"	.set	pop\n"
 
+
 
+#define user_cache(op, base)		__BUILD_EVA_INSN("cachee", op, base)
 
+#define user_ll(reg, addr)		__BUILD_EVA_INSN("lle", reg, addr)
 
+#define user_sc(reg, addr)		__BUILD_EVA_INSN("sce", reg, addr)
 
+#define user_lw(reg, addr)		__BUILD_EVA_INSN("lwe", reg, addr)
 
+#define user_lwl(reg, addr)		__BUILD_EVA_INSN("lwle", reg, addr)
 
+#define user_lwr(reg, addr)		__BUILD_EVA_INSN("lwre", reg, addr)
 
+#define user_lh(reg, addr)		__BUILD_EVA_INSN("lhe", reg, addr)
 
+#define user_lb(reg, addr)		__BUILD_EVA_INSN("lbe", reg, addr)
 
+#define user_lbu(reg, addr)		__BUILD_EVA_INSN("lbue", reg, addr)
 
+/* No 64-bit EVA instruction for loading double words */
 
+#define user_ld(reg, addr)		user_lw(reg, addr)
 
+#define user_sw(reg, addr)		__BUILD_EVA_INSN("swe", reg, addr)
 
+#define user_swl(reg, addr)		__BUILD_EVA_INSN("swle", reg, addr)
 
+#define user_swr(reg, addr)		__BUILD_EVA_INSN("swre", reg, addr)
 
+#define user_sh(reg, addr)		__BUILD_EVA_INSN("she", reg, addr)
 
+#define user_sb(reg, addr)		__BUILD_EVA_INSN("sbe", reg, addr)
 
+/* No 64-bit EVA instruction for storing double words */
 
+#define user_sd(reg, addr)		user_sw(reg, addr)
 
+
 
+#else
 
+
 
+#define user_cache(op, base)		"cache " op ", " base "\n"
 
+#define user_ll(reg, addr)		"ll " reg ", " addr "\n"
 
+#define user_sc(reg, addr)		"sc " reg ", " addr "\n"
 
+#define user_lw(reg, addr)		"lw " reg ", " addr "\n"
 
+#define user_lwl(reg, addr)		"lwl " reg ", " addr "\n"
 
+#define user_lwr(reg, addr)		"lwr " reg ", " addr "\n"
 
+#define user_lh(reg, addr)		"lh " reg ", " addr "\n"
 
+#define user_lb(reg, addr)		"lb " reg ", " addr "\n"
 
+#define user_lbu(reg, addr)		"lbu " reg ", " addr "\n"
 
+#define user_sw(reg, addr)		"sw " reg ", " addr "\n"
 
+#define user_swl(reg, addr)		"swl " reg ", " addr "\n"
 
+#define user_swr(reg, addr)		"swr " reg ", " addr "\n"
 
+#define user_sh(reg, addr)		"sh " reg ", " addr "\n"
 
+#define user_sb(reg, addr)		"sb " reg ", " addr "\n"
 
+
 
+#ifdef CONFIG_32BIT
 
+/*
 
+ * No 'sd' or 'ld' instructions in 32-bit but the code will
 
+ * do the correct thing
 
+ */
 
+#define user_sd(reg, addr)		user_sw(reg, addr)
 
+#define user_ld(reg, addr)		user_lw(reg, addr)
 
+#else
 
+#define user_sd(reg, addr)		"sd " reg", " addr "\n"
 
+#define user_ld(reg, addr)		"ld " reg", " addr "\n"
 
+#endif /* CONFIG_32BIT */
 
+
 
+#endif /* CONFIG_EVA */
 
+
 
+#else /* __ASSEMBLY__ */
 
+
 
+#ifdef CONFIG_EVA
 
+
 
+#define __BUILD_EVA_INSN(insn, reg, addr)			\
 
+				.set	push;			\
 
+				.set	mips0;			\
 
+				.set	eva;			\
 
+				insn reg, addr;			\
 
+				.set	pop;
 
+
 
+#define user_cache(op, base)		__BUILD_EVA_INSN(cachee, op, base)
 
+#define user_ll(reg, addr)		__BUILD_EVA_INSN(lle, reg, addr)
 
+#define user_sc(reg, addr)		__BUILD_EVA_INSN(sce, reg, addr)
 
+#define user_lw(reg, addr)		__BUILD_EVA_INSN(lwe, reg, addr)
 
+#define user_lwl(reg, addr)		__BUILD_EVA_INSN(lwle, reg, addr)
 
+#define user_lwr(reg, addr)		__BUILD_EVA_INSN(lwre, reg, addr)
 
+#define user_lh(reg, addr)		__BUILD_EVA_INSN(lhe, reg, addr)
 
+#define user_lb(reg, addr)		__BUILD_EVA_INSN(lbe, reg, addr)
 
+#define user_lbu(reg, addr)		__BUILD_EVA_INSN(lbue, reg, addr)
 
+/* No 64-bit EVA instruction for loading double words */
 
+#define user_ld(reg, addr)		user_lw(reg, addr)
 
+#define user_sw(reg, addr)		__BUILD_EVA_INSN(swe, reg, addr)
 
+#define user_swl(reg, addr)		__BUILD_EVA_INSN(swle, reg, addr)
 
+#define user_swr(reg, addr)		__BUILD_EVA_INSN(swre, reg, addr)
 
+#define user_sh(reg, addr)		__BUILD_EVA_INSN(she, reg, addr)
 
+#define user_sb(reg, addr)		__BUILD_EVA_INSN(sbe, reg, addr)
 
+/* No 64-bit EVA instruction for loading double words */
 
+#define user_sd(reg, addr)		user_sw(reg, addr)
 
+#else
 
+
 
+#define user_cache(op, base)		cache op, base
 
+#define user_ll(reg, addr)		ll reg, addr
 
+#define user_sc(reg, addr)		sc reg, addr
 
+#define user_lw(reg, addr)		lw reg, addr
 
+#define user_lwl(reg, addr)		lwl reg, addr
 
+#define user_lwr(reg, addr)		lwr reg, addr
 
+#define user_lh(reg, addr)		lh reg, addr
 
+#define user_lb(reg, addr)		lb reg, addr
 
+#define user_lbu(reg, addr)		lbu reg, addr
 
+#define user_sw(reg, addr)		sw reg, addr
 
+#define user_swl(reg, addr)		swl reg, addr
 
+#define user_swr(reg, addr)		swr reg, addr
 
+#define user_sh(reg, addr)		sh reg, addr
 
+#define user_sb(reg, addr)		sb reg, addr
 
+
 
+#ifdef CONFIG_32BIT
 
+/*
 
+ * No 'sd' or 'ld' instructions in 32-bit but the code will
 
+ * do the correct thing
 
+ */
 
+#define user_sd(reg, addr)		user_sw(reg, addr)
 
+#define user_ld(reg, addr)		user_lw(reg, addr)
 
+#else
 
+#define user_sd(reg, addr)		sd reg, addr
 
+#define user_ld(reg, addr)		ld reg, addr
 
+#endif /* CONFIG_32BIT */
 
+
 
+#endif /* CONFIG_EVA */
 
+
 
+#endif /* __ASSEMBLY__ */
 
+
 
+#endif /* __ASM_ASM_EVA_H */

+ 11 - 2
arch/mips/include/asm/asm.h
Vizualizați fișierul 

@@ -18,6 +18,7 @@
 
 #define __ASM_ASM_H
 
 #define __ASM_ASM_H
 
 
 
 #include <asm/sgidefs.h>
 
 #include <asm/sgidefs.h>
 
+#include <asm/asm-eva.h>
 
 
 
 #ifndef CAT
 
 #ifndef CAT
 
 #ifdef __STDC__
 
 #ifdef __STDC__
 
@@ -145,19 +146,27 @@ symbol		=	value
 
 
 
 #define PREF(hint,addr)					\
 
 #define PREF(hint,addr)					\
 
 		.set	push;				\
 
 		.set	push;				\
 
-		.set	mips4;				\
 
+		.set	arch=r5000;			\
 
 		pref	hint, addr;			\
 
 		pref	hint, addr;			\
 
 		.set	pop
 
 		.set	pop
 
 
 
+#define PREFE(hint, addr)				\
 
+		.set	push;				\
 
+		.set	mips0;				\
 
+		.set	eva;				\
 
+		prefe	hint, addr;			\
 
+		.set	pop
 
+
 
 #define PREFX(hint,addr)				\
 
 #define PREFX(hint,addr)				\
 
 		.set	push;				\
 
 		.set	push;				\
 
-		.set	mips4;				\
 
+		.set	arch=r5000;			\
 
 		prefx	hint, addr;			\
 
 		prefx	hint, addr;			\
 
 		.set	pop
 
 		.set	pop
 
 
 
 #else /* !CONFIG_CPU_HAS_PREFETCH */
 
 #else /* !CONFIG_CPU_HAS_PREFETCH */
 
 
 
 #define PREF(hint, addr)
 
 #define PREF(hint, addr)
 
+#define PREFE(hint, addr)
 
 #define PREFX(hint, addr)
 
 #define PREFX(hint, addr)
 
 
 
 #endif /* !CONFIG_CPU_HAS_PREFETCH */
 
 #endif /* !CONFIG_CPU_HAS_PREFETCH */

+ 64 - 64
arch/mips/include/asm/asmmacro-32.h
Vizualizați fișierul 

@@ -14,75 +14,75 @@
 
 
 
 	.macro	fpu_save_single thread tmp=t0
 
 	.macro	fpu_save_single thread tmp=t0
 
 	cfc1	\tmp,  fcr31
 
 	cfc1	\tmp,  fcr31
 
-	swc1	$f0,  THREAD_FPR0(\thread)
 
-	swc1	$f1,  THREAD_FPR1(\thread)
 
-	swc1	$f2,  THREAD_FPR2(\thread)
 
-	swc1	$f3,  THREAD_FPR3(\thread)
 
-	swc1	$f4,  THREAD_FPR4(\thread)
 
-	swc1	$f5,  THREAD_FPR5(\thread)
 
-	swc1	$f6,  THREAD_FPR6(\thread)
 
-	swc1	$f7,  THREAD_FPR7(\thread)
 
-	swc1	$f8,  THREAD_FPR8(\thread)
 
-	swc1	$f9,  THREAD_FPR9(\thread)
 
-	swc1	$f10, THREAD_FPR10(\thread)
 
-	swc1	$f11, THREAD_FPR11(\thread)
 
-	swc1	$f12, THREAD_FPR12(\thread)
 
-	swc1	$f13, THREAD_FPR13(\thread)
 
-	swc1	$f14, THREAD_FPR14(\thread)
 
-	swc1	$f15, THREAD_FPR15(\thread)
 
-	swc1	$f16, THREAD_FPR16(\thread)
 
-	swc1	$f17, THREAD_FPR17(\thread)
 
-	swc1	$f18, THREAD_FPR18(\thread)
 
-	swc1	$f19, THREAD_FPR19(\thread)
 
-	swc1	$f20, THREAD_FPR20(\thread)
 
-	swc1	$f21, THREAD_FPR21(\thread)
 
-	swc1	$f22, THREAD_FPR22(\thread)
 
-	swc1	$f23, THREAD_FPR23(\thread)
 
-	swc1	$f24, THREAD_FPR24(\thread)
 
-	swc1	$f25, THREAD_FPR25(\thread)
 
-	swc1	$f26, THREAD_FPR26(\thread)
 
-	swc1	$f27, THREAD_FPR27(\thread)
 
-	swc1	$f28, THREAD_FPR28(\thread)
 
-	swc1	$f29, THREAD_FPR29(\thread)
 
-	swc1	$f30, THREAD_FPR30(\thread)
 
-	swc1	$f31, THREAD_FPR31(\thread)
 
+	swc1	$f0,  THREAD_FPR0_LS64(\thread)
 
+	swc1	$f1,  THREAD_FPR1_LS64(\thread)
 
+	swc1	$f2,  THREAD_FPR2_LS64(\thread)
 
+	swc1	$f3,  THREAD_FPR3_LS64(\thread)
 
+	swc1	$f4,  THREAD_FPR4_LS64(\thread)
 
+	swc1	$f5,  THREAD_FPR5_LS64(\thread)
 
+	swc1	$f6,  THREAD_FPR6_LS64(\thread)
 
+	swc1	$f7,  THREAD_FPR7_LS64(\thread)
 
+	swc1	$f8,  THREAD_FPR8_LS64(\thread)
 
+	swc1	$f9,  THREAD_FPR9_LS64(\thread)
 
+	swc1	$f10, THREAD_FPR10_LS64(\thread)
 
+	swc1	$f11, THREAD_FPR11_LS64(\thread)
 
+	swc1	$f12, THREAD_FPR12_LS64(\thread)
 
+	swc1	$f13, THREAD_FPR13_LS64(\thread)
 
+	swc1	$f14, THREAD_FPR14_LS64(\thread)
 
+	swc1	$f15, THREAD_FPR15_LS64(\thread)
 
+	swc1	$f16, THREAD_FPR16_LS64(\thread)
 
+	swc1	$f17, THREAD_FPR17_LS64(\thread)
 
+	swc1	$f18, THREAD_FPR18_LS64(\thread)
 
+	swc1	$f19, THREAD_FPR19_LS64(\thread)
 
+	swc1	$f20, THREAD_FPR20_LS64(\thread)
 
+	swc1	$f21, THREAD_FPR21_LS64(\thread)
 
+	swc1	$f22, THREAD_FPR22_LS64(\thread)
 
+	swc1	$f23, THREAD_FPR23_LS64(\thread)
 
+	swc1	$f24, THREAD_FPR24_LS64(\thread)
 
+	swc1	$f25, THREAD_FPR25_LS64(\thread)
 
+	swc1	$f26, THREAD_FPR26_LS64(\thread)
 
+	swc1	$f27, THREAD_FPR27_LS64(\thread)
 
+	swc1	$f28, THREAD_FPR28_LS64(\thread)
 
+	swc1	$f29, THREAD_FPR29_LS64(\thread)
 
+	swc1	$f30, THREAD_FPR30_LS64(\thread)
 
+	swc1	$f31, THREAD_FPR31_LS64(\thread)
 
 	sw	\tmp, THREAD_FCR31(\thread)
 
 	sw	\tmp, THREAD_FCR31(\thread)
 
 	.endm
 
 	.endm
 
 
 
 	.macro	fpu_restore_single thread tmp=t0
 
 	.macro	fpu_restore_single thread tmp=t0
 
 	lw	\tmp, THREAD_FCR31(\thread)
 
 	lw	\tmp, THREAD_FCR31(\thread)
 
-	lwc1	$f0,  THREAD_FPR0(\thread)
 
-	lwc1	$f1,  THREAD_FPR1(\thread)
 
-	lwc1	$f2,  THREAD_FPR2(\thread)
 
-	lwc1	$f3,  THREAD_FPR3(\thread)
 
-	lwc1	$f4,  THREAD_FPR4(\thread)
 
-	lwc1	$f5,  THREAD_FPR5(\thread)
 
-	lwc1	$f6,  THREAD_FPR6(\thread)
 
-	lwc1	$f7,  THREAD_FPR7(\thread)
 
-	lwc1	$f8,  THREAD_FPR8(\thread)
 
-	lwc1	$f9,  THREAD_FPR9(\thread)
 
-	lwc1	$f10, THREAD_FPR10(\thread)
 
-	lwc1	$f11, THREAD_FPR11(\thread)
 
-	lwc1	$f12, THREAD_FPR12(\thread)
 
-	lwc1	$f13, THREAD_FPR13(\thread)
 
-	lwc1	$f14, THREAD_FPR14(\thread)
 
-	lwc1	$f15, THREAD_FPR15(\thread)
 
-	lwc1	$f16, THREAD_FPR16(\thread)
 
-	lwc1	$f17, THREAD_FPR17(\thread)
 
-	lwc1	$f18, THREAD_FPR18(\thread)
 
-	lwc1	$f19, THREAD_FPR19(\thread)
 
-	lwc1	$f20, THREAD_FPR20(\thread)
 
-	lwc1	$f21, THREAD_FPR21(\thread)
 
-	lwc1	$f22, THREAD_FPR22(\thread)
 
-	lwc1	$f23, THREAD_FPR23(\thread)
 
-	lwc1	$f24, THREAD_FPR24(\thread)
 
-	lwc1	$f25, THREAD_FPR25(\thread)
 
-	lwc1	$f26, THREAD_FPR26(\thread)
 
-	lwc1	$f27, THREAD_FPR27(\thread)
 
-	lwc1	$f28, THREAD_FPR28(\thread)
 
-	lwc1	$f29, THREAD_FPR29(\thread)
 
-	lwc1	$f30, THREAD_FPR30(\thread)
 
-	lwc1	$f31, THREAD_FPR31(\thread)
 
+	lwc1	$f0,  THREAD_FPR0_LS64(\thread)
 
+	lwc1	$f1,  THREAD_FPR1_LS64(\thread)
 
+	lwc1	$f2,  THREAD_FPR2_LS64(\thread)
 
+	lwc1	$f3,  THREAD_FPR3_LS64(\thread)
 
+	lwc1	$f4,  THREAD_FPR4_LS64(\thread)
 
+	lwc1	$f5,  THREAD_FPR5_LS64(\thread)
 
+	lwc1	$f6,  THREAD_FPR6_LS64(\thread)
 
+	lwc1	$f7,  THREAD_FPR7_LS64(\thread)
 
+	lwc1	$f8,  THREAD_FPR8_LS64(\thread)
 
+	lwc1	$f9,  THREAD_FPR9_LS64(\thread)
 
+	lwc1	$f10, THREAD_FPR10_LS64(\thread)
 
+	lwc1	$f11, THREAD_FPR11_LS64(\thread)
 
+	lwc1	$f12, THREAD_FPR12_LS64(\thread)
 
+	lwc1	$f13, THREAD_FPR13_LS64(\thread)
 
+	lwc1	$f14, THREAD_FPR14_LS64(\thread)
 
+	lwc1	$f15, THREAD_FPR15_LS64(\thread)
 
+	lwc1	$f16, THREAD_FPR16_LS64(\thread)
 
+	lwc1	$f17, THREAD_FPR17_LS64(\thread)
 
+	lwc1	$f18, THREAD_FPR18_LS64(\thread)
 
+	lwc1	$f19, THREAD_FPR19_LS64(\thread)
 
+	lwc1	$f20, THREAD_FPR20_LS64(\thread)
 
+	lwc1	$f21, THREAD_FPR21_LS64(\thread)
 
+	lwc1	$f22, THREAD_FPR22_LS64(\thread)
 
+	lwc1	$f23, THREAD_FPR23_LS64(\thread)
 
+	lwc1	$f24, THREAD_FPR24_LS64(\thread)
 
+	lwc1	$f25, THREAD_FPR25_LS64(\thread)
 
+	lwc1	$f26, THREAD_FPR26_LS64(\thread)
 
+	lwc1	$f27, THREAD_FPR27_LS64(\thread)
 
+	lwc1	$f28, THREAD_FPR28_LS64(\thread)
 
+	lwc1	$f29, THREAD_FPR29_LS64(\thread)
 
+	lwc1	$f30, THREAD_FPR30_LS64(\thread)
 
+	lwc1	$f31, THREAD_FPR31_LS64(\thread)
 
 	ctc1	\tmp, fcr31
 
 	ctc1	\tmp, fcr31
 
 	.endm
 
 	.endm

+ 266 - 64
arch/mips/include/asm/asmmacro.h
Vizualizați fișierul 

@@ -75,44 +75,44 @@
 
 
 
 	.macro	fpu_save_16even thread tmp=t0
 
 	.macro	fpu_save_16even thread tmp=t0
 
 	cfc1	\tmp, fcr31
 
 	cfc1	\tmp, fcr31
 
-	sdc1	$f0,  THREAD_FPR0(\thread)
 
-	sdc1	$f2,  THREAD_FPR2(\thread)
 
-	sdc1	$f4,  THREAD_FPR4(\thread)
 
-	sdc1	$f6,  THREAD_FPR6(\thread)
 
-	sdc1	$f8,  THREAD_FPR8(\thread)
 
-	sdc1	$f10, THREAD_FPR10(\thread)
 
-	sdc1	$f12, THREAD_FPR12(\thread)
 
-	sdc1	$f14, THREAD_FPR14(\thread)
 
-	sdc1	$f16, THREAD_FPR16(\thread)
 
-	sdc1	$f18, THREAD_FPR18(\thread)
 
-	sdc1	$f20, THREAD_FPR20(\thread)
 
-	sdc1	$f22, THREAD_FPR22(\thread)
 
-	sdc1	$f24, THREAD_FPR24(\thread)
 
-	sdc1	$f26, THREAD_FPR26(\thread)
 
-	sdc1	$f28, THREAD_FPR28(\thread)
 
-	sdc1	$f30, THREAD_FPR30(\thread)
 
+	sdc1	$f0,  THREAD_FPR0_LS64(\thread)
 
+	sdc1	$f2,  THREAD_FPR2_LS64(\thread)
 
+	sdc1	$f4,  THREAD_FPR4_LS64(\thread)
 
+	sdc1	$f6,  THREAD_FPR6_LS64(\thread)
 
+	sdc1	$f8,  THREAD_FPR8_LS64(\thread)
 
+	sdc1	$f10, THREAD_FPR10_LS64(\thread)
 
+	sdc1	$f12, THREAD_FPR12_LS64(\thread)
 
+	sdc1	$f14, THREAD_FPR14_LS64(\thread)
 
+	sdc1	$f16, THREAD_FPR16_LS64(\thread)
 
+	sdc1	$f18, THREAD_FPR18_LS64(\thread)
 
+	sdc1	$f20, THREAD_FPR20_LS64(\thread)
 
+	sdc1	$f22, THREAD_FPR22_LS64(\thread)
 
+	sdc1	$f24, THREAD_FPR24_LS64(\thread)
 
+	sdc1	$f26, THREAD_FPR26_LS64(\thread)
 
+	sdc1	$f28, THREAD_FPR28_LS64(\thread)
 
+	sdc1	$f30, THREAD_FPR30_LS64(\thread)
 
 	sw	\tmp, THREAD_FCR31(\thread)
 
 	sw	\tmp, THREAD_FCR31(\thread)
 
 	.endm
 
 	.endm
 
 
 
 	.macro	fpu_save_16odd thread
 
 	.macro	fpu_save_16odd thread
 
 	.set	push
 
 	.set	push
 
 	.set	mips64r2
 
 	.set	mips64r2
 
-	sdc1	$f1,  THREAD_FPR1(\thread)
 
-	sdc1	$f3,  THREAD_FPR3(\thread)
 
-	sdc1	$f5,  THREAD_FPR5(\thread)
 
-	sdc1	$f7,  THREAD_FPR7(\thread)
 
-	sdc1	$f9,  THREAD_FPR9(\thread)
 
-	sdc1	$f11, THREAD_FPR11(\thread)
 
-	sdc1	$f13, THREAD_FPR13(\thread)
 
-	sdc1	$f15, THREAD_FPR15(\thread)
 
-	sdc1	$f17, THREAD_FPR17(\thread)
 
-	sdc1	$f19, THREAD_FPR19(\thread)
 
-	sdc1	$f21, THREAD_FPR21(\thread)
 
-	sdc1	$f23, THREAD_FPR23(\thread)
 
-	sdc1	$f25, THREAD_FPR25(\thread)
 
-	sdc1	$f27, THREAD_FPR27(\thread)
 
-	sdc1	$f29, THREAD_FPR29(\thread)
 
-	sdc1	$f31, THREAD_FPR31(\thread)
 
+	sdc1	$f1,  THREAD_FPR1_LS64(\thread)
 
+	sdc1	$f3,  THREAD_FPR3_LS64(\thread)
 
+	sdc1	$f5,  THREAD_FPR5_LS64(\thread)
 
+	sdc1	$f7,  THREAD_FPR7_LS64(\thread)
 
+	sdc1	$f9,  THREAD_FPR9_LS64(\thread)
 
+	sdc1	$f11, THREAD_FPR11_LS64(\thread)
 
+	sdc1	$f13, THREAD_FPR13_LS64(\thread)
 
+	sdc1	$f15, THREAD_FPR15_LS64(\thread)
 
+	sdc1	$f17, THREAD_FPR17_LS64(\thread)
 
+	sdc1	$f19, THREAD_FPR19_LS64(\thread)
 
+	sdc1	$f21, THREAD_FPR21_LS64(\thread)
 
+	sdc1	$f23, THREAD_FPR23_LS64(\thread)
 
+	sdc1	$f25, THREAD_FPR25_LS64(\thread)
 
+	sdc1	$f27, THREAD_FPR27_LS64(\thread)
 
+	sdc1	$f29, THREAD_FPR29_LS64(\thread)
 
+	sdc1	$f31, THREAD_FPR31_LS64(\thread)
 
 	.set	pop
 
 	.set	pop
 
 	.endm
 
 	.endm
 
 
 
@@ -128,44 +128,44 @@
 
 
 
 	.macro	fpu_restore_16even thread tmp=t0
 
 	.macro	fpu_restore_16even thread tmp=t0
 
 	lw	\tmp, THREAD_FCR31(\thread)
 
 	lw	\tmp, THREAD_FCR31(\thread)
 
-	ldc1	$f0,  THREAD_FPR0(\thread)
 
-	ldc1	$f2,  THREAD_FPR2(\thread)
 
-	ldc1	$f4,  THREAD_FPR4(\thread)
 
-	ldc1	$f6,  THREAD_FPR6(\thread)
 
-	ldc1	$f8,  THREAD_FPR8(\thread)
 
-	ldc1	$f10, THREAD_FPR10(\thread)
 
-	ldc1	$f12, THREAD_FPR12(\thread)
 
-	ldc1	$f14, THREAD_FPR14(\thread)
 
-	ldc1	$f16, THREAD_FPR16(\thread)
 
-	ldc1	$f18, THREAD_FPR18(\thread)
 
-	ldc1	$f20, THREAD_FPR20(\thread)
 
-	ldc1	$f22, THREAD_FPR22(\thread)
 
-	ldc1	$f24, THREAD_FPR24(\thread)
 
-	ldc1	$f26, THREAD_FPR26(\thread)
 
-	ldc1	$f28, THREAD_FPR28(\thread)
 
-	ldc1	$f30, THREAD_FPR30(\thread)
 
+	ldc1	$f0,  THREAD_FPR0_LS64(\thread)
 
+	ldc1	$f2,  THREAD_FPR2_LS64(\thread)
 
+	ldc1	$f4,  THREAD_FPR4_LS64(\thread)
 
+	ldc1	$f6,  THREAD_FPR6_LS64(\thread)
 
+	ldc1	$f8,  THREAD_FPR8_LS64(\thread)
 
+	ldc1	$f10, THREAD_FPR10_LS64(\thread)
 
+	ldc1	$f12, THREAD_FPR12_LS64(\thread)
 
+	ldc1	$f14, THREAD_FPR14_LS64(\thread)
 
+	ldc1	$f16, THREAD_FPR16_LS64(\thread)
 
+	ldc1	$f18, THREAD_FPR18_LS64(\thread)
 
+	ldc1	$f20, THREAD_FPR20_LS64(\thread)
 
+	ldc1	$f22, THREAD_FPR22_LS64(\thread)
 
+	ldc1	$f24, THREAD_FPR24_LS64(\thread)
 
+	ldc1	$f26, THREAD_FPR26_LS64(\thread)
 
+	ldc1	$f28, THREAD_FPR28_LS64(\thread)
 
+	ldc1	$f30, THREAD_FPR30_LS64(\thread)
 
 	ctc1	\tmp, fcr31
 
 	ctc1	\tmp, fcr31
 
 	.endm
 
 	.endm
 
 
 
 	.macro	fpu_restore_16odd thread
 
 	.macro	fpu_restore_16odd thread
 
 	.set	push
 
 	.set	push
 
 	.set	mips64r2
 
 	.set	mips64r2
 
-	ldc1	$f1,  THREAD_FPR1(\thread)
 
-	ldc1	$f3,  THREAD_FPR3(\thread)
 
-	ldc1	$f5,  THREAD_FPR5(\thread)
 
-	ldc1	$f7,  THREAD_FPR7(\thread)
 
-	ldc1	$f9,  THREAD_FPR9(\thread)
 
-	ldc1	$f11, THREAD_FPR11(\thread)
 
-	ldc1	$f13, THREAD_FPR13(\thread)
 
-	ldc1	$f15, THREAD_FPR15(\thread)
 
-	ldc1	$f17, THREAD_FPR17(\thread)
 
-	ldc1	$f19, THREAD_FPR19(\thread)
 
-	ldc1	$f21, THREAD_FPR21(\thread)
 
-	ldc1	$f23, THREAD_FPR23(\thread)
 
-	ldc1	$f25, THREAD_FPR25(\thread)
 
-	ldc1	$f27, THREAD_FPR27(\thread)
 
-	ldc1	$f29, THREAD_FPR29(\thread)
 
-	ldc1	$f31, THREAD_FPR31(\thread)
 
+	ldc1	$f1,  THREAD_FPR1_LS64(\thread)
 
+	ldc1	$f3,  THREAD_FPR3_LS64(\thread)
 
+	ldc1	$f5,  THREAD_FPR5_LS64(\thread)
 
+	ldc1	$f7,  THREAD_FPR7_LS64(\thread)
 
+	ldc1	$f9,  THREAD_FPR9_LS64(\thread)
 
+	ldc1	$f11, THREAD_FPR11_LS64(\thread)
 
+	ldc1	$f13, THREAD_FPR13_LS64(\thread)
 
+	ldc1	$f15, THREAD_FPR15_LS64(\thread)
 
+	ldc1	$f17, THREAD_FPR17_LS64(\thread)
 
+	ldc1	$f19, THREAD_FPR19_LS64(\thread)
 
+	ldc1	$f21, THREAD_FPR21_LS64(\thread)
 
+	ldc1	$f23, THREAD_FPR23_LS64(\thread)
 
+	ldc1	$f25, THREAD_FPR25_LS64(\thread)
 
+	ldc1	$f27, THREAD_FPR27_LS64(\thread)
 
+	ldc1	$f29, THREAD_FPR29_LS64(\thread)
 
+	ldc1	$f31, THREAD_FPR31_LS64(\thread)
 
 	.set	pop
 
 	.set	pop
 
 	.endm
 
 	.endm
 
 
 
@@ -180,6 +180,17 @@
 
 	fpu_restore_16even \thread \tmp
 
 	fpu_restore_16even \thread \tmp
 
 	.endm
 
 	.endm
 
 
 
+#ifdef CONFIG_CPU_MIPSR2
 
+	.macro	_EXT	rd, rs, p, s
 
+	ext	\rd, \rs, \p, \s
 
+	.endm
 
+#else /* !CONFIG_CPU_MIPSR2 */
 
+	.macro	_EXT	rd, rs, p, s
 
+	srl	\rd, \rs, \p
 
+	andi	\rd, \rd, (1 << \s) - 1
 
+	.endm
 
+#endif /* !CONFIG_CPU_MIPSR2 */
 
+
 
 /*
 
 /*
 
  * Temporary until all gas have MT ASE support
 
  * Temporary until all gas have MT ASE support
 
  */
 
  */
 
@@ -207,4 +218,195 @@
 
 	 .word	0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
 
 	 .word	0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
 
 	.endm
 
 	.endm
 
 
 
+#ifdef TOOLCHAIN_SUPPORTS_MSA
 
+	.macro	ld_d	wd, off, base
 
+	.set	push
 
+	.set	mips32r2
 
+	.set	msa
 
+	ld.d	$w\wd, \off(\base)
 
+	.set	pop
 
+	.endm
 
+
 
+	.macro	st_d	wd, off, base
 
+	.set	push
 
+	.set	mips32r2
 
+	.set	msa
 
+	st.d	$w\wd, \off(\base)
 
+	.set	pop
 
+	.endm
 
+
 
+	.macro	copy_u_w	rd, ws, n
 
+	.set	push
 
+	.set	mips32r2
 
+	.set	msa
 
+	copy_u.w \rd, $w\ws[\n]
 
+	.set	pop
 
+	.endm
 
+
 
+	.macro	copy_u_d	rd, ws, n
 
+	.set	push
 
+	.set	mips64r2
 
+	.set	msa
 
+	copy_u.d \rd, $w\ws[\n]
 
+	.set	pop
 
+	.endm
 
+
 
+	.macro	insert_w	wd, n, rs
 
+	.set	push
 
+	.set	mips32r2
 
+	.set	msa
 
+	insert.w $w\wd[\n], \rs
 
+	.set	pop
 
+	.endm
 
+
 
+	.macro	insert_d	wd, n, rs
 
+	.set	push
 
+	.set	mips64r2
 
+	.set	msa
 
+	insert.d $w\wd[\n], \rs
 
+	.set	pop
 
+	.endm
 
+#else
 
+	/*
 
+	 * Temporary until all toolchains in use include MSA support.
 
+	 */
 
+	.macro	cfcmsa	rd, cs
 
+	.set	push
 
+	.set	noat
 
+	.word	0x787e0059 | (\cs << 11)
 
+	move	\rd, $1
 
+	.set	pop
 
+	.endm
 
+
 
+	.macro	ctcmsa	cd, rs
 
+	.set	push
 
+	.set	noat
 
+	move	$1, \rs
 
+	.word	0x783e0819 | (\cd << 6)
 
+	.set	pop
 
+	.endm
 
+
 
+	.macro	ld_d	wd, off, base
 
+	.set	push
 
+	.set	noat
 
+	add	$1, \base, \off
 
+	.word	0x78000823 | (\wd << 6)
 
+	.set	pop
 
+	.endm
 
+
 
+	.macro	st_d	wd, off, base
 
+	.set	push
 
+	.set	noat
 
+	add	$1, \base, \off
 
+	.word	0x78000827 | (\wd << 6)
 
+	.set	pop
 
+	.endm
 
+
 
+	.macro	copy_u_w	rd, ws, n
 
+	.set	push
 
+	.set	noat
 
+	.word	0x78f00059 | (\n << 16) | (\ws << 11)
 
+	/* move triggers an assembler bug... */
 
+	or	\rd, $1, zero
 
+	.set	pop
 
+	.endm
 
+
 
+	.macro	copy_u_d	rd, ws, n
 
+	.set	push
 
+	.set	noat
 
+	.word	0x78f80059 | (\n << 16) | (\ws << 11)
 
+	/* move triggers an assembler bug... */
 
+	or	\rd, $1, zero
 
+	.set	pop
 
+	.endm
 
+
 
+	.macro	insert_w	wd, n, rs
 
+	.set	push
 
+	.set	noat
 
+	/* move triggers an assembler bug... */
 
+	or	$1, \rs, zero
 
+	.word	0x79300819 | (\n << 16) | (\wd << 6)
 
+	.set	pop
 
+	.endm
 
+
 
+	.macro	insert_d	wd, n, rs
 
+	.set	push
 
+	.set	noat
 
+	/* move triggers an assembler bug... */
 
+	or	$1, \rs, zero
 
+	.word	0x79380819 | (\n << 16) | (\wd << 6)
 
+	.set	pop
 
+	.endm
 
+#endif
 
+
 
+	.macro	msa_save_all	thread
 
+	st_d	0, THREAD_FPR0, \thread
 
+	st_d	1, THREAD_FPR1, \thread
 
+	st_d	2, THREAD_FPR2, \thread
 
+	st_d	3, THREAD_FPR3, \thread
 
+	st_d	4, THREAD_FPR4, \thread
 
+	st_d	5, THREAD_FPR5, \thread
 
+	st_d	6, THREAD_FPR6, \thread
 
+	st_d	7, THREAD_FPR7, \thread
 
+	st_d	8, THREAD_FPR8, \thread
 
+	st_d	9, THREAD_FPR9, \thread
 
+	st_d	10, THREAD_FPR10, \thread
 
+	st_d	11, THREAD_FPR11, \thread
 
+	st_d	12, THREAD_FPR12, \thread
 
+	st_d	13, THREAD_FPR13, \thread
 
+	st_d	14, THREAD_FPR14, \thread
 
+	st_d	15, THREAD_FPR15, \thread
 
+	st_d	16, THREAD_FPR16, \thread
 
+	st_d	17, THREAD_FPR17, \thread
 
+	st_d	18, THREAD_FPR18, \thread
 
+	st_d	19, THREAD_FPR19, \thread
 
+	st_d	20, THREAD_FPR20, \thread
 
+	st_d	21, THREAD_FPR21, \thread
 
+	st_d	22, THREAD_FPR22, \thread
 
+	st_d	23, THREAD_FPR23, \thread
 
+	st_d	24, THREAD_FPR24, \thread
 
+	st_d	25, THREAD_FPR25, \thread
 
+	st_d	26, THREAD_FPR26, \thread
 
+	st_d	27, THREAD_FPR27, \thread
 
+	st_d	28, THREAD_FPR28, \thread
 
+	st_d	29, THREAD_FPR29, \thread
 
+	st_d	30, THREAD_FPR30, \thread
 
+	st_d	31, THREAD_FPR31, \thread
 
+	.endm
 
+
 
+	.macro	msa_restore_all	thread
 
+	ld_d	0, THREAD_FPR0, \thread
 
+	ld_d	1, THREAD_FPR1, \thread
 
+	ld_d	2, THREAD_FPR2, \thread
 
+	ld_d	3, THREAD_FPR3, \thread
 
+	ld_d	4, THREAD_FPR4, \thread
 
+	ld_d	5, THREAD_FPR5, \thread
 
+	ld_d	6, THREAD_FPR6, \thread
 
+	ld_d	7, THREAD_FPR7, \thread
 
+	ld_d	8, THREAD_FPR8, \thread
 
+	ld_d	9, THREAD_FPR9, \thread
 
+	ld_d	10, THREAD_FPR10, \thread
 
+	ld_d	11, THREAD_FPR11, \thread
 
+	ld_d	12, THREAD_FPR12, \thread
 
+	ld_d	13, THREAD_FPR13, \thread
 
+	ld_d	14, THREAD_FPR14, \thread
 
+	ld_d	15, THREAD_FPR15, \thread
 
+	ld_d	16, THREAD_FPR16, \thread
 
+	ld_d	17, THREAD_FPR17, \thread
 
+	ld_d	18, THREAD_FPR18, \thread
 
+	ld_d	19, THREAD_FPR19, \thread
 
+	ld_d	20, THREAD_FPR20, \thread
 
+	ld_d	21, THREAD_FPR21, \thread
 
+	ld_d	22, THREAD_FPR22, \thread
 
+	ld_d	23, THREAD_FPR23, \thread
 
+	ld_d	24, THREAD_FPR24, \thread
 
+	ld_d	25, THREAD_FPR25, \thread
 
+	ld_d	26, THREAD_FPR26, \thread
 
+	ld_d	27, THREAD_FPR27, \thread
 
+	ld_d	28, THREAD_FPR28, \thread
 
+	ld_d	29, THREAD_FPR29, \thread
 
+	ld_d	30, THREAD_FPR30, \thread
 
+	ld_d	31, THREAD_FPR31, \thread
 
+	.endm
 
+
 
 #endif /* _ASM_ASMMACRO_H */
 
 #endif /* _ASM_ASMMACRO_H */

+ 20 - 20
arch/mips/include/asm/atomic.h
Vizualizați fișierul 

@@ -53,7 +53,7 @@ static __inline__ void atomic_add(int i, atomic_t * v)
 
 		int temp;
 
 		int temp;
 
 
 
 		__asm__ __volatile__(
 
 		__asm__ __volatile__(
 
-		"	.set	mips3					\n"
 
+		"	.set	arch=r4000				\n"
 
 		"1:	ll	%0, %1		# atomic_add		\n"
 
 		"1:	ll	%0, %1		# atomic_add		\n"
 
 		"	addu	%0, %2					\n"
 
 		"	addu	%0, %2					\n"
 
 		"	sc	%0, %1					\n"
 
 		"	sc	%0, %1					\n"
 
@@ -66,7 +66,7 @@ static __inline__ void atomic_add(int i, atomic_t * v)
 
 
 
 		do {
 
 		do {
 
 			__asm__ __volatile__(
 
 			__asm__ __volatile__(
 
-			"	.set	mips3				\n"
 
+			"	.set	arch=r4000			\n"
 
 			"	ll	%0, %1		# atomic_add	\n"
 
 			"	ll	%0, %1		# atomic_add	\n"
 
 			"	addu	%0, %2				\n"
 
 			"	addu	%0, %2				\n"
 
 			"	sc	%0, %1				\n"
 
 			"	sc	%0, %1				\n"
 
@@ -96,7 +96,7 @@ static __inline__ void atomic_sub(int i, atomic_t * v)
 
 		int temp;
 
 		int temp;
 
 
 
 		__asm__ __volatile__(
 
 		__asm__ __volatile__(
 
-		"	.set	mips3					\n"
 
+		"	.set	arch=r4000				\n"
 
 		"1:	ll	%0, %1		# atomic_sub		\n"
 
 		"1:	ll	%0, %1		# atomic_sub		\n"
 
 		"	subu	%0, %2					\n"
 
 		"	subu	%0, %2					\n"
 
 		"	sc	%0, %1					\n"
 
 		"	sc	%0, %1					\n"
 
@@ -109,7 +109,7 @@ static __inline__ void atomic_sub(int i, atomic_t * v)
 
 
 
 		do {
 
 		do {
 
 			__asm__ __volatile__(
 
 			__asm__ __volatile__(
 
-			"	.set	mips3				\n"
 
+			"	.set	arch=r4000			\n"
 
 			"	ll	%0, %1		# atomic_sub	\n"
 
 			"	ll	%0, %1		# atomic_sub	\n"
 
 			"	subu	%0, %2				\n"
 
 			"	subu	%0, %2				\n"
 
 			"	sc	%0, %1				\n"
 
 			"	sc	%0, %1				\n"
 
@@ -139,7 +139,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
 
 		int temp;
 
 		int temp;
 
 
 
 		__asm__ __volatile__(
 
 		__asm__ __volatile__(
 
-		"	.set	mips3					\n"
 
+		"	.set	arch=r4000				\n"
 
 		"1:	ll	%1, %2		# atomic_add_return	\n"
 
 		"1:	ll	%1, %2		# atomic_add_return	\n"
 
 		"	addu	%0, %1, %3				\n"
 
 		"	addu	%0, %1, %3				\n"
 
 		"	sc	%0, %2					\n"
 
 		"	sc	%0, %2					\n"
 
@@ -153,7 +153,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
 
 
 
 		do {
 
 		do {
 
 			__asm__ __volatile__(
 
 			__asm__ __volatile__(
 
-			"	.set	mips3				\n"
 
+			"	.set	arch=r4000			\n"
 
 			"	ll	%1, %2	# atomic_add_return	\n"
 
 			"	ll	%1, %2	# atomic_add_return	\n"
 
 			"	addu	%0, %1, %3			\n"
 
 			"	addu	%0, %1, %3			\n"
 
 			"	sc	%0, %2				\n"
 
 			"	sc	%0, %2				\n"
 
@@ -188,7 +188,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
 
 		int temp;
 
 		int temp;
 
 
 
 		__asm__ __volatile__(
 
 		__asm__ __volatile__(
 
-		"	.set	mips3					\n"
 
+		"	.set	arch=r4000				\n"
 
 		"1:	ll	%1, %2		# atomic_sub_return	\n"
 
 		"1:	ll	%1, %2		# atomic_sub_return	\n"
 
 		"	subu	%0, %1, %3				\n"
 
 		"	subu	%0, %1, %3				\n"
 
 		"	sc	%0, %2					\n"
 
 		"	sc	%0, %2					\n"
 
@@ -205,7 +205,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
 
 
 
 		do {
 
 		do {
 
 			__asm__ __volatile__(
 
 			__asm__ __volatile__(
 
-			"	.set	mips3				\n"
 
+			"	.set	arch=r4000			\n"
 
 			"	ll	%1, %2	# atomic_sub_return	\n"
 
 			"	ll	%1, %2	# atomic_sub_return	\n"
 
 			"	subu	%0, %1, %3			\n"
 
 			"	subu	%0, %1, %3			\n"
 
 			"	sc	%0, %2				\n"
 
 			"	sc	%0, %2				\n"
 
@@ -248,7 +248,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
 
 		int temp;
 
 		int temp;
 
 
 
 		__asm__ __volatile__(
 
 		__asm__ __volatile__(
 
-		"	.set	mips3					\n"
 
+		"	.set	arch=r4000				\n"
 
 		"1:	ll	%1, %2		# atomic_sub_if_positive\n"
 
 		"1:	ll	%1, %2		# atomic_sub_if_positive\n"
 
 		"	subu	%0, %1, %3				\n"
 
 		"	subu	%0, %1, %3				\n"
 
 		"	bltz	%0, 1f					\n"
 
 		"	bltz	%0, 1f					\n"
 
@@ -266,7 +266,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
 
 		int temp;
 
 		int temp;
 
 
 
 		__asm__ __volatile__(
 
 		__asm__ __volatile__(
 
-		"	.set	mips3					\n"
 
+		"	.set	arch=r4000				\n"
 
 		"1:	ll	%1, %2		# atomic_sub_if_positive\n"
 
 		"1:	ll	%1, %2		# atomic_sub_if_positive\n"
 
 		"	subu	%0, %1, %3				\n"
 
 		"	subu	%0, %1, %3				\n"
 
 		"	bltz	%0, 1f					\n"
 
 		"	bltz	%0, 1f					\n"
 
@@ -420,7 +420,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
 
 		long temp;
 
 		long temp;
 
 
 
 		__asm__ __volatile__(
 
 		__asm__ __volatile__(
 
-		"	.set	mips3					\n"
 
+		"	.set	arch=r4000				\n"
 
 		"1:	lld	%0, %1		# atomic64_add		\n"
 
 		"1:	lld	%0, %1		# atomic64_add		\n"
 
 		"	daddu	%0, %2					\n"
 
 		"	daddu	%0, %2					\n"
 
 		"	scd	%0, %1					\n"
 
 		"	scd	%0, %1					\n"
 
@@ -433,7 +433,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
 
 
 
 		do {
 
 		do {
 
 			__asm__ __volatile__(
 
 			__asm__ __volatile__(
 
-			"	.set	mips3				\n"
 
+			"	.set	arch=r4000			\n"
 
 			"	lld	%0, %1		# atomic64_add	\n"
 
 			"	lld	%0, %1		# atomic64_add	\n"
 
 			"	daddu	%0, %2				\n"
 
 			"	daddu	%0, %2				\n"
 
 			"	scd	%0, %1				\n"
 
 			"	scd	%0, %1				\n"
 
@@ -463,7 +463,7 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
 
 		long temp;
 
 		long temp;
 
 
 
 		__asm__ __volatile__(
 
 		__asm__ __volatile__(
 
-		"	.set	mips3					\n"
 
+		"	.set	arch=r4000				\n"
 
 		"1:	lld	%0, %1		# atomic64_sub		\n"
 
 		"1:	lld	%0, %1		# atomic64_sub		\n"
 
 		"	dsubu	%0, %2					\n"
 
 		"	dsubu	%0, %2					\n"
 
 		"	scd	%0, %1					\n"
 
 		"	scd	%0, %1					\n"
 
@@ -476,7 +476,7 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
 
 
 
 		do {
 
 		do {
 
 			__asm__ __volatile__(
 
 			__asm__ __volatile__(
 
-			"	.set	mips3				\n"
 
+			"	.set	arch=r4000			\n"
 
 			"	lld	%0, %1		# atomic64_sub	\n"
 
 			"	lld	%0, %1		# atomic64_sub	\n"
 
 			"	dsubu	%0, %2				\n"
 
 			"	dsubu	%0, %2				\n"
 
 			"	scd	%0, %1				\n"
 
 			"	scd	%0, %1				\n"
 
@@ -506,7 +506,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
 
 		long temp;
 
 		long temp;
 
 
 
 		__asm__ __volatile__(
 
 		__asm__ __volatile__(
 
-		"	.set	mips3					\n"
 
+		"	.set	arch=r4000				\n"
 
 		"1:	lld	%1, %2		# atomic64_add_return	\n"
 
 		"1:	lld	%1, %2		# atomic64_add_return	\n"
 
 		"	daddu	%0, %1, %3				\n"
 
 		"	daddu	%0, %1, %3				\n"
 
 		"	scd	%0, %2					\n"
 
 		"	scd	%0, %2					\n"
 
@@ -520,7 +520,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
 
 
 
 		do {
 
 		do {
 
 			__asm__ __volatile__(
 
 			__asm__ __volatile__(
 
-			"	.set	mips3				\n"
 
+			"	.set	arch=r4000			\n"
 
 			"	lld	%1, %2	# atomic64_add_return	\n"
 
 			"	lld	%1, %2	# atomic64_add_return	\n"
 
 			"	daddu	%0, %1, %3			\n"
 
 			"	daddu	%0, %1, %3			\n"
 
 			"	scd	%0, %2				\n"
 
 			"	scd	%0, %2				\n"
 
@@ -556,7 +556,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
 
 		long temp;
 
 		long temp;
 
 
 
 		__asm__ __volatile__(
 
 		__asm__ __volatile__(
 
-		"	.set	mips3					\n"
 
+		"	.set	arch=r4000				\n"
 
 		"1:	lld	%1, %2		# atomic64_sub_return	\n"
 
 		"1:	lld	%1, %2		# atomic64_sub_return	\n"
 
 		"	dsubu	%0, %1, %3				\n"
 
 		"	dsubu	%0, %1, %3				\n"
 
 		"	scd	%0, %2					\n"
 
 		"	scd	%0, %2					\n"
 
@@ -571,7 +571,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
 
 
 
 		do {
 
 		do {
 
 			__asm__ __volatile__(
 
 			__asm__ __volatile__(
 
-			"	.set	mips3				\n"
 
+			"	.set	arch=r4000			\n"
 
 			"	lld	%1, %2	# atomic64_sub_return	\n"
 
 			"	lld	%1, %2	# atomic64_sub_return	\n"
 
 			"	dsubu	%0, %1, %3			\n"
 
 			"	dsubu	%0, %1, %3			\n"
 
 			"	scd	%0, %2				\n"
 
 			"	scd	%0, %2				\n"
 
@@ -615,7 +615,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
 
 		long temp;
 
 		long temp;
 
 
 
 		__asm__ __volatile__(
 
 		__asm__ __volatile__(
 
-		"	.set	mips3					\n"
 
+		"	.set	arch=r4000				\n"
 
 		"1:	lld	%1, %2		# atomic64_sub_if_positive\n"
 
 		"1:	lld	%1, %2		# atomic64_sub_if_positive\n"
 
 		"	dsubu	%0, %1, %3				\n"
 
 		"	dsubu	%0, %1, %3				\n"
 
 		"	bltz	%0, 1f					\n"
 
 		"	bltz	%0, 1f					\n"
 
@@ -633,7 +633,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
 
 		long temp;
 
 		long temp;
 
 
 
 		__asm__ __volatile__(
 
 		__asm__ __volatile__(
 
-		"	.set	mips3					\n"
 
+		"	.set	arch=r4000				\n"
 
 		"1:	lld	%1, %2		# atomic64_sub_if_positive\n"
 
 		"1:	lld	%1, %2		# atomic64_sub_if_positive\n"
 
 		"	dsubu	%0, %1, %3				\n"
 
 		"	dsubu	%0, %1, %3				\n"
 
 		"	bltz	%0, 1f					\n"
 
 		"	bltz	%0, 1f					\n"

+ 14 - 14
arch/mips/include/asm/bitops.h
Vizualizați fișierul 

@@ -79,7 +79,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
 
 
 
 	if (kernel_uses_llsc && R10000_LLSC_WAR) {
 
 	if (kernel_uses_llsc && R10000_LLSC_WAR) {
 
 		__asm__ __volatile__(
 
 		__asm__ __volatile__(
 
-		"	.set	mips3					\n"
 
+		"	.set	arch=r4000				\n"
 
 		"1:	" __LL "%0, %1			# set_bit	\n"
 
 		"1:	" __LL "%0, %1			# set_bit	\n"
 
 		"	or	%0, %2					\n"
 
 		"	or	%0, %2					\n"
 
 		"	" __SC	"%0, %1					\n"
 
 		"	" __SC	"%0, %1					\n"
 
@@ -101,7 +101,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
 
 	} else if (kernel_uses_llsc) {
 
 	} else if (kernel_uses_llsc) {
 
 		do {
 
 		do {
 
 			__asm__ __volatile__(
 
 			__asm__ __volatile__(
 
-			"	.set	mips3				\n"
 
+			"	.set	arch=r4000			\n"
 
 			"	" __LL "%0, %1		# set_bit	\n"
 
 			"	" __LL "%0, %1		# set_bit	\n"
 
 			"	or	%0, %2				\n"
 
 			"	or	%0, %2				\n"
 
 			"	" __SC	"%0, %1				\n"
 
 			"	" __SC	"%0, %1				\n"
 
@@ -131,7 +131,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
 
 
 
 	if (kernel_uses_llsc && R10000_LLSC_WAR) {
 
 	if (kernel_uses_llsc && R10000_LLSC_WAR) {
 
 		__asm__ __volatile__(
 
 		__asm__ __volatile__(
 
-		"	.set	mips3					\n"
 
+		"	.set	arch=r4000				\n"
 
 		"1:	" __LL "%0, %1			# clear_bit	\n"
 
 		"1:	" __LL "%0, %1			# clear_bit	\n"
 
 		"	and	%0, %2					\n"
 
 		"	and	%0, %2					\n"
 
 		"	" __SC "%0, %1					\n"
 
 		"	" __SC "%0, %1					\n"
 
@@ -153,7 +153,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
 
 	} else if (kernel_uses_llsc) {
 
 	} else if (kernel_uses_llsc) {
 
 		do {
 
 		do {
 
 			__asm__ __volatile__(
 
 			__asm__ __volatile__(
 
-			"	.set	mips3				\n"
 
+			"	.set	arch=r4000			\n"
 
 			"	" __LL "%0, %1		# clear_bit	\n"
 
 			"	" __LL "%0, %1		# clear_bit	\n"
 
 			"	and	%0, %2				\n"
 
 			"	and	%0, %2				\n"
 
 			"	" __SC "%0, %1				\n"
 
 			"	" __SC "%0, %1				\n"
 
@@ -197,7 +197,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
 
 		unsigned long temp;
 
 		unsigned long temp;
 
 
 
 		__asm__ __volatile__(
 
 		__asm__ __volatile__(
 
-		"	.set	mips3				\n"
 
+		"	.set	arch=r4000			\n"
 
 		"1:	" __LL "%0, %1		# change_bit	\n"
 
 		"1:	" __LL "%0, %1		# change_bit	\n"
 
 		"	xor	%0, %2				\n"
 
 		"	xor	%0, %2				\n"
 
 		"	" __SC	"%0, %1				\n"
 
 		"	" __SC	"%0, %1				\n"
 
@@ -211,7 +211,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
 
 
 
 		do {
 
 		do {
 
 			__asm__ __volatile__(
 
 			__asm__ __volatile__(
 
-			"	.set	mips3				\n"
 
+			"	.set	arch=r4000			\n"
 
 			"	" __LL "%0, %1		# change_bit	\n"
 
 			"	" __LL "%0, %1		# change_bit	\n"
 
 			"	xor	%0, %2				\n"
 
 			"	xor	%0, %2				\n"
 
 			"	" __SC	"%0, %1				\n"
 
 			"	" __SC	"%0, %1				\n"
 
@@ -244,7 +244,7 @@ static inline int test_and_set_bit(unsigned long nr,
 
 		unsigned long temp;
 
 		unsigned long temp;
 
 
 
 		__asm__ __volatile__(
 
 		__asm__ __volatile__(
 
-		"	.set	mips3					\n"
 
+		"	.set	arch=r4000				\n"
 
 		"1:	" __LL "%0, %1		# test_and_set_bit	\n"
 
 		"1:	" __LL "%0, %1		# test_and_set_bit	\n"
 
 		"	or	%2, %0, %3				\n"
 
 		"	or	%2, %0, %3				\n"
 
 		"	" __SC	"%2, %1					\n"
 
 		"	" __SC	"%2, %1					\n"
 
@@ -260,7 +260,7 @@ static inline int test_and_set_bit(unsigned long nr,
 
 
 
 		do {
 
 		do {
 
 			__asm__ __volatile__(
 
 			__asm__ __volatile__(
 
-			"	.set	mips3				\n"
 
+			"	.set	arch=r4000			\n"
 
 			"	" __LL "%0, %1	# test_and_set_bit	\n"
 
 			"	" __LL "%0, %1	# test_and_set_bit	\n"
 
 			"	or	%2, %0, %3			\n"
 
 			"	or	%2, %0, %3			\n"
 
 			"	" __SC	"%2, %1				\n"
 
 			"	" __SC	"%2, %1				\n"
 
@@ -298,7 +298,7 @@ static inline int test_and_set_bit_lock(unsigned long nr,
 
 		unsigned long temp;
 
 		unsigned long temp;
 
 
 
 		__asm__ __volatile__(
 
 		__asm__ __volatile__(
 
-		"	.set	mips3					\n"
 
+		"	.set	arch=r4000				\n"
 
 		"1:	" __LL "%0, %1		# test_and_set_bit	\n"
 
 		"1:	" __LL "%0, %1		# test_and_set_bit	\n"
 
 		"	or	%2, %0, %3				\n"
 
 		"	or	%2, %0, %3				\n"
 
 		"	" __SC	"%2, %1					\n"
 
 		"	" __SC	"%2, %1					\n"
 
@@ -314,7 +314,7 @@ static inline int test_and_set_bit_lock(unsigned long nr,
 
 
 
 		do {
 
 		do {
 
 			__asm__ __volatile__(
 
 			__asm__ __volatile__(
 
-			"	.set	mips3				\n"
 
+			"	.set	arch=r4000			\n"
 
 			"	" __LL "%0, %1	# test_and_set_bit	\n"
 
 			"	" __LL "%0, %1	# test_and_set_bit	\n"
 
 			"	or	%2, %0, %3			\n"
 
 			"	or	%2, %0, %3			\n"
 
 			"	" __SC	"%2, %1				\n"
 
 			"	" __SC	"%2, %1				\n"
 
@@ -353,7 +353,7 @@ static inline int test_and_clear_bit(unsigned long nr,
 
 		unsigned long temp;
 
 		unsigned long temp;
 
 
 
 		__asm__ __volatile__(
 
 		__asm__ __volatile__(
 
-		"	.set	mips3					\n"
 
+		"	.set	arch=r4000				\n"
 
 		"1:	" __LL	"%0, %1		# test_and_clear_bit	\n"
 
 		"1:	" __LL	"%0, %1		# test_and_clear_bit	\n"
 
 		"	or	%2, %0, %3				\n"
 
 		"	or	%2, %0, %3				\n"
 
 		"	xor	%2, %3					\n"
 
 		"	xor	%2, %3					\n"
 
@@ -386,7 +386,7 @@ static inline int test_and_clear_bit(unsigned long nr,
 
 
 
 		do {
 
 		do {
 
 			__asm__ __volatile__(
 
 			__asm__ __volatile__(
 
-			"	.set	mips3				\n"
 
+			"	.set	arch=r4000			\n"
 
 			"	" __LL	"%0, %1 # test_and_clear_bit	\n"
 
 			"	" __LL	"%0, %1 # test_and_clear_bit	\n"
 
 			"	or	%2, %0, %3			\n"
 
 			"	or	%2, %0, %3			\n"
 
 			"	xor	%2, %3				\n"
 
 			"	xor	%2, %3				\n"
 
@@ -427,7 +427,7 @@ static inline int test_and_change_bit(unsigned long nr,
 
 		unsigned long temp;
 
 		unsigned long temp;
 
 
 
 		__asm__ __volatile__(
 
 		__asm__ __volatile__(
 
-		"	.set	mips3					\n"
 
+		"	.set	arch=r4000				\n"
 
 		"1:	" __LL	"%0, %1		# test_and_change_bit	\n"
 
 		"1:	" __LL	"%0, %1		# test_and_change_bit	\n"
 
 		"	xor	%2, %0, %3				\n"
 
 		"	xor	%2, %0, %3				\n"
 
 		"	" __SC	"%2, %1					\n"
 
 		"	" __SC	"%2, %1					\n"
 
@@ -443,7 +443,7 @@ static inline int test_and_change_bit(unsigned long nr,
 
 
 
 		do {
 
 		do {
 
 			__asm__ __volatile__(
 
 			__asm__ __volatile__(
 
-			"	.set	mips3				\n"
 
+			"	.set	arch=r4000			\n"
 
 			"	" __LL	"%0, %1 # test_and_change_bit	\n"
 
 			"	" __LL	"%0, %1 # test_and_change_bit	\n"
 
 			"	xor	%2, %0, %3			\n"
 
 			"	xor	%2, %0, %3			\n"
 
 			"	" __SC	"\t%2, %1			\n"
 
 			"	" __SC	"\t%2, %1			\n"

+ 17 - 9
arch/mips/include/asm/bootinfo.h
Vizualizați fișierul 

@@ -61,15 +61,21 @@
 
 /*
 
 /*
 
  * Valid machtype for Loongson family
 
  * Valid machtype for Loongson family
 
  */
 
  */
 
-#define MACH_LOONGSON_UNKNOWN  0
 
-#define MACH_LEMOTE_FL2E       1
 
-#define MACH_LEMOTE_FL2F       2
 
-#define MACH_LEMOTE_ML2F7      3
 
-#define MACH_LEMOTE_YL2F89     4
 
-#define MACH_DEXXON_GDIUM2F10  5
 
-#define MACH_LEMOTE_NAS	       6
 
-#define MACH_LEMOTE_LL2F       7
 
-#define MACH_LOONGSON_END      8
 
+enum loongson_machine_type {
 
+	MACH_LOONGSON_UNKNOWN,
 
+	MACH_LEMOTE_FL2E,
 
+	MACH_LEMOTE_FL2F,
 
+	MACH_LEMOTE_ML2F7,
 
+	MACH_LEMOTE_YL2F89,
 
+	MACH_DEXXON_GDIUM2F10,
 
+	MACH_LEMOTE_NAS,
 
+	MACH_LEMOTE_LL2F,
 
+	MACH_LEMOTE_A1004,
 
+	MACH_LEMOTE_A1101,
 
+	MACH_LEMOTE_A1201,
 
+	MACH_LEMOTE_A1205,
 
+	MACH_LOONGSON_END
 
+};
 
 
 
 /*
 
 /*
 
  * Valid machtype for group INGENIC
 
  * Valid machtype for group INGENIC
 
@@ -112,6 +118,8 @@ extern void prom_free_prom_memory(void);
 
 extern void free_init_pages(const char *what,
 
 extern void free_init_pages(const char *what,
 
 			    unsigned long begin, unsigned long end);
 
 			    unsigned long begin, unsigned long end);
 
 
 
+extern void (*free_init_pages_eva)(void *begin, void *end);
 
+
 
 /*
 
 /*
 
  * Initial kernel command line, usually setup by prom_init()
 
  * Initial kernel command line, usually setup by prom_init()
 
  */
 
  */

+ 37 - 7
arch/mips/include/asm/checksum.h
Vizualizați fișierul 

@@ -7,6 +7,7 @@
 
  * Copyright (C) 1999 Silicon Graphics, Inc.
 
  * Copyright (C) 1999 Silicon Graphics, Inc.
 
  * Copyright (C) 2001 Thiemo Seufer.
 
  * Copyright (C) 2001 Thiemo Seufer.
 
  * Copyright (C) 2002 Maciej W. Rozycki
 
  * Copyright (C) 2002 Maciej W. Rozycki
 
+ * Copyright (C) 2014 Imagination Technologies Ltd.
 
  */
 
  */
 
 #ifndef _ASM_CHECKSUM_H
 
 #ifndef _ASM_CHECKSUM_H
 
 #define _ASM_CHECKSUM_H
 
 #define _ASM_CHECKSUM_H
 
@@ -29,9 +30,13 @@
 
  */
 
  */
 
 __wsum csum_partial(const void *buff, int len, __wsum sum);
 
 __wsum csum_partial(const void *buff, int len, __wsum sum);
 
 
 
-__wsum __csum_partial_copy_user(const void *src, void *dst,
 
-				int len, __wsum sum, int *err_ptr);
 
+__wsum __csum_partial_copy_kernel(const void *src, void *dst,
 
+				  int len, __wsum sum, int *err_ptr);
 
 
 
+__wsum __csum_partial_copy_from_user(const void *src, void *dst,
 
+				     int len, __wsum sum, int *err_ptr);
 
+__wsum __csum_partial_copy_to_user(const void *src, void *dst,
 
+				   int len, __wsum sum, int *err_ptr);
 
 /*
 
 /*
 
  * this is a new version of the above that records errors it finds in *errp,
 
  * this is a new version of the above that records errors it finds in *errp,
 
  * but continues and zeros the rest of the buffer.
 
  * but continues and zeros the rest of the buffer.
 
@@ -41,8 +46,26 @@ __wsum csum_partial_copy_from_user(const void __user *src, void *dst, int len,
 
 				   __wsum sum, int *err_ptr)
 
 				   __wsum sum, int *err_ptr)
 
 {
 
 {
 
 	might_fault();
 
 	might_fault();
 
-	return __csum_partial_copy_user((__force void *)src, dst,
 
-					len, sum, err_ptr);
 
+	if (segment_eq(get_fs(), get_ds()))
 
+		return __csum_partial_copy_kernel((__force void *)src, dst,
 
+						  len, sum, err_ptr);
 
+	else
 
+		return __csum_partial_copy_from_user((__force void *)src, dst,
 
+						     len, sum, err_ptr);
 
+}
 
+
 
+#define _HAVE_ARCH_COPY_AND_CSUM_FROM_USER
 
+static inline
 
+__wsum csum_and_copy_from_user(const void __user *src, void *dst,
 
+			       int len, __wsum sum, int *err_ptr)
 
+{
 
+	if (access_ok(VERIFY_READ, src, len))
 
+		return csum_partial_copy_from_user(src, dst, len, sum,
 
+						   err_ptr);
 
+	if (len)
 
+		*err_ptr = -EFAULT;
 
+
 
+	return sum;
 
 }
 
 }
 
 
 
 /*
 
 /*
 
@@ -54,9 +77,16 @@ __wsum csum_and_copy_to_user(const void *src, void __user *dst, int len,
 
 			     __wsum sum, int *err_ptr)
 
 			     __wsum sum, int *err_ptr)
 
 {
 
 {
 
 	might_fault();
 
 	might_fault();
 
-	if (access_ok(VERIFY_WRITE, dst, len))
 
-		return __csum_partial_copy_user(src, (__force void *)dst,
 
-						len, sum, err_ptr);
 
+	if (access_ok(VERIFY_WRITE, dst, len)) {
 
+		if (segment_eq(get_fs(), get_ds()))
 
+			return __csum_partial_copy_kernel(src,
 
+							  (__force void *)dst,
 
+							  len, sum, err_ptr);
 
+		else
 
+			return __csum_partial_copy_to_user(src,
 
+							   (__force void *)dst,
 
+							   len, sum, err_ptr);
 
+	}
 
 	if (len)
 
 	if (len)
 
 		*err_ptr = -EFAULT;
 
 		*err_ptr = -EFAULT;

+ 10 - 10
arch/mips/include/asm/cmpxchg.h
Vizualizați fișierul 

@@ -22,11 +22,11 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
 
 		unsigned long dummy;
 
 		unsigned long dummy;
 
 
 
 		__asm__ __volatile__(
 
 		__asm__ __volatile__(
 
-		"	.set	mips3					\n"
 
+		"	.set	arch=r4000				\n"
 
 		"1:	ll	%0, %3			# xchg_u32	\n"
 
 		"1:	ll	%0, %3			# xchg_u32	\n"
 
 		"	.set	mips0					\n"
 
 		"	.set	mips0					\n"
 
 		"	move	%2, %z4					\n"
 
 		"	move	%2, %z4					\n"
 
-		"	.set	mips3					\n"
 
+		"	.set	arch=r4000				\n"
 
 		"	sc	%2, %1					\n"
 
 		"	sc	%2, %1					\n"
 
 		"	beqzl	%2, 1b					\n"
 
 		"	beqzl	%2, 1b					\n"
 
 		"	.set	mips0					\n"
 
 		"	.set	mips0					\n"
 
@@ -38,11 +38,11 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
 
 
 
 		do {
 
 		do {
 
 			__asm__ __volatile__(
 
 			__asm__ __volatile__(
 
-			"	.set	mips3				\n"
 
+			"	.set	arch=r4000			\n"
 
 			"	ll	%0, %3		# xchg_u32	\n"
 
 			"	ll	%0, %3		# xchg_u32	\n"
 
 			"	.set	mips0				\n"
 
 			"	.set	mips0				\n"
 
 			"	move	%2, %z4				\n"
 
 			"	move	%2, %z4				\n"
 
-			"	.set	mips3				\n"
 
+			"	.set	arch=r4000			\n"
 
 			"	sc	%2, %1				\n"
 
 			"	sc	%2, %1				\n"
 
 			"	.set	mips0				\n"
 
 			"	.set	mips0				\n"
 
 			: "=&r" (retval), "=m" (*m), "=&r" (dummy)
 
 			: "=&r" (retval), "=m" (*m), "=&r" (dummy)
 
@@ -74,7 +74,7 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
 
 		unsigned long dummy;
 
 		unsigned long dummy;
 
 
 
 		__asm__ __volatile__(
 
 		__asm__ __volatile__(
 
-		"	.set	mips3					\n"
 
+		"	.set	arch=r4000				\n"
 
 		"1:	lld	%0, %3			# xchg_u64	\n"
 
 		"1:	lld	%0, %3			# xchg_u64	\n"
 
 		"	move	%2, %z4					\n"
 
 		"	move	%2, %z4					\n"
 
 		"	scd	%2, %1					\n"
 
 		"	scd	%2, %1					\n"
 
@@ -88,7 +88,7 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
 
 
 
 		do {
 
 		do {
 
 			__asm__ __volatile__(
 
 			__asm__ __volatile__(
 
-			"	.set	mips3				\n"
 
+			"	.set	arch=r4000			\n"
 
 			"	lld	%0, %3		# xchg_u64	\n"
 
 			"	lld	%0, %3		# xchg_u64	\n"
 
 			"	move	%2, %z4				\n"
 
 			"	move	%2, %z4				\n"
 
 			"	scd	%2, %1				\n"
 
 			"	scd	%2, %1				\n"
 
@@ -145,12 +145,12 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
 
 		__asm__ __volatile__(					\
 
 		__asm__ __volatile__(					\
 
 		"	.set	push				\n"	\
 
 		"	.set	push				\n"	\
 
 		"	.set	noat				\n"	\
 
 		"	.set	noat				\n"	\
 
-		"	.set	mips3				\n"	\
 
+		"	.set	arch=r4000			\n"	\
 
 		"1:	" ld "	%0, %2		# __cmpxchg_asm \n"	\
 
 		"1:	" ld "	%0, %2		# __cmpxchg_asm \n"	\
 
 		"	bne	%0, %z3, 2f			\n"	\
 
 		"	bne	%0, %z3, 2f			\n"	\
 
 		"	.set	mips0				\n"	\
 
 		"	.set	mips0				\n"	\
 
 		"	move	$1, %z4				\n"	\
 
 		"	move	$1, %z4				\n"	\
 
-		"	.set	mips3				\n"	\
 
+		"	.set	arch=r4000			\n"	\
 
 		"	" st "	$1, %1				\n"	\
 
 		"	" st "	$1, %1				\n"	\
 
 		"	beqzl	$1, 1b				\n"	\
 
 		"	beqzl	$1, 1b				\n"	\
 
 		"2:						\n"	\
 
 		"2:						\n"	\
 
@@ -162,12 +162,12 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
 
 		__asm__ __volatile__(					\
 
 		__asm__ __volatile__(					\
 
 		"	.set	push				\n"	\
 
 		"	.set	push				\n"	\
 
 		"	.set	noat				\n"	\
 
 		"	.set	noat				\n"	\
 
-		"	.set	mips3				\n"	\
 
+		"	.set	arch=r4000			\n"	\
 
 		"1:	" ld "	%0, %2		# __cmpxchg_asm \n"	\
 
 		"1:	" ld "	%0, %2		# __cmpxchg_asm \n"	\
 
 		"	bne	%0, %z3, 2f			\n"	\
 
 		"	bne	%0, %z3, 2f			\n"	\
 
 		"	.set	mips0				\n"	\
 
 		"	.set	mips0				\n"	\
 
 		"	move	$1, %z4				\n"	\
 
 		"	move	$1, %z4				\n"	\
 
-		"	.set	mips3				\n"	\
 
+		"	.set	arch=r4000			\n"	\
 
 		"	" st "	$1, %1				\n"	\
 
 		"	" st "	$1, %1				\n"	\
 
 		"	beqz	$1, 1b				\n"	\
 
 		"	beqz	$1, 1b				\n"	\
 
 		"	.set	pop				\n"	\
 
 		"	.set	pop				\n"	\

+ 9 - 1
arch/mips/include/asm/cpu-features.h
Vizualizați fișierul 

@@ -26,7 +26,9 @@
 
 #ifndef cpu_has_segments
 
 #ifndef cpu_has_segments
 
 #define cpu_has_segments	(cpu_data[0].options & MIPS_CPU_SEGMENTS)
 
 #define cpu_has_segments	(cpu_data[0].options & MIPS_CPU_SEGMENTS)
 
 #endif
 
 #endif
 
-
 
+#ifndef cpu_has_eva
 
+#define cpu_has_eva		(cpu_data[0].options & MIPS_CPU_EVA)
 
+#endif
 
 
 
 /*
 
 /*
 
  * For the moment we don't consider R6000 and R8000 so we can assume that
 
  * For the moment we don't consider R6000 and R8000 so we can assume that
 
@@ -299,4 +301,10 @@
 
 #define cpu_has_vz		(cpu_data[0].ases & MIPS_ASE_VZ)
 
 #define cpu_has_vz		(cpu_data[0].ases & MIPS_ASE_VZ)
 
 #endif
 
 #endif
 
 
 
+#if defined(CONFIG_CPU_HAS_MSA) && !defined(cpu_has_msa)
 
+# define cpu_has_msa		(cpu_data[0].ases & MIPS_ASE_MSA)
 
+#elif !defined(cpu_has_msa)
 
+# define cpu_has_msa		0
 
+#endif
 
+
 
 #endif /* __ASM_CPU_FEATURES_H */
 
 #endif /* __ASM_CPU_FEATURES_H */

+ 28 - 0
arch/mips/include/asm/cpu-info.h
Vizualizați fișierul 

@@ -49,6 +49,7 @@ struct cpuinfo_mips {
 
 	unsigned long		ases;
 
 	unsigned long		ases;
 
 	unsigned int		processor_id;
 
 	unsigned int		processor_id;
 
 	unsigned int		fpu_id;
 
 	unsigned int		fpu_id;
 
+	unsigned int		msa_id;
 
 	unsigned int		cputype;
 
 	unsigned int		cputype;
 
 	int			isa_level;
 
 	int			isa_level;
 
 	int			tlbsize;
 
 	int			tlbsize;
 
@@ -95,4 +96,31 @@ extern void cpu_report(void);
 
 extern const char *__cpu_name[];
 
 extern const char *__cpu_name[];
 
 #define cpu_name_string()	__cpu_name[smp_processor_id()]
 
 #define cpu_name_string()	__cpu_name[smp_processor_id()]
 
 
 
+struct seq_file;
 
+struct notifier_block;
 
+
 
+extern int register_proc_cpuinfo_notifier(struct notifier_block *nb);
 
+extern int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v);
 
+
 
+#define proc_cpuinfo_notifier(fn, pri)					\
 
+({									\
 
+	static struct notifier_block fn##_nb = {			\
 
+		.notifier_call = fn,					\
 
+		.priority = pri						\
 
+	};								\
 
+									\
 
+	register_proc_cpuinfo_notifier(&fn##_nb);			\
 
+})
 
+
 
+struct proc_cpuinfo_notifier_args {
 
+	struct seq_file *m;
 
+	unsigned long n;
 
+};
 
+
 
+#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
 
+# define cpu_vpe_id(cpuinfo)	((cpuinfo)->vpe_id)
 
+#else
 
+# define cpu_vpe_id(cpuinfo)	0
 
+#endif
 
+
 
 #endif /* __ASM_CPU_INFO_H */
 
 #endif /* __ASM_CPU_INFO_H */

+ 6 - 0
arch/mips/include/asm/cpu-type.h
Vizualizați fișierul 

@@ -20,6 +20,10 @@ static inline int __pure __get_cpu_type(const int cpu_type)
 
 	case CPU_LOONGSON2:
 
 	case CPU_LOONGSON2:
 
 #endif
 
 #endif
 
 
 
+#ifdef CONFIG_SYS_HAS_CPU_LOONGSON3
 
+	case CPU_LOONGSON3:
 
+#endif
 
+
 
 #ifdef CONFIG_SYS_HAS_CPU_LOONGSON1B
 
 #ifdef CONFIG_SYS_HAS_CPU_LOONGSON1B
 
 	case CPU_LOONGSON1:
 
 	case CPU_LOONGSON1:
 
 #endif
 
 #endif
 
@@ -46,6 +50,8 @@ static inline int __pure __get_cpu_type(const int cpu_type)
 
 	case CPU_M14KEC:
 
 	case CPU_M14KEC:
 
 	case CPU_INTERAPTIV:
 
 	case CPU_INTERAPTIV:
 
 	case CPU_PROAPTIV:
 
 	case CPU_PROAPTIV:
 
+	case CPU_P5600:
 
+	case CPU_M5150:
 
 #endif
 
 #endif
 
 
 
 #ifdef CONFIG_SYS_HAS_CPU_MIPS64_R1
 
 #ifdef CONFIG_SYS_HAS_CPU_MIPS64_R1

+ 10 - 5
arch/mips/include/asm/cpu.h
Vizualizați fișierul 

@@ -82,10 +82,10 @@
 
 #define PRID_IMP_RM7000		0x2700
 
 #define PRID_IMP_RM7000		0x2700
 
 #define PRID_IMP_NEVADA		0x2800		/* RM5260 ??? */
 
 #define PRID_IMP_NEVADA		0x2800		/* RM5260 ??? */
 
 #define PRID_IMP_RM9000		0x3400
 
 #define PRID_IMP_RM9000		0x3400
 
-#define PRID_IMP_LOONGSON1	0x4200
 
+#define PRID_IMP_LOONGSON_32	0x4200  /* Loongson-1 */
 
 #define PRID_IMP_R5432		0x5400
 
 #define PRID_IMP_R5432		0x5400
 
 #define PRID_IMP_R5500		0x5500
 
 #define PRID_IMP_R5500		0x5500
 
-#define PRID_IMP_LOONGSON2	0x6300
 
+#define PRID_IMP_LOONGSON_64	0x6300  /* Loongson-2/3 */
 
 
 
 #define PRID_IMP_UNKNOWN	0xff00
 
 #define PRID_IMP_UNKNOWN	0xff00
 
 
 
@@ -115,6 +115,8 @@
 
 #define PRID_IMP_INTERAPTIV_MP	0xa100
 
 #define PRID_IMP_INTERAPTIV_MP	0xa100
 
 #define PRID_IMP_PROAPTIV_UP	0xa200
 
 #define PRID_IMP_PROAPTIV_UP	0xa200
 
 #define PRID_IMP_PROAPTIV_MP	0xa300
 
 #define PRID_IMP_PROAPTIV_MP	0xa300
 
+#define PRID_IMP_M5150		0xa700
 
+#define PRID_IMP_P5600		0xa800
 
 
 
 /*
 
 /*
 
  * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
 
  * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
 
@@ -229,6 +231,7 @@
 
 #define PRID_REV_LOONGSON1B	0x0020
 
 #define PRID_REV_LOONGSON1B	0x0020
 
 #define PRID_REV_LOONGSON2E	0x0002
 
 #define PRID_REV_LOONGSON2E	0x0002
 
 #define PRID_REV_LOONGSON2F	0x0003
 
 #define PRID_REV_LOONGSON2F	0x0003
 
+#define PRID_REV_LOONGSON3A	0x0005
 
 
 
 /*
 
 /*
 
  * Older processors used to encode processor version and revision in two
 
  * Older processors used to encode processor version and revision in two
 
@@ -296,14 +299,14 @@ enum cpu_type_enum {
 
 	CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
 
 	CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
 
 	CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
 
 	CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
 
 	CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
 
 	CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
 
-	CPU_M14KEC, CPU_INTERAPTIV, CPU_PROAPTIV,
 
+	CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K, CPU_M5150,
 
 
 
 	/*
 
 	/*
 
 	 * MIPS64 class processors
 
 	 * MIPS64 class processors
 
 	 */
 
 	 */
 
 	CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
 
 	CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
 
-	CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
 
-	CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP,
 
+	CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
 
+	CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP,
 
 
 
 	CPU_LAST
 
 	CPU_LAST
 
 };
 
 };
 
@@ -358,6 +361,7 @@ enum cpu_type_enum {
 
 #define MIPS_CPU_MICROMIPS	0x01000000 /* CPU has microMIPS capability */
 
 #define MIPS_CPU_MICROMIPS	0x01000000 /* CPU has microMIPS capability */
 
 #define MIPS_CPU_TLBINV		0x02000000 /* CPU supports TLBINV/F */
 
 #define MIPS_CPU_TLBINV		0x02000000 /* CPU supports TLBINV/F */
 
 #define MIPS_CPU_SEGMENTS	0x04000000 /* CPU supports Segmentation Control registers */
 
 #define MIPS_CPU_SEGMENTS	0x04000000 /* CPU supports Segmentation Control registers */
 
+#define MIPS_CPU_EVA		0x80000000 /* CPU supports Enhanced Virtual Addressing */
 
 
 
 /*
 
 /*
 
  * CPU ASE encodings
 
  * CPU ASE encodings
 
@@ -370,5 +374,6 @@ enum cpu_type_enum {
 
 #define MIPS_ASE_MIPSMT		0x00000020 /* CPU supports MIPS MT */
 
 #define MIPS_ASE_MIPSMT		0x00000020 /* CPU supports MIPS MT */
 
 #define MIPS_ASE_DSP2P		0x00000040 /* Signal Processing ASE Rev 2 */
 
 #define MIPS_ASE_DSP2P		0x00000040 /* Signal Processing ASE Rev 2 */
 
 #define MIPS_ASE_VZ		0x00000080 /* Virtualization ASE */
 
 #define MIPS_ASE_VZ		0x00000080 /* Virtualization ASE */
 
+#define MIPS_ASE_MSA		0x00000100 /* MIPS SIMD Architecture */
 
 
 
 #endif /* _ASM_CPU_H */
 
 #endif /* _ASM_CPU_H */

+ 5 - 0
arch/mips/include/asm/dma-mapping.h
Vizualizați fișierul 

@@ -49,9 +49,14 @@ static inline int dma_mapping_error(struct device *dev, u64 mask)
 
 static inline int
 
 static inline int
 
 dma_set_mask(struct device *dev, u64 mask)
 
 dma_set_mask(struct device *dev, u64 mask)
 
 {
 
 {
 
+	struct dma_map_ops *ops = get_dma_ops(dev);
 
+
 
 	if(!dev->dma_mask || !dma_supported(dev, mask))
 
 	if(!dev->dma_mask || !dma_supported(dev, mask))
 
 		return -EIO;
 
 		return -EIO;
 
 
 
+	if (ops->set_dma_mask)
 
+		return ops->set_dma_mask(dev, mask);
 
+
 
 	*dev->dma_mask = mask;
 
 	*dev->dma_mask = mask;
 
 
 
 	return 0;
 
 	return 0;

+ 1 - 1
arch/mips/include/asm/fpu.h
Vizualizați fișierul 

@@ -180,7 +180,7 @@ static inline void restore_fp(struct task_struct *tsk)
 
 		_restore_fp(tsk);
 
 		_restore_fp(tsk);
 
 }
 
 }
 
 
 
-static inline fpureg_t *get_fpu_regs(struct task_struct *tsk)
 
+static inline union fpureg *get_fpu_regs(struct task_struct *tsk)
 
 {
 
 {
 
 	if (tsk == current) {
 
 	if (tsk == current) {
 
 		preempt_disable();
 
 		preempt_disable();

+ 13 - 12
arch/mips/include/asm/futex.h
Vizualizați fișierul 

@@ -12,6 +12,7 @@
 
 
 
 #include <linux/futex.h>
 
 #include <linux/futex.h>
 
 #include <linux/uaccess.h>
 
 #include <linux/uaccess.h>
 
+#include <asm/asm-eva.h>
 
 #include <asm/barrier.h>
 
 #include <asm/barrier.h>
 
 #include <asm/errno.h>
 
 #include <asm/errno.h>
 
 #include <asm/war.h>
 
 #include <asm/war.h>
 
@@ -22,11 +23,11 @@
 
 		__asm__ __volatile__(					\
 
 		__asm__ __volatile__(					\
 
 		"	.set	push				\n"	\
 
 		"	.set	push				\n"	\
 
 		"	.set	noat				\n"	\
 
 		"	.set	noat				\n"	\
 
-		"	.set	mips3				\n"	\
 
+		"	.set	arch=r4000			\n"	\
 
 		"1:	ll	%1, %4	# __futex_atomic_op	\n"	\
 
 		"1:	ll	%1, %4	# __futex_atomic_op	\n"	\
 
 		"	.set	mips0				\n"	\
 
 		"	.set	mips0				\n"	\
 
 		"	" insn	"				\n"	\
 
 		"	" insn	"				\n"	\
 
-		"	.set	mips3				\n"	\
 
+		"	.set	arch=r4000			\n"	\
 
 		"2:	sc	$1, %2				\n"	\
 
 		"2:	sc	$1, %2				\n"	\
 
 		"	beqzl	$1, 1b				\n"	\
 
 		"	beqzl	$1, 1b				\n"	\
 
 		__WEAK_LLSC_MB						\
 
 		__WEAK_LLSC_MB						\
 
@@ -48,12 +49,12 @@
 
 		__asm__ __volatile__(					\
 
 		__asm__ __volatile__(					\
 
 		"	.set	push				\n"	\
 
 		"	.set	push				\n"	\
 
 		"	.set	noat				\n"	\
 
 		"	.set	noat				\n"	\
 
-		"	.set	mips3				\n"	\
 
-		"1:	ll	%1, %4	# __futex_atomic_op	\n"	\
 
+		"	.set	arch=r4000			\n"	\
 
+		"1:	"user_ll("%1", "%4")" # __futex_atomic_op\n"	\
 
 		"	.set	mips0				\n"	\
 
 		"	.set	mips0				\n"	\
 
 		"	" insn	"				\n"	\
 
 		"	" insn	"				\n"	\
 
-		"	.set	mips3				\n"	\
 
-		"2:	sc	$1, %2				\n"	\
 
+		"	.set	arch=r4000			\n"	\
 
+		"2:	"user_sc("$1", "%2")"			\n"	\
 
 		"	beqz	$1, 1b				\n"	\
 
 		"	beqz	$1, 1b				\n"	\
 
 		__WEAK_LLSC_MB						\
 
 		__WEAK_LLSC_MB						\
 
 		"3:						\n"	\
 
 		"3:						\n"	\
 
@@ -146,12 +147,12 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
 
 		"# futex_atomic_cmpxchg_inatomic			\n"
 
 		"# futex_atomic_cmpxchg_inatomic			\n"
 
 		"	.set	push					\n"
 
 		"	.set	push					\n"
 
 		"	.set	noat					\n"
 
 		"	.set	noat					\n"
 
-		"	.set	mips3					\n"
 
+		"	.set	arch=r4000				\n"
 
 		"1:	ll	%1, %3					\n"
 
 		"1:	ll	%1, %3					\n"
 
 		"	bne	%1, %z4, 3f				\n"
 
 		"	bne	%1, %z4, 3f				\n"
 
 		"	.set	mips0					\n"
 
 		"	.set	mips0					\n"
 
 		"	move	$1, %z5					\n"
 
 		"	move	$1, %z5					\n"
 
-		"	.set	mips3					\n"
 
+		"	.set	arch=r4000				\n"
 
 		"2:	sc	$1, %2					\n"
 
 		"2:	sc	$1, %2					\n"
 
 		"	beqzl	$1, 1b					\n"
 
 		"	beqzl	$1, 1b					\n"
 
 		__WEAK_LLSC_MB
 
 		__WEAK_LLSC_MB
 
@@ -173,13 +174,13 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
 
 		"# futex_atomic_cmpxchg_inatomic			\n"
 
 		"# futex_atomic_cmpxchg_inatomic			\n"
 
 		"	.set	push					\n"
 
 		"	.set	push					\n"
 
 		"	.set	noat					\n"
 
 		"	.set	noat					\n"
 
-		"	.set	mips3					\n"
 
-		"1:	ll	%1, %3					\n"
 
+		"	.set	arch=r4000				\n"
 
+		"1:	"user_ll("%1", "%3")"				\n"
 
 		"	bne	%1, %z4, 3f				\n"
 
 		"	bne	%1, %z4, 3f				\n"
 
 		"	.set	mips0					\n"
 
 		"	.set	mips0					\n"
 
 		"	move	$1, %z5					\n"
 
 		"	move	$1, %z5					\n"
 
-		"	.set	mips3					\n"
 
-		"2:	sc	$1, %2					\n"
 
+		"	.set	arch=r4000				\n"
 
+		"2:	"user_sc("$1", "%2")"				\n"
 
 		"	beqz	$1, 1b					\n"
 
 		"	beqz	$1, 1b					\n"
 
 		__WEAK_LLSC_MB
 
 		__WEAK_LLSC_MB
 
 		"3:							\n"
 
 		"3:							\n"

+ 1 - 1
arch/mips/include/asm/fw/fw.h
Vizualizați fișierul 

@@ -38,7 +38,7 @@ extern int *_fw_envp;
 
 
 
 extern void fw_init_cmdline(void);
 
 extern void fw_init_cmdline(void);
 
 extern char *fw_getcmdline(void);
 
 extern char *fw_getcmdline(void);
 
-extern fw_memblock_t *fw_getmdesc(void);
 
+extern fw_memblock_t *fw_getmdesc(int);
 
 extern void fw_meminit(void);
 
 extern void fw_meminit(void);
 
 extern char *fw_getenv(char *name);
 
 extern char *fw_getenv(char *name);
 
 extern unsigned long fw_getenvl(char *name);
 
 extern unsigned long fw_getenvl(char *name);

+ 0 - 125
arch/mips/include/asm/gcmpregs.h
Vizualizați fișierul 

@@ -1,125 +0,0 @@
 
-/*
 
- * This file is subject to the terms and conditions of the GNU General Public
 
- * License.  See the file "COPYING" in the main directory of this archive
 
- * for more details.
 
- *
 
- * Copyright (C) 2000, 07 MIPS Technologies, Inc.
 
- *
 
- * Multiprocessor Subsystem Register Definitions
 
- *
 
- */
 
-#ifndef _ASM_GCMPREGS_H
 
-#define _ASM_GCMPREGS_H
 
-
 
-
 
-/* Offsets to major blocks within GCMP from GCMP base */
 
-#define GCMP_GCB_OFS		0x0000 /* Global Control Block */
 
-#define GCMP_CLCB_OFS		0x2000 /* Core Local Control Block */
 
-#define GCMP_COCB_OFS		0x4000 /* Core Other Control Block */
 
-#define GCMP_GDB_OFS		0x8000 /* Global Debug Block */
 
-
 
-/* Offsets to individual GCMP registers from GCMP base */
 
-#define GCMPOFS(block, tag, reg)	\
 
-	(GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS)
 
-#define GCMPOFSn(block, tag, reg, n) \
 
-	(GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS(n))
 
-
 
-#define GCMPGCBOFS(reg)		GCMPOFS(GCB, GCB, reg)
 
-#define GCMPGCBOFSn(reg, n)	GCMPOFSn(GCB, GCB, reg, n)
 
-#define GCMPCLCBOFS(reg)	GCMPOFS(CLCB, CCB, reg)
 
-#define GCMPCOCBOFS(reg)	GCMPOFS(COCB, CCB, reg)
 
-#define GCMPGDBOFS(reg)		GCMPOFS(GDB, GDB, reg)
 
-
 
-/* GCMP register access */
 
-#define GCMPGCB(reg)			REGP(_gcmp_base, GCMPGCBOFS(reg))
 
-#define GCMPGCBn(reg, n)	       REGP(_gcmp_base, GCMPGCBOFSn(reg, n))
 
-#define GCMPCLCB(reg)			REGP(_gcmp_base, GCMPCLCBOFS(reg))
 
-#define GCMPCOCB(reg)			REGP(_gcmp_base, GCMPCOCBOFS(reg))
 
-#define GCMPGDB(reg)			REGP(_gcmp_base, GCMPGDBOFS(reg))
 
-
 
-/* Mask generation */
 
-#define GCMPMSK(block, reg, bits)	(MSK(bits)<<GCMP_##block##_##reg##_SHF)
 
-#define GCMPGCBMSK(reg, bits)		GCMPMSK(GCB, reg, bits)
 
-#define GCMPCCBMSK(reg, bits)		GCMPMSK(CCB, reg, bits)
 
-#define GCMPGDBMSK(reg, bits)		GCMPMSK(GDB, reg, bits)
 
-
 
-/* GCB registers */
 
-#define GCMP_GCB_GC_OFS			0x0000	/* Global Config Register */
 
-#define	 GCMP_GCB_GC_NUMIOCU_SHF	8
 
-#define	 GCMP_GCB_GC_NUMIOCU_MSK	GCMPGCBMSK(GC_NUMIOCU, 4)
 
-#define	 GCMP_GCB_GC_NUMCORES_SHF	0
 
-#define	 GCMP_GCB_GC_NUMCORES_MSK	GCMPGCBMSK(GC_NUMCORES, 8)
 
-#define GCMP_GCB_GCMPB_OFS		0x0008		/* Global GCMP Base */
 
-#define	 GCMP_GCB_GCMPB_GCMPBASE_SHF	15
 
-#define	 GCMP_GCB_GCMPB_GCMPBASE_MSK	GCMPGCBMSK(GCMPB_GCMPBASE, 17)
 
-#define	 GCMP_GCB_GCMPB_CMDEFTGT_SHF	0
 
-#define	 GCMP_GCB_GCMPB_CMDEFTGT_MSK	GCMPGCBMSK(GCMPB_CMDEFTGT, 2)
 
-#define	 GCMP_GCB_GCMPB_CMDEFTGT_DISABLED	0
 
-#define	 GCMP_GCB_GCMPB_CMDEFTGT_MEM		1
 
-#define	 GCMP_GCB_GCMPB_CMDEFTGT_IOCU1		2
 
-#define	 GCMP_GCB_GCMPB_CMDEFTGT_IOCU2		3
 
-#define GCMP_GCB_CCMC_OFS		0x0010	/* Global CM Control */
 
-#define GCMP_GCB_GCSRAP_OFS		0x0020	/* Global CSR Access Privilege */
 
-#define	 GCMP_GCB_GCSRAP_CMACCESS_SHF	0
 
-#define	 GCMP_GCB_GCSRAP_CMACCESS_MSK	GCMPGCBMSK(GCSRAP_CMACCESS, 8)
 
-#define GCMP_GCB_GCMPREV_OFS		0x0030	/* GCMP Revision Register */
 
-#define GCMP_GCB_GCMEM_OFS		0x0040	/* Global CM Error Mask */
 
-#define GCMP_GCB_GCMEC_OFS		0x0048	/* Global CM Error Cause */
 
-#define	 GCMP_GCB_GMEC_ERROR_TYPE_SHF	27
 
-#define	 GCMP_GCB_GMEC_ERROR_TYPE_MSK	GCMPGCBMSK(GMEC_ERROR_TYPE, 5)
 
-#define	 GCMP_GCB_GMEC_ERROR_INFO_SHF	0
 
-#define	 GCMP_GCB_GMEC_ERROR_INFO_MSK	GCMPGCBMSK(GMEC_ERROR_INFO, 27)
 
-#define GCMP_GCB_GCMEA_OFS		0x0050	/* Global CM Error Address */
 
-#define GCMP_GCB_GCMEO_OFS		0x0058	/* Global CM Error Multiple */
 
-#define	 GCMP_GCB_GMEO_ERROR_2ND_SHF	0
 
-#define	 GCMP_GCB_GMEO_ERROR_2ND_MSK	GCMPGCBMSK(GMEO_ERROR_2ND, 5)
 
-#define GCMP_GCB_GICBA_OFS		0x0080	/* Global Interrupt Controller Base Address */
 
-#define	 GCMP_GCB_GICBA_BASE_SHF	17
 
-#define	 GCMP_GCB_GICBA_BASE_MSK	GCMPGCBMSK(GICBA_BASE, 15)
 
-#define	 GCMP_GCB_GICBA_EN_SHF		0
 
-#define	 GCMP_GCB_GICBA_EN_MSK		GCMPGCBMSK(GICBA_EN, 1)
 
-
 
-/* GCB Regions */
 
-#define GCMP_GCB_CMxBASE_OFS(n)		(0x0090+16*(n))		/* Global Region[0-3] Base Address */
 
-#define	 GCMP_GCB_CMxBASE_BASE_SHF	16
 
-#define	 GCMP_GCB_CMxBASE_BASE_MSK	GCMPGCBMSK(CMxBASE_BASE, 16)
 
-#define GCMP_GCB_CMxMASK_OFS(n)		(0x0098+16*(n))		/* Global Region[0-3] Address Mask */
 
-#define	 GCMP_GCB_CMxMASK_MASK_SHF	16
 
-#define	 GCMP_GCB_CMxMASK_MASK_MSK	GCMPGCBMSK(CMxMASK_MASK, 16)
 
-#define	 GCMP_GCB_CMxMASK_CMREGTGT_SHF	0
 
-#define	 GCMP_GCB_CMxMASK_CMREGTGT_MSK	GCMPGCBMSK(CMxMASK_CMREGTGT, 2)
 
-#define	 GCMP_GCB_CMxMASK_CMREGTGT_MEM	 0
 
-#define	 GCMP_GCB_CMxMASK_CMREGTGT_MEM1	 1
 
-#define	 GCMP_GCB_CMxMASK_CMREGTGT_IOCU1 2
 
-#define	 GCMP_GCB_CMxMASK_CMREGTGT_IOCU2 3
 
-
 
-
 
-/* Core local/Core other control block registers */
 
-#define GCMP_CCB_RESETR_OFS		0x0000			/* Reset Release */
 
-#define	 GCMP_CCB_RESETR_INRESET_SHF	0
 
-#define	 GCMP_CCB_RESETR_INRESET_MSK	GCMPCCBMSK(RESETR_INRESET, 16)
 
-#define GCMP_CCB_COHCTL_OFS		0x0008			/* Coherence Control */
 
-#define	 GCMP_CCB_COHCTL_DOMAIN_SHF	0
 
-#define	 GCMP_CCB_COHCTL_DOMAIN_MSK	GCMPCCBMSK(COHCTL_DOMAIN, 8)
 
-#define GCMP_CCB_CFG_OFS		0x0010			/* Config */
 
-#define	 GCMP_CCB_CFG_IOCUTYPE_SHF	10
 
-#define	 GCMP_CCB_CFG_IOCUTYPE_MSK	GCMPCCBMSK(CFG_IOCUTYPE, 2)
 
-#define	  GCMP_CCB_CFG_IOCUTYPE_CPU	0
 
-#define	  GCMP_CCB_CFG_IOCUTYPE_NCIOCU	1
 
-#define	  GCMP_CCB_CFG_IOCUTYPE_CIOCU	2
 
-#define	 GCMP_CCB_CFG_NUMVPE_SHF	0
 
-#define	 GCMP_CCB_CFG_NUMVPE_MSK	GCMPCCBMSK(CFG_NUMVPE, 10)
 
-#define GCMP_CCB_OTHER_OFS		0x0018		/* Other Address */
 
-#define	 GCMP_CCB_OTHER_CORENUM_SHF	16
 
-#define	 GCMP_CCB_OTHER_CORENUM_MSK	GCMPCCBMSK(OTHER_CORENUM, 16)
 
-#define GCMP_CCB_RESETBASE_OFS		0x0020		/* Reset Exception Base */
 
-#define	 GCMP_CCB_RESETBASE_BEV_SHF	12
 
-#define	 GCMP_CCB_RESETBASE_BEV_MSK	GCMPCCBMSK(RESETBASE_BEV, 20)
 
-#define GCMP_CCB_ID_OFS			0x0028		/* Identification */
 
-#define GCMP_CCB_DINTGROUP_OFS		0x0030		/* DINT Group Participate */
 
-#define GCMP_CCB_DBGGROUP_OFS		0x0100		/* DebugBreak Group */
 
-
 
-extern int __init gcmp_probe(unsigned long, unsigned long);
 
-extern int __init gcmp_niocu(void);
 
-extern void __init gcmp_setregion(int, unsigned long, unsigned long, int);
 
-#endif /* _ASM_GCMPREGS_H */

+ 3 - 0
arch/mips/include/asm/gic.h
Vizualizați fișierul 

@@ -11,6 +11,9 @@
 
 #ifndef _ASM_GICREGS_H
 
 #ifndef _ASM_GICREGS_H
 
 #define _ASM_GICREGS_H
 
 #define _ASM_GICREGS_H
 
 
 
+#include <linux/bitmap.h>
 
+#include <linux/threads.h>
 
+
 
 #undef	GICISBYTELITTLEENDIAN
 
 #undef	GICISBYTELITTLEENDIAN
 
 
 
 /* Constants */
 
 /* Constants */

+ 4 - 4
arch/mips/include/asm/io.h
Vizualizați fișierul 

@@ -331,7 +331,7 @@ static inline void pfx##write##bwlq(type val,				\
 
 		if (irq)						\
 
 		if (irq)						\
 
 			local_irq_save(__flags);			\
 
 			local_irq_save(__flags);			\
 
 		__asm__ __volatile__(					\
 
 		__asm__ __volatile__(					\
 
-			".set	mips3"		"\t\t# __writeq""\n\t"	\
 
+			".set	arch=r4000"	"\t\t# __writeq""\n\t"	\
 
 			"dsll32 %L0, %L0, 0"			"\n\t"	\
 
 			"dsll32 %L0, %L0, 0"			"\n\t"	\
 
 			"dsrl32 %L0, %L0, 0"			"\n\t"	\
 
 			"dsrl32 %L0, %L0, 0"			"\n\t"	\
 
 			"dsll32 %M0, %M0, 0"			"\n\t"	\
 
 			"dsll32 %M0, %M0, 0"			"\n\t"	\
 
@@ -361,7 +361,7 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem)	\
 
 		if (irq)						\
 
 		if (irq)						\
 
 			local_irq_save(__flags);			\
 
 			local_irq_save(__flags);			\
 
 		__asm__ __volatile__(					\
 
 		__asm__ __volatile__(					\
 
-			".set	mips3"		"\t\t# __readq" "\n\t"	\
 
+			".set	arch=r4000"	"\t\t# __readq" "\n\t"	\
 
 			"ld	%L0, %1"			"\n\t"	\
 
 			"ld	%L0, %1"			"\n\t"	\
 
 			"dsra32 %M0, %L0, 0"			"\n\t"	\
 
 			"dsra32 %M0, %L0, 0"			"\n\t"	\
 
 			"sll	%L0, %L0, 0"			"\n\t"	\
 
 			"sll	%L0, %L0, 0"			"\n\t"	\
 
@@ -584,7 +584,7 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int
 
  *
 
  *
 
  * This API used to be exported; it now is for arch code internal use only.
 
  * This API used to be exported; it now is for arch code internal use only.
 
  */
 
  */
 
-#ifdef CONFIG_DMA_NONCOHERENT
 
+#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)
 
 
 
 extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
 
 extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
 
 extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
 
 extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
 
@@ -603,7 +603,7 @@ extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
 
 #define dma_cache_inv(start,size)	\
 
 #define dma_cache_inv(start,size)	\
 
 	do { (void) (start); (void) (size); } while (0)
 
 	do { (void) (start); (void) (size); } while (0)
 
 
 
-#endif /* CONFIG_DMA_NONCOHERENT */
 
+#endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */
 
 
 
 /*
 
 /*
 
  * Read a 32-bit register that requires a 64-bit read cycle on the bus.
 
  * Read a 32-bit register that requires a 64-bit read cycle on the bus.

+ 4 - 4
arch/mips/include/asm/local.h
Vizualizați fișierul 

@@ -33,7 +33,7 @@ static __inline__ long local_add_return(long i, local_t * l)
 
 		unsigned long temp;
 
 		unsigned long temp;
 
 
 
 		__asm__ __volatile__(
 
 		__asm__ __volatile__(
 
-		"	.set	mips3					\n"
 
+		"	.set	arch=r4000				\n"
 
 		"1:"	__LL	"%1, %2		# local_add_return	\n"
 
 		"1:"	__LL	"%1, %2		# local_add_return	\n"
 
 		"	addu	%0, %1, %3				\n"
 
 		"	addu	%0, %1, %3				\n"
 
 			__SC	"%0, %2					\n"
 
 			__SC	"%0, %2					\n"
 
@@ -47,7 +47,7 @@ static __inline__ long local_add_return(long i, local_t * l)
 
 		unsigned long temp;
 
 		unsigned long temp;
 
 
 
 		__asm__ __volatile__(
 
 		__asm__ __volatile__(
 
-		"	.set	mips3					\n"
 
+		"	.set	arch=r4000				\n"
 
 		"1:"	__LL	"%1, %2		# local_add_return	\n"
 
 		"1:"	__LL	"%1, %2		# local_add_return	\n"
 
 		"	addu	%0, %1, %3				\n"
 
 		"	addu	%0, %1, %3				\n"
 
 			__SC	"%0, %2					\n"
 
 			__SC	"%0, %2					\n"
 
@@ -78,7 +78,7 @@ static __inline__ long local_sub_return(long i, local_t * l)
 
 		unsigned long temp;
 
 		unsigned long temp;
 
 
 
 		__asm__ __volatile__(
 
 		__asm__ __volatile__(
 
-		"	.set	mips3					\n"
 
+		"	.set	arch=r4000				\n"
 
 		"1:"	__LL	"%1, %2		# local_sub_return	\n"
 
 		"1:"	__LL	"%1, %2		# local_sub_return	\n"
 
 		"	subu	%0, %1, %3				\n"
 
 		"	subu	%0, %1, %3				\n"
 
 			__SC	"%0, %2					\n"
 
 			__SC	"%0, %2					\n"
 
@@ -92,7 +92,7 @@ static __inline__ long local_sub_return(long i, local_t * l)
 
 		unsigned long temp;
 
 		unsigned long temp;
 
 
 
 		__asm__ __volatile__(
 
 		__asm__ __volatile__(
 
-		"	.set	mips3					\n"
 
+		"	.set	arch=r4000				\n"
 
 		"1:"	__LL	"%1, %2		# local_sub_return	\n"
 
 		"1:"	__LL	"%1, %2		# local_sub_return	\n"
 
 		"	subu	%0, %1, %3				\n"
 
 		"	subu	%0, %1, %3				\n"
 
 			__SC	"%0, %2					\n"
 
 			__SC	"%0, %2					\n"

+ 0 - 12
arch/mips/include/asm/mach-au1x00/au1000.h
Vizualizați fișierul 

@@ -1161,18 +1161,6 @@ enum soc_au1200_ints {
 
 #define MAC_RX_BUFF3_STATUS	0x30
 
 #define MAC_RX_BUFF3_STATUS	0x30
 
 #define MAC_RX_BUFF3_ADDR	0x34
 
 #define MAC_RX_BUFF3_ADDR	0x34
 
 
 
-#define UART_RX		0	/* Receive buffer */
 
-#define UART_TX		4	/* Transmit buffer */
 
-#define UART_IER	8	/* Interrupt Enable Register */
 
-#define UART_IIR	0xC	/* Interrupt ID Register */
 
-#define UART_FCR	0x10	/* FIFO Control Register */
 
-#define UART_LCR	0x14	/* Line Control Register */
 
-#define UART_MCR	0x18	/* Modem Control Register */
 
-#define UART_LSR	0x1C	/* Line Status Register */
 
-#define UART_MSR	0x20	/* Modem Status Register */
 
-#define UART_CLK	0x28	/* Baud Rate Clock Divider */
 
-#define UART_MOD_CNTRL	0x100	/* Module Control */
 
-
 
 /* SSIO */
 
 /* SSIO */
 
 #define SSI0_STATUS		0xB1600000
 
 #define SSI0_STATUS		0xB1600000
 
 #  define SSI_STATUS_BF		(1 << 4)
 
 #  define SSI_STATUS_BF		(1 << 4)

+ 7 - 1
arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
Vizualizați fișierul 

@@ -27,7 +27,11 @@ enum bcm47xx_board {
 
 	BCM47XX_BOARD_ASUS_WL700GE,
 
 	BCM47XX_BOARD_ASUS_WL700GE,
 
 	BCM47XX_BOARD_ASUS_WLHDD,
 
 	BCM47XX_BOARD_ASUS_WLHDD,
 
 
 
+	BCM47XX_BOARD_BELKIN_F7D3301,
 
+	BCM47XX_BOARD_BELKIN_F7D3302,
 
 	BCM47XX_BOARD_BELKIN_F7D4301,
 
 	BCM47XX_BOARD_BELKIN_F7D4301,
 
+	BCM47XX_BOARD_BELKIN_F7D4302,
 
+	BCM47XX_BOARD_BELKIN_F7D4401,
 
 
 
 	BCM47XX_BOARD_BUFFALO_WBR2_G54,
 
 	BCM47XX_BOARD_BUFFALO_WBR2_G54,
 
 	BCM47XX_BOARD_BUFFALO_WHR2_A54G54,
 
 	BCM47XX_BOARD_BUFFALO_WHR2_A54G54,
 
@@ -66,7 +70,7 @@ enum bcm47xx_board {
 
 	BCM47XX_BOARD_LINKSYS_WRT310NV1,
 
 	BCM47XX_BOARD_LINKSYS_WRT310NV1,
 
 	BCM47XX_BOARD_LINKSYS_WRT310NV2,
 
 	BCM47XX_BOARD_LINKSYS_WRT310NV2,
 
 	BCM47XX_BOARD_LINKSYS_WRT54G3GV2,
 
 	BCM47XX_BOARD_LINKSYS_WRT54G3GV2,
 
-	BCM47XX_BOARD_LINKSYS_WRT54GSV1,
 
+	BCM47XX_BOARD_LINKSYS_WRT54G,
 
 	BCM47XX_BOARD_LINKSYS_WRT610NV1,
 
 	BCM47XX_BOARD_LINKSYS_WRT610NV1,
 
 	BCM47XX_BOARD_LINKSYS_WRT610NV2,
 
 	BCM47XX_BOARD_LINKSYS_WRT610NV2,
 
 	BCM47XX_BOARD_LINKSYS_WRTSL54GS,
 
 	BCM47XX_BOARD_LINKSYS_WRTSL54GS,
 
@@ -94,6 +98,8 @@ enum bcm47xx_board {
 
 
 
 	BCM47XX_BOARD_PHICOMM_M1,
 
 	BCM47XX_BOARD_PHICOMM_M1,
 
 
 
+	BCM47XX_BOARD_SIEMENS_SE505V2,
 
+
 
 	BCM47XX_BOARD_SIMPLETECH_SIMPLESHARE,
 
 	BCM47XX_BOARD_SIMPLETECH_SIMPLESHARE,
 
 
 
 	BCM47XX_BOARD_ZTE_H218N,
 
 	BCM47XX_BOARD_ZTE_H218N,

+ 0 - 91
arch/mips/include/asm/mach-db1x00/db1200.h
Vizualizați fișierul 

@@ -1,91 +0,0 @@
 
-/*
 
- * AMD Alchemy DBAu1200 Reference Board
 
- * Board register defines.
 
- *
 
- * ########################################################################
 
- *
 
- *  This program is free software; you can distribute it and/or modify it
 
- *  under the terms of the GNU General Public License (Version 2) as
 
- *  published by the Free Software Foundation.
 
- *
 
- *  This program is distributed in the hope it will be useful, but WITHOUT
 
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 
- *  for more details.
 
- *
 
- *  You should have received a copy of the GNU General Public License along
 
- *  with this program; if not, write to the Free Software Foundation, Inc.,
 
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 
- *
 
- * ########################################################################
 
- *
 
- *
 
- */
 
-#ifndef __ASM_DB1200_H
 
-#define __ASM_DB1200_H
 
-
 
-#include <linux/types.h>
 
-#include <asm/mach-au1x00/au1000.h>
 
-#include <asm/mach-au1x00/au1xxx_psc.h>
 
-
 
-/* Bit positions for the different interrupt sources */
 
-#define BCSR_INT_IDE		0x0001
 
-#define BCSR_INT_ETH		0x0002
 
-#define BCSR_INT_PC0		0x0004
 
-#define BCSR_INT_PC0STSCHG	0x0008
 
-#define BCSR_INT_PC1		0x0010
 
-#define BCSR_INT_PC1STSCHG	0x0020
 
-#define BCSR_INT_DC		0x0040
 
-#define BCSR_INT_FLASHBUSY	0x0080
 
-#define BCSR_INT_PC0INSERT	0x0100
 
-#define BCSR_INT_PC0EJECT	0x0200
 
-#define BCSR_INT_PC1INSERT	0x0400
 
-#define BCSR_INT_PC1EJECT	0x0800
 
-#define BCSR_INT_SD0INSERT	0x1000
 
-#define BCSR_INT_SD0EJECT	0x2000
 
-#define BCSR_INT_SD1INSERT	0x4000
 
-#define BCSR_INT_SD1EJECT	0x8000
 
-
 
-#define IDE_REG_SHIFT		5
 
-
 
-#define DB1200_IDE_PHYS_ADDR	0x18800000
 
-#define DB1200_IDE_PHYS_LEN	(16 << IDE_REG_SHIFT)
 
-#define DB1200_ETH_PHYS_ADDR	0x19000300
 
-#define DB1200_NAND_PHYS_ADDR	0x20000000
 
-
 
-#define PB1200_IDE_PHYS_ADDR	0x0C800000
 
-#define PB1200_ETH_PHYS_ADDR	0x0D000300
 
-#define PB1200_NAND_PHYS_ADDR	0x1C000000
 
-
 
-/*
 
- * External Interrupts for DBAu1200 as of 8/6/2004.
 
- * Bit positions in the CPLD registers can be calculated by taking
 
- * the interrupt define and subtracting the DB1200_INT_BEGIN value.
 
- *
 
- *   Example: IDE bis pos is  = 64 - 64
 
- *	      ETH bit pos is  = 65 - 64
 
- */
 
-enum external_db1200_ints {
 
-	DB1200_INT_BEGIN	= AU1000_MAX_INTR + 1,
 
-
 
-	DB1200_IDE_INT		= DB1200_INT_BEGIN,
 
-	DB1200_ETH_INT,
 
-	DB1200_PC0_INT,
 
-	DB1200_PC0_STSCHG_INT,
 
-	DB1200_PC1_INT,
 
-	DB1200_PC1_STSCHG_INT,
 
-	DB1200_DC_INT,
 
-	DB1200_FLASHBUSY_INT,
 
-	DB1200_PC0_INSERT_INT,
 
-	DB1200_PC0_EJECT_INT,
 
-	DB1200_PC1_INSERT_INT,
 
-	DB1200_PC1_EJECT_INT,
 
-	DB1200_SD0_INSERT_INT,
 
-	DB1200_SD0_EJECT_INT,
 
-	PB1200_SD1_INSERT_INT,
 
-	PB1200_SD1_EJECT_INT,
 
-
 
-	DB1200_INT_END		= DB1200_INT_BEGIN + 15,
 
-};
 
-
 
-#endif /* __ASM_DB1200_H */

+ 0 - 40
arch/mips/include/asm/mach-db1x00/db1300.h
Vizualizați fișierul 

@@ -1,40 +0,0 @@
 
-/*
 
- * NetLogic DB1300 board constants
 
- */
 
-
 
-#ifndef _DB1300_H_
 
-#define _DB1300_H_
 
-
 
-/* FPGA (external mux) interrupt sources */
 
-#define DB1300_FIRST_INT	(ALCHEMY_GPIC_INT_LAST + 1)
 
-#define DB1300_IDE_INT		(DB1300_FIRST_INT + 0)
 
-#define DB1300_ETH_INT		(DB1300_FIRST_INT + 1)
 
-#define DB1300_CF_INT		(DB1300_FIRST_INT + 2)
 
-#define DB1300_VIDEO_INT	(DB1300_FIRST_INT + 4)
 
-#define DB1300_HDMI_INT		(DB1300_FIRST_INT + 5)
 
-#define DB1300_DC_INT		(DB1300_FIRST_INT + 6)
 
-#define DB1300_FLASH_INT	(DB1300_FIRST_INT + 7)
 
-#define DB1300_CF_INSERT_INT	(DB1300_FIRST_INT + 8)
 
-#define DB1300_CF_EJECT_INT	(DB1300_FIRST_INT + 9)
 
-#define DB1300_AC97_INT		(DB1300_FIRST_INT + 10)
 
-#define DB1300_AC97_PEN_INT	(DB1300_FIRST_INT + 11)
 
-#define DB1300_SD1_INSERT_INT	(DB1300_FIRST_INT + 12)
 
-#define DB1300_SD1_EJECT_INT	(DB1300_FIRST_INT + 13)
 
-#define DB1300_OTG_VBUS_OC_INT	(DB1300_FIRST_INT + 14)
 
-#define DB1300_HOST_VBUS_OC_INT (DB1300_FIRST_INT + 15)
 
-#define DB1300_LAST_INT		(DB1300_FIRST_INT + 15)
 
-
 
-/* SMSC9210 CS */
 
-#define DB1300_ETH_PHYS_ADDR	0x19000000
 
-#define DB1300_ETH_PHYS_END	0x197fffff
 
-
 
-/* ATA CS */
 
-#define DB1300_IDE_PHYS_ADDR	0x18800000
 
-#define DB1300_IDE_REG_SHIFT	5
 
-#define DB1300_IDE_PHYS_LEN	(16 << DB1300_IDE_REG_SHIFT)
 
-
 
-/* NAND CS */
 
-#define DB1300_NAND_PHYS_ADDR	0x20000000
 
-#define DB1300_NAND_PHYS_END	0x20000fff
 
-
 
-#endif	/* _DB1300_H_ */

+ 163 - 0
arch/mips/include/asm/mach-loongson/boot_param.h
Vizualizați fișierul 

@@ -0,0 +1,163 @@
 
+#ifndef __ASM_MACH_LOONGSON_BOOT_PARAM_H_
 
+#define __ASM_MACH_LOONGSON_BOOT_PARAM_H_
 
+
 
+#define SYSTEM_RAM_LOW		1
 
+#define SYSTEM_RAM_HIGH		2
 
+#define MEM_RESERVED		3
 
+#define PCI_IO			4
 
+#define PCI_MEM			5
 
+#define LOONGSON_CFG_REG	6
 
+#define VIDEO_ROM		7
 
+#define ADAPTER_ROM		8
 
+#define ACPI_TABLE		9
 
+#define MAX_MEMORY_TYPE		10
 
+
 
+#define LOONGSON3_BOOT_MEM_MAP_MAX 128
 
+struct efi_memory_map_loongson {
 
+	u16 vers;	/* version of efi_memory_map */
 
+	u32 nr_map;	/* number of memory_maps */
 
+	u32 mem_freq;	/* memory frequence */
 
+	struct mem_map {
 
+		u32 node_id;	/* node_id which memory attached to */
 
+		u32 mem_type;	/* system memory, pci memory, pci io, etc. */
 
+		u64 mem_start;	/* memory map start address */
 
+		u32 mem_size;	/* each memory_map size, not the total size */
 
+	} map[LOONGSON3_BOOT_MEM_MAP_MAX];
 
+} __packed;
 
+
 
+enum loongson_cpu_type {
 
+	Loongson_2E = 0,
 
+	Loongson_2F = 1,
 
+	Loongson_3A = 2,
 
+	Loongson_3B = 3,
 
+	Loongson_1A = 4,
 
+	Loongson_1B = 5
 
+};
 
+
 
+/*
 
+ * Capability and feature descriptor structure for MIPS CPU
 
+ */
 
+struct efi_cpuinfo_loongson {
 
+	u16 vers;     /* version of efi_cpuinfo_loongson */
 
+	u32 processor_id; /* PRID, e.g. 6305, 6306 */
 
+	u32 cputype;  /* Loongson_3A/3B, etc. */
 
+	u32 total_node;   /* num of total numa nodes */
 
+	u32 cpu_startup_core_id; /* Core id */
 
+	u32 cpu_clock_freq; /* cpu_clock */
 
+	u32 nr_cpus;
 
+} __packed;
 
+
 
+struct system_loongson {
 
+	u16 vers;     /* version of system_loongson */
 
+	u32 ccnuma_smp; /* 0: no numa; 1: has numa */
 
+	u32 sing_double_channel; /* 1:single; 2:double */
 
+} __packed;
 
+
 
+struct irq_source_routing_table {
 
+	u16 vers;
 
+	u16 size;
 
+	u16 rtr_bus;
 
+	u16 rtr_devfn;
 
+	u32 vendor;
 
+	u32 device;
 
+	u32 PIC_type;   /* conform use HT or PCI to route to CPU-PIC */
 
+	u64 ht_int_bit; /* 3A: 1<<24; 3B: 1<<16 */
 
+	u64 ht_enable;  /* irqs used in this PIC */
 
+	u32 node_id;    /* node id: 0x0-0; 0x1-1; 0x10-2; 0x11-3 */
 
+	u64 pci_mem_start_addr;
 
+	u64 pci_mem_end_addr;
 
+	u64 pci_io_start_addr;
 
+	u64 pci_io_end_addr;
 
+	u64 pci_config_addr;
 
+	u32 dma_mask_bits;
 
+} __packed;
 
+
 
+struct interface_info {
 
+	u16 vers; /* version of the specificition */
 
+	u16 size;
 
+	u8  flag;
 
+	char description[64];
 
+} __packed;
 
+
 
+#define MAX_RESOURCE_NUMBER 128
 
+struct resource_loongson {
 
+	u64 start; /* resource start address */
 
+	u64 end;   /* resource end address */
 
+	char name[64];
 
+	u32 flags;
 
+};
 
+
 
+struct archdev_data {};  /* arch specific additions */
 
+
 
+struct board_devices {
 
+	char name[64];    /* hold the device name */
 
+	u32 num_resources; /* number of device_resource */
 
+	/* for each device's resource */
 
+	struct resource_loongson resource[MAX_RESOURCE_NUMBER];
 
+	/* arch specific additions */
 
+	struct archdev_data archdata;
 
+};
 
+
 
+struct loongson_special_attribute {
 
+	u16 vers;     /* version of this special */
 
+	char special_name[64]; /* special_atribute_name */
 
+	u32 loongson_special_type; /* type of special device */
 
+	/* for each device's resource */
 
+	struct resource_loongson resource[MAX_RESOURCE_NUMBER];
 
+};
 
+
 
+struct loongson_params {
 
+	u64 memory_offset;	/* efi_memory_map_loongson struct offset */
 
+	u64 cpu_offset;		/* efi_cpuinfo_loongson struct offset */
 
+	u64 system_offset;	/* system_loongson struct offset */
 
+	u64 irq_offset;		/* irq_source_routing_table struct offset */
 
+	u64 interface_offset;	/* interface_info struct offset */
 
+	u64 special_offset;	/* loongson_special_attribute struct offset */
 
+	u64 boarddev_table_offset;  /* board_devices offset */
 
+};
 
+
 
+struct smbios_tables {
 
+	u16 vers;     /* version of smbios */
 
+	u64 vga_bios; /* vga_bios address */
 
+	struct loongson_params lp;
 
+};
 
+
 
+struct efi_reset_system_t {
 
+	u64 ResetCold;
 
+	u64 ResetWarm;
 
+	u64 ResetType;
 
+	u64 Shutdown;
 
+	u64 DoSuspend; /* NULL if not support */
 
+};
 
+
 
+struct efi_loongson {
 
+	u64 mps;	/* MPS table */
 
+	u64 acpi;	/* ACPI table (IA64 ext 0.71) */
 
+	u64 acpi20;	/* ACPI table (ACPI 2.0) */
 
+	struct smbios_tables smbios;	/* SM BIOS table */
 
+	u64 sal_systab;	/* SAL system table */
 
+	u64 boot_info;	/* boot info table */
 
+};
 
+
 
+struct boot_params {
 
+	struct efi_loongson efi;
 
+	struct efi_reset_system_t reset_system;
 
+};
 
+
 
+struct loongson_system_configuration {
 
+	u32 nr_cpus;
 
+	enum loongson_cpu_type cputype;
 
+	u64 ht_control_base;
 
+	u64 pci_mem_start_addr;
 
+	u64 pci_mem_end_addr;
 
+	u64 pci_io_base;
 
+	u64 restart_addr;
 
+	u64 poweroff_addr;
 
+	u64 suspend_addr;
 
+	u64 vgabios_addr;
 
+	u32 dma_mask_bits;
 
+};
 
+
 
+extern struct efi_memory_map_loongson *loongson_memmap;
 
+extern struct loongson_system_configuration loongson_sysconf;
 
+#endif

+ 21 - 1
arch/mips/include/asm/mach-loongson/dma-coherence.h
Vizualizați fișierul 

@@ -11,24 +11,40 @@
 
 #ifndef __ASM_MACH_LOONGSON_DMA_COHERENCE_H
 
 #ifndef __ASM_MACH_LOONGSON_DMA_COHERENCE_H
 
 #define __ASM_MACH_LOONGSON_DMA_COHERENCE_H
 
 #define __ASM_MACH_LOONGSON_DMA_COHERENCE_H
 
 
 
+#ifdef CONFIG_SWIOTLB
 
+#include <linux/swiotlb.h>
 
+#endif
 
+
 
 struct device;
 
 struct device;
 
 
 
+extern dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr);
 
+extern phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr);
 
 static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
 
 static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
 
 					  size_t size)
 
 					  size_t size)
 
 {
 
 {
 
+#ifdef CONFIG_CPU_LOONGSON3
 
+	return virt_to_phys(addr);
 
+#else
 
 	return virt_to_phys(addr) | 0x80000000;
 
 	return virt_to_phys(addr) | 0x80000000;
 
+#endif
 
 }
 
 }
 
 
 
 static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
 
 static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
 
 					       struct page *page)
 
 					       struct page *page)
 
 {
 
 {
 
+#ifdef CONFIG_CPU_LOONGSON3
 
+	return page_to_phys(page);
 
+#else
 
 	return page_to_phys(page) | 0x80000000;
 
 	return page_to_phys(page) | 0x80000000;
 
+#endif
 
 }
 
 }
 
 
 
 static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
 
 static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
 
 	dma_addr_t dma_addr)
 
 	dma_addr_t dma_addr)
 
 {
 
 {
 
-#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT)
 
+#if defined(CONFIG_CPU_LOONGSON3) && defined(CONFIG_64BIT)
 
+	return dma_addr;
 
+#elif defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT)
 
 	return (dma_addr > 0x8fffffff) ? dma_addr : (dma_addr & 0x0fffffff);
 
 	return (dma_addr > 0x8fffffff) ? dma_addr : (dma_addr & 0x0fffffff);
 
 #else
 
 #else
 
 	return dma_addr & 0x7fffffff;
 
 	return dma_addr & 0x7fffffff;
 
@@ -55,7 +71,11 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
 
 
 
 static inline int plat_device_is_coherent(struct device *dev)
 
 static inline int plat_device_is_coherent(struct device *dev)
 
 {
 
 {
 
+#ifdef CONFIG_DMA_NONCOHERENT
 
 	return 0;
 
 	return 0;
 
+#else
 
+	return 1;
 
+#endif /* CONFIG_DMA_NONCOHERENT */
 
 }
 
 }
 
 
 
 #endif /* __ASM_MACH_LOONGSON_DMA_COHERENCE_H */
 
 #endif /* __ASM_MACH_LOONGSON_DMA_COHERENCE_H */

+ 44 - 0
arch/mips/include/asm/mach-loongson/irq.h
Vizualizați fișierul 

@@ -0,0 +1,44 @@
 
+#ifndef __ASM_MACH_LOONGSON_IRQ_H_
 
+#define __ASM_MACH_LOONGSON_IRQ_H_
 
+
 
+#include <boot_param.h>
 
+
 
+#ifdef CONFIG_CPU_LOONGSON3
 
+
 
+/* cpu core interrupt numbers */
 
+#define MIPS_CPU_IRQ_BASE 56
 
+
 
+#define LOONGSON_UART_IRQ   (MIPS_CPU_IRQ_BASE + 2) /* UART */
 
+#define LOONGSON_HT1_IRQ    (MIPS_CPU_IRQ_BASE + 3) /* HT1 */
 
+#define LOONGSON_TIMER_IRQ  (MIPS_CPU_IRQ_BASE + 7) /* CPU Timer */
 
+
 
+#define LOONGSON_HT1_CFG_BASE		loongson_sysconf.ht_control_base
 
+#define LOONGSON_HT1_INT_VECTOR_BASE	(LOONGSON_HT1_CFG_BASE + 0x80)
 
+#define LOONGSON_HT1_INT_EN_BASE	(LOONGSON_HT1_CFG_BASE + 0xa0)
 
+#define LOONGSON_HT1_INT_VECTOR(n)	\
 
+		LOONGSON3_REG32(LOONGSON_HT1_INT_VECTOR_BASE, 4 * (n))
 
+#define LOONGSON_HT1_INTN_EN(n)		\
 
+		LOONGSON3_REG32(LOONGSON_HT1_INT_EN_BASE, 4 * (n))
 
+
 
+#define LOONGSON_INT_ROUTER_OFFSET	0x1400
 
+#define LOONGSON_INT_ROUTER_INTEN	\
 
+	  LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x24)
 
+#define LOONGSON_INT_ROUTER_INTENSET	\
 
+	  LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x28)
 
+#define LOONGSON_INT_ROUTER_INTENCLR	\
 
+	  LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x2c)
 
+#define LOONGSON_INT_ROUTER_ENTRY(n)	\
 
+	  LOONGSON3_REG8(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + n)
 
+#define LOONGSON_INT_ROUTER_LPC		LOONGSON_INT_ROUTER_ENTRY(0x0a)
 
+#define LOONGSON_INT_ROUTER_HT1(n)	LOONGSON_INT_ROUTER_ENTRY(n + 0x18)
 
+
 
+#define LOONGSON_INT_CORE0_INT0		0x11 /* route to int 0 of core 0 */
 
+#define LOONGSON_INT_CORE0_INT1		0x21 /* route to int 1 of core 0 */
 
+
 
+#endif
 
+
 
+extern void fixup_irqs(void);
 
+extern void loongson3_ipi_interrupt(struct pt_regs *regs);
 
+
 
+#include_next <irq.h>
 
+#endif /* __ASM_MACH_LOONGSON_IRQ_H_ */

+ 23 - 5
arch/mips/include/asm/mach-loongson/loongson.h
Vizualizați fișierul 

@@ -15,6 +15,7 @@
 
 #include <linux/init.h>
 
 #include <linux/init.h>
 
 #include <linux/irq.h>
 
 #include <linux/irq.h>
 
 #include <linux/kconfig.h>
 
 #include <linux/kconfig.h>
 
+#include <boot_param.h>
 
 
 
 /* loongson internal northbridge initialization */
 
 /* loongson internal northbridge initialization */
 
 extern void bonito_irq_init(void);
 
 extern void bonito_irq_init(void);
 
@@ -24,8 +25,9 @@ extern void mach_prepare_reboot(void);
 
 extern void mach_prepare_shutdown(void);
 
 extern void mach_prepare_shutdown(void);
 
 
 
 /* environment arguments from bootloader */
 
 /* environment arguments from bootloader */
 
-extern unsigned long cpu_clock_freq;
 
-extern unsigned long memsize, highmemsize;
 
+extern u32 cpu_clock_freq;
 
+extern u32 memsize, highmemsize;
 
+extern struct plat_smp_ops loongson3_smp_ops;
 
 
 
 /* loongson-specific command line, env and memory initialization */
 
 /* loongson-specific command line, env and memory initialization */
 
 extern void __init prom_init_memory(void);
 
 extern void __init prom_init_memory(void);
 
@@ -61,6 +63,12 @@ extern int mach_i8259_irq(void);
 
 #define LOONGSON_REG(x) \
 
 #define LOONGSON_REG(x) \
 
 	(*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))
 
 	(*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))
 
 
 
+#define LOONGSON3_REG8(base, x) \
 
+	(*(volatile u8 *)((char *)TO_UNCAC(base) + (x)))
 
+
 
+#define LOONGSON3_REG32(base, x) \
 
+	(*(volatile u32 *)((char *)TO_UNCAC(base) + (x)))
 
+
 
 #define LOONGSON_IRQ_BASE	32
 
 #define LOONGSON_IRQ_BASE	32
 
 #define LOONGSON2_PERFCNT_IRQ	(MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
 
 #define LOONGSON2_PERFCNT_IRQ	(MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
 
 
 
@@ -86,6 +94,10 @@ static inline void do_perfcnt_IRQ(void)
 
 #define LOONGSON_REG_BASE	0x1fe00000
 
 #define LOONGSON_REG_BASE	0x1fe00000
 
 #define LOONGSON_REG_SIZE	0x00100000	/* 256Bytes + 256Bytes + ??? */
 
 #define LOONGSON_REG_SIZE	0x00100000	/* 256Bytes + 256Bytes + ??? */
 
 #define LOONGSON_REG_TOP	(LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
 
 #define LOONGSON_REG_TOP	(LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
 
+/* Loongson-3 specific registers */
 
+#define LOONGSON3_REG_BASE	0x3ff00000
 
+#define LOONGSON3_REG_SIZE	0x00100000	/* 256Bytes + 256Bytes + ??? */
 
+#define LOONGSON3_REG_TOP	(LOONGSON3_REG_BASE+LOONGSON3_REG_SIZE-1)
 
 
 
 #define LOONGSON_LIO1_BASE	0x1ff00000
 
 #define LOONGSON_LIO1_BASE	0x1ff00000
 
 #define LOONGSON_LIO1_SIZE	0x00100000	/* 1M */
 
 #define LOONGSON_LIO1_SIZE	0x00100000	/* 1M */
 
@@ -101,7 +113,13 @@ static inline void do_perfcnt_IRQ(void)
 
 #define LOONGSON_PCICFG_BASE	0x1fe80000
 
 #define LOONGSON_PCICFG_BASE	0x1fe80000
 
 #define LOONGSON_PCICFG_SIZE	0x00000800	/* 2K */
 
 #define LOONGSON_PCICFG_SIZE	0x00000800	/* 2K */
 
 #define LOONGSON_PCICFG_TOP	(LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1)
 
 #define LOONGSON_PCICFG_TOP	(LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1)
 
+
 
+#if defined(CONFIG_HT_PCI)
 
+#define LOONGSON_PCIIO_BASE	loongson_sysconf.pci_io_base
 
+#else
 
 #define LOONGSON_PCIIO_BASE	0x1fd00000
 
 #define LOONGSON_PCIIO_BASE	0x1fd00000
 
+#endif
 
+
 
 #define LOONGSON_PCIIO_SIZE	0x00100000	/* 1M */
 
 #define LOONGSON_PCIIO_SIZE	0x00100000	/* 1M */
 
 #define LOONGSON_PCIIO_TOP	(LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1)
 
 #define LOONGSON_PCIIO_TOP	(LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1)
 
 
 
@@ -231,6 +249,9 @@ static inline void do_perfcnt_IRQ(void)
 
 #define LOONGSON_PXARB_CFG		LOONGSON_REG(LOONGSON_REGBASE + 0x68)
 
 #define LOONGSON_PXARB_CFG		LOONGSON_REG(LOONGSON_REGBASE + 0x68)
 
 #define LOONGSON_PXARB_STATUS		LOONGSON_REG(LOONGSON_REGBASE + 0x6c)
 
 #define LOONGSON_PXARB_STATUS		LOONGSON_REG(LOONGSON_REGBASE + 0x6c)
 
 
 
+/* Chip Config */
 
+#define LOONGSON_CHIPCFG0		LOONGSON_REG(LOONGSON_REGBASE + 0x80)
 
+
 
 /* pcimap */
 
 /* pcimap */
 
 
 
 #define LOONGSON_PCIMAP_PCIMAP_LO0	0x0000003f
 
 #define LOONGSON_PCIMAP_PCIMAP_LO0	0x0000003f
 
@@ -246,9 +267,6 @@ static inline void do_perfcnt_IRQ(void)
 
 #ifdef CONFIG_CPU_SUPPORTS_CPUFREQ
 
 #ifdef CONFIG_CPU_SUPPORTS_CPUFREQ
 
 #include <linux/cpufreq.h>
 
 #include <linux/cpufreq.h>
 
 extern struct cpufreq_frequency_table loongson2_clockmod_table[];
 
 extern struct cpufreq_frequency_table loongson2_clockmod_table[];
 
-
 
-/* Chip Config */
 
-#define LOONGSON_CHIPCFG0		LOONGSON_REG(LOONGSON_REGBASE + 0x80)
 
 #endif
 
 #endif
 
 
 
 /*
 
 /*

+ 6 - 0
arch/mips/include/asm/mach-loongson/machine.h
Vizualizați fișierul 

@@ -24,4 +24,10 @@
 
 
 
 #endif
 
 #endif
 
 
 
+#ifdef CONFIG_LEMOTE_MACH3A
 
+
 
+#define LOONGSON_MACHTYPE MACH_LEMOTE_A1101
 
+
 
+#endif /* CONFIG_LEMOTE_MACH3A */
 
+
 
 #endif /* __ASM_MACH_LOONGSON_MACHINE_H */
 
 #endif /* __ASM_MACH_LOONGSON_MACHINE_H */

+ 5 - 0
arch/mips/include/asm/mach-loongson/pci.h
Vizualizați fișierul 

@@ -40,8 +40,13 @@ extern struct pci_ops loongson_pci_ops;
 
 #else	/* loongson2f/32bit & loongson2e */
 
 #else	/* loongson2f/32bit & loongson2e */
 
 
 
 /* this pci memory space is mapped by pcimap in pci.c */
 
 /* this pci memory space is mapped by pcimap in pci.c */
 
+#ifdef CONFIG_CPU_LOONGSON3
 
+#define LOONGSON_PCI_MEM_START	0x40000000UL
 
+#define LOONGSON_PCI_MEM_END	0x7effffffUL
 
+#else
 
 #define LOONGSON_PCI_MEM_START	LOONGSON_PCILO1_BASE
 
 #define LOONGSON_PCI_MEM_START	LOONGSON_PCILO1_BASE
 
 #define LOONGSON_PCI_MEM_END	(LOONGSON_PCILO1_BASE + 0x04000000 * 2)
 
 #define LOONGSON_PCI_MEM_END	(LOONGSON_PCILO1_BASE + 0x04000000 * 2)
 
+#endif
 
 /* this is an offset from mips_io_port_base */
 
 /* this is an offset from mips_io_port_base */
 
 #define LOONGSON_PCI_IO_START	0x00004000UL
 
 #define LOONGSON_PCI_IO_START	0x00004000UL

+ 9 - 0
arch/mips/include/asm/mach-loongson/spaces.h
Vizualizați fișierul 

@@ -0,0 +1,9 @@
 
+#ifndef __ASM_MACH_LOONGSON_SPACES_H_
 
+#define __ASM_MACH_LOONGSON_SPACES_H_
 
+
 
+#if defined(CONFIG_64BIT)
 
+#define CAC_BASE        _AC(0x9800000000000000, UL)
 
+#endif /* CONFIG_64BIT */
 
+
 
+#include <asm/mach-generic/spaces.h>
 
+#endif

+ 114 - 1
arch/mips/include/asm/mach-malta/kernel-entry-init.h
Vizualizați fișierul 

@@ -5,10 +5,80 @@
 
  *
 
  *
 
  * Chris Dearman (chris@mips.com)
 
  * Chris Dearman (chris@mips.com)
 
  * Copyright (C) 2007 Mips Technologies, Inc.
 
  * Copyright (C) 2007 Mips Technologies, Inc.
 
+ * Copyright (C) 2014 Imagination Technologies Ltd.
 
  */
 
  */
 
 #ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
 
 #ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
 
 #define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
 
 #define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
 
 
 
+	/*
 
+	 * Prepare segments for EVA boot:
 
+	 *
 
+	 * This is in case the processor boots in legacy configuration
 
+	 * (SI_EVAReset is de-asserted and CONFIG5.K == 0)
 
+	 *
 
+	 * On entry, t1 is loaded with CP0_CONFIG
 
+	 *
 
+	 * ========================= Mappings =============================
 
+	 * Virtual memory           Physical memory           Mapping
 
+	 * 0x00000000 - 0x7fffffff  0x80000000 - 0xfffffffff   MUSUK (kuseg)
 
+	 *                          Flat 2GB physical memory
 
+	 *
 
+	 * 0x80000000 - 0x9fffffff  0x00000000 - 0x1ffffffff   MUSUK (kseg0)
 
+	 * 0xa0000000 - 0xbf000000  0x00000000 - 0x1ffffffff   MUSUK (kseg1)
 
+	 * 0xc0000000 - 0xdfffffff             -                 MK  (kseg2)
 
+	 * 0xe0000000 - 0xffffffff             -                 MK  (kseg3)
 
+	 *
 
+	 *
 
+	 * Lowmem is expanded to 2GB
 
+	 */
 
+	.macro	eva_entry
 
+	/*
 
+	 * Get Config.K0 value and use it to program
 
+	 * the segmentation registers
 
+	 */
 
+	andi	t1, 0x7 /* CCA */
 
+	move	t2, t1
 
+	ins	t2, t1, 16, 3
 
+	/* SegCtl0 */
 
+	li      t0, ((MIPS_SEGCFG_MK << MIPS_SEGCFG_AM_SHIFT) |		\
 
+		(0 << MIPS_SEGCFG_PA_SHIFT) |				\
 
+		(1 << MIPS_SEGCFG_EU_SHIFT)) |				\
 
+		(((MIPS_SEGCFG_MK << MIPS_SEGCFG_AM_SHIFT) |		\
 
+		(0 << MIPS_SEGCFG_PA_SHIFT) |				\
 
+		(1 << MIPS_SEGCFG_EU_SHIFT)) << 16)
 
+	or	t0, t2
 
+	mtc0	t0, $5, 2
 
+
 
+	/* SegCtl1 */
 
+	li      t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) |	\
 
+		(0 << MIPS_SEGCFG_PA_SHIFT) |				\
 
+		(2 << MIPS_SEGCFG_C_SHIFT) |				\
 
+		(1 << MIPS_SEGCFG_EU_SHIFT)) |				\
 
+		(((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) |		\
 
+		(0 << MIPS_SEGCFG_PA_SHIFT) |				\
 
+		(1 << MIPS_SEGCFG_EU_SHIFT)) << 16)
 
+	ins	t0, t1, 16, 3
 
+	mtc0	t0, $5, 3
 
+
 
+	/* SegCtl2 */
 
+	li	t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) |	\
 
+		(6 << MIPS_SEGCFG_PA_SHIFT) |				\
 
+		(1 << MIPS_SEGCFG_EU_SHIFT)) |				\
 
+		(((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) |		\
 
+		(4 << MIPS_SEGCFG_PA_SHIFT) |				\
 
+		(1 << MIPS_SEGCFG_EU_SHIFT)) << 16)
 
+	or	t0, t2
 
+	mtc0	t0, $5, 4
 
+
 
+	jal	mips_ihb
 
+	mfc0    t0, $16, 5
 
+	li      t2, 0x40000000      /* K bit */
 
+	or      t0, t0, t2
 
+	mtc0    t0, $16, 5
 
+	sync
 
+	jal	mips_ihb
 
+	.endm
 
+
 
 	.macro	kernel_entry_setup
 
 	.macro	kernel_entry_setup
 
 #ifdef CONFIG_MIPS_MT_SMTC
 
 #ifdef CONFIG_MIPS_MT_SMTC
 
 	mfc0	t0, CP0_CONFIG
 
 	mfc0	t0, CP0_CONFIG
 
@@ -39,14 +109,57 @@
 
 nonmt_processor:
 
 nonmt_processor:
 
 	.asciz	"SMTC kernel requires the MT ASE to run\n"
 
 	.asciz	"SMTC kernel requires the MT ASE to run\n"
 
 	__FINIT
 
 	__FINIT
 
-0:
 
 #endif
 
 #endif
 
+
 
+#ifdef CONFIG_EVA
 
+	sync
 
+	ehb
 
+
 
+	mfc0    t1, CP0_CONFIG
 
+	bgez    t1, 9f
 
+	mfc0	t0, CP0_CONFIG, 1
 
+	bgez	t0, 9f
 
+	mfc0	t0, CP0_CONFIG, 2
 
+	bgez	t0, 9f
 
+	mfc0	t0, CP0_CONFIG, 3
 
+	sll     t0, t0, 6   /* SC bit */
 
+	bgez    t0, 9f
 
+
 
+	eva_entry
 
+	b       0f
 
+9:
 
+	/* Assume we came from YAMON... */
 
+	PTR_LA	v0, 0x9fc00534	/* YAMON print */
 
+	lw	v0, (v0)
 
+	move	a0, zero
 
+	PTR_LA  a1, nonsc_processor
 
+	jal	v0
 
+
 
+	PTR_LA	v0, 0x9fc00520	/* YAMON exit */
 
+	lw	v0, (v0)
 
+	li	a0, 1
 
+	jal	v0
 
+
 
+1:	b	1b
 
+	nop
 
+	__INITDATA
 
+nonsc_processor:
 
+	.asciz  "EVA kernel requires a MIPS core with Segment Control implemented\n"
 
+	__FINIT
 
+#endif /* CONFIG_EVA */
 
+0:
 
 	.endm
 
 	.endm
 
 
 
 /*
 
 /*
 
  * Do SMP slave processor setup necessary before we can safely execute C code.
 
  * Do SMP slave processor setup necessary before we can safely execute C code.
 
  */
 
  */
 
 	.macro	smp_slave_setup
 
 	.macro	smp_slave_setup
 
+#ifdef CONFIG_EVA
 
+	sync
 
+	ehb
 
+	mfc0    t1, CP0_CONFIG
 
+	eva_entry
 
+#endif
 
 	.endm
 
 	.endm
 
 
 
 #endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */
 
 #endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */

+ 46 - 0
arch/mips/include/asm/mach-malta/spaces.h
Vizualizați fișierul 

@@ -0,0 +1,46 @@
 
+/*
 
+ * This file is subject to the terms and conditions of the GNU General Public
 
+ * License.  See the file "COPYING" in the main directory of this archive
 
+ * for more details.
 
+ *
 
+ * Copyright (C) 2014 Imagination Technologies Ltd.
 
+ */
 
+
 
+#ifndef _ASM_MALTA_SPACES_H
 
+#define _ASM_MALTA_SPACES_H
 
+
 
+#ifdef CONFIG_EVA
 
+
 
+/*
 
+ * Traditional Malta Board Memory Map for EVA
 
+ *
 
+ * 0x00000000 - 0x0fffffff: 1st RAM region, 256MB
 
+ * 0x10000000 - 0x1bffffff: GIC and CPC Control Registers
 
+ * 0x1c000000 - 0x1fffffff: I/O And Flash
 
+ * 0x20000000 - 0x7fffffff: 2nd RAM region, 1.5GB
 
+ * 0x80000000 - 0xffffffff: Physical memory aliases to 0x0 (2GB)
 
+ *
 
+ * The kernel is still located in 0x80000000(kseg0). However,
 
+ * the physical mask has been shifted to 0x80000000 which exploits the alias
 
+ * on the Malta board. As a result of which, we override the __pa_symbol
 
+ * to peform direct mapping from virtual to physical addresses. In other
 
+ * words, the 0x80000000 virtual address maps to 0x80000000 physical address
 
+ * which in turn aliases to 0x0. We do this in order to be able to use a flat
 
+ * 2GB of memory (0x80000000 - 0xffffffff) so we can avoid the I/O hole in
 
+ * 0x10000000 - 0x1fffffff.
 
+ * The last 64KB of physical memory are reserved for correct HIGHMEM
 
+ * macros arithmetics.
 
+ *
 
+ */
 
+
 
+#define PAGE_OFFSET	_AC(0x0, UL)
 
+#define PHYS_OFFSET	_AC(0x80000000, UL)
 
+#define HIGHMEM_START	_AC(0xffff0000, UL)
 
+
 
+#define __pa_symbol(x)	(RELOC_HIDE((unsigned long)(x), 0))
 
+
 
+#endif /* CONFIG_EVA */
 
+
 
+#include <asm/mach-generic/spaces.h>
 
+
 
+#endif /* _ASM_MALTA_SPACES_H */

+ 6 - 6
arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h
Vizualizați fișierul 

@@ -76,7 +76,7 @@ static inline void set_value_reg32(volatile u32 *const addr,
 
 
 
 	__asm__ __volatile__(
 
 	__asm__ __volatile__(
 
 	"	.set	push				\n"
 
 	"	.set	push				\n"
 
-	"	.set	mips3				\n"
 
+	"	.set	arch=r4000			\n"
 
 	"1:	ll	%0, %1	# set_value_reg32	\n"
 
 	"1:	ll	%0, %1	# set_value_reg32	\n"
 
 	"	and	%0, %2				\n"
 
 	"	and	%0, %2				\n"
 
 	"	or	%0, %3				\n"
 
 	"	or	%0, %3				\n"
 
@@ -98,7 +98,7 @@ static inline void set_reg32(volatile u32 *const addr,
 
 
 
 	__asm__ __volatile__(
 
 	__asm__ __volatile__(
 
 	"	.set	push				\n"
 
 	"	.set	push				\n"
 
-	"	.set	mips3				\n"
 
+	"	.set	arch=r4000			\n"
 
 	"1:	ll	%0, %1		# set_reg32	\n"
 
 	"1:	ll	%0, %1		# set_reg32	\n"
 
 	"	or	%0, %2				\n"
 
 	"	or	%0, %2				\n"
 
 	"	sc	%0, %1				\n"
 
 	"	sc	%0, %1				\n"
 
@@ -119,7 +119,7 @@ static inline void clear_reg32(volatile u32 *const addr,
 
 
 
 	__asm__ __volatile__(
 
 	__asm__ __volatile__(
 
 	"	.set	push				\n"
 
 	"	.set	push				\n"
 
-	"	.set	mips3				\n"
 
+	"	.set	arch=r4000			\n"
 
 	"1:	ll	%0, %1		# clear_reg32	\n"
 
 	"1:	ll	%0, %1		# clear_reg32	\n"
 
 	"	and	%0, %2				\n"
 
 	"	and	%0, %2				\n"
 
 	"	sc	%0, %1				\n"
 
 	"	sc	%0, %1				\n"
 
@@ -140,7 +140,7 @@ static inline void toggle_reg32(volatile u32 *const addr,
 
 
 
 	__asm__ __volatile__(
 
 	__asm__ __volatile__(
 
 	"	.set	push				\n"
 
 	"	.set	push				\n"
 
-	"	.set	mips3				\n"
 
+	"	.set	arch=r4000			\n"
 
 	"1:	ll	%0, %1		# toggle_reg32	\n"
 
 	"1:	ll	%0, %1		# toggle_reg32	\n"
 
 	"	xor	%0, %2				\n"
 
 	"	xor	%0, %2				\n"
 
 	"	sc	%0, %1				\n"
 
 	"	sc	%0, %1				\n"
 
@@ -216,7 +216,7 @@ static inline u32 blocking_read_reg32(volatile u32 *const addr)
 
 #define custom_read_reg32(address, tmp)				\
 
 #define custom_read_reg32(address, tmp)				\
 
 	__asm__ __volatile__(					\
 
 	__asm__ __volatile__(					\
 
 	"	.set	push				\n"	\
 
 	"	.set	push				\n"	\
 
-	"	.set	mips3				\n"	\
 
+	"	.set	arch=r4000			\n"	\
 
 	"1:	ll	%0, %1	#custom_read_reg32	\n"	\
 
 	"1:	ll	%0, %1	#custom_read_reg32	\n"	\
 
 	"	.set	pop				\n"	\
 
 	"	.set	pop				\n"	\
 
 	: "=r" (tmp), "=m" (*address)				\
 
 	: "=r" (tmp), "=m" (*address)				\
 
@@ -225,7 +225,7 @@ static inline u32 blocking_read_reg32(volatile u32 *const addr)
 
 #define custom_write_reg32(address, tmp)			\
 
 #define custom_write_reg32(address, tmp)			\
 
 	__asm__ __volatile__(					\
 
 	__asm__ __volatile__(					\
 
 	"	.set	push				\n"	\
 
 	"	.set	push				\n"	\
 
-	"	.set	mips3				\n"	\
 
+	"	.set	arch=r4000			\n"	\
 
 	"	sc	%0, %1	#custom_write_reg32	\n"	\
 
 	"	sc	%0, %1	#custom_write_reg32	\n"	\
 
 	"	"__beqz"%0, 1b				\n"	\
 
 	"	"__beqz"%0, 1b				\n"	\
 
 	"	nop					\n"	\
 
 	"	nop					\n"	\

+ 5 - 0
arch/mips/include/asm/mips-boards/malta.h
Vizualizați fișierul 

@@ -63,6 +63,11 @@ static inline unsigned long get_msc_port_base(unsigned long reg)
 
 #define GIC_BASE_ADDR			0x1bdc0000
 
 #define GIC_BASE_ADDR			0x1bdc0000
 
 #define GIC_ADDRSPACE_SZ		(128 * 1024)
 
 #define GIC_ADDRSPACE_SZ		(128 * 1024)
 
 
 
+/*
 
+ * CPC Specific definitions
 
+ */
 
+#define CPC_BASE_ADDR			0x1bde0000
 
+
 
 /*
 
 /*
 
  * MSC01 BIU Specific definitions
 
  * MSC01 BIU Specific definitions
 
  * FIXME : These should be elsewhere ?
 
  * FIXME : These should be elsewhere ?

+ 5 - 0
arch/mips/include/asm/mips-boards/piix4.h
Vizualizați fișierul 

@@ -50,4 +50,9 @@
 
 #define PIIX4_FUNC1_IDETIM_SECONDARY_HI		0x43
 
 #define PIIX4_FUNC1_IDETIM_SECONDARY_HI		0x43
 
 #define   PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN	(1 << 7)
 
 #define   PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN	(1 << 7)
 
 
 
+/* Power Management Configuration Space */
 
+#define PIIX4_FUNC3_PMBA			0x40
 
+#define PIIX4_FUNC3_PMREGMISC			0x80
 
+#define   PIIX4_FUNC3_PMREGMISC_EN			(1 << 0)
 
+
 
 #endif /* __ASM_MIPS_BOARDS_PIIX4_H */
 
 #endif /* __ASM_MIPS_BOARDS_PIIX4_H */

+ 322 - 0
arch/mips/include/asm/mips-cm.h
Vizualizați fișierul 

@@ -0,0 +1,322 @@
 
+/*
 
+ * Copyright (C) 2013 Imagination Technologies
 
+ * Author: Paul Burton <paul.burton@imgtec.com>
 
+ *
 
+ * This program is free software; you can redistribute it and/or modify it
 
+ * under the terms of the GNU General Public License as published by the
 
+ * Free Software Foundation;  either version 2 of the  License, or (at your
 
+ * option) any later version.
 
+ */
 
+
 
+#ifndef __MIPS_ASM_MIPS_CM_H__
 
+#define __MIPS_ASM_MIPS_CM_H__
 
+
 
+#include <linux/io.h>
 
+#include <linux/types.h>
 
+
 
+/* The base address of the CM GCR block */
 
+extern void __iomem *mips_cm_base;
 
+
 
+/* The base address of the CM L2-only sync region */
 
+extern void __iomem *mips_cm_l2sync_base;
 
+
 
+/**
 
+ * __mips_cm_phys_base - retrieve the physical base address of the CM
 
+ *
 
+ * This function returns the physical base address of the Coherence Manager
 
+ * global control block, or 0 if no Coherence Manager is present. It provides
 
+ * a default implementation which reads the CMGCRBase register where available,
 
+ * and may be overriden by platforms which determine this address in a
 
+ * different way by defining a function with the same prototype except for the
 
+ * name mips_cm_phys_base (without underscores).
 
+ */
 
+extern phys_t __mips_cm_phys_base(void);
 
+
 
+/**
 
+ * mips_cm_probe - probe for a Coherence Manager
 
+ *
 
+ * Attempt to detect the presence of a Coherence Manager. Returns 0 if a CM
 
+ * is successfully detected, else -errno.
 
+ */
 
+#ifdef CONFIG_MIPS_CM
 
+extern int mips_cm_probe(void);
 
+#else
 
+static inline int mips_cm_probe(void)
 
+{
 
+	return -ENODEV;
 
+}
 
+#endif
 
+
 
+/**
 
+ * mips_cm_present - determine whether a Coherence Manager is present
 
+ *
 
+ * Returns true if a CM is present in the system, else false.
 
+ */
 
+static inline bool mips_cm_present(void)
 
+{
 
+#ifdef CONFIG_MIPS_CM
 
+	return mips_cm_base != NULL;
 
+#else
 
+	return false;
 
+#endif
 
+}
 
+
 
+/**
 
+ * mips_cm_has_l2sync - determine whether an L2-only sync region is present
 
+ *
 
+ * Returns true if the system implements an L2-only sync region, else false.
 
+ */
 
+static inline bool mips_cm_has_l2sync(void)
 
+{
 
+#ifdef CONFIG_MIPS_CM
 
+	return mips_cm_l2sync_base != NULL;
 
+#else
 
+	return false;
 
+#endif
 
+}
 
+
 
+/* Offsets to register blocks from the CM base address */
 
+#define MIPS_CM_GCB_OFS		0x0000 /* Global Control Block */
 
+#define MIPS_CM_CLCB_OFS	0x2000 /* Core Local Control Block */
 
+#define MIPS_CM_COCB_OFS	0x4000 /* Core Other Control Block */
 
+#define MIPS_CM_GDB_OFS		0x6000 /* Global Debug Block */
 
+
 
+/* Total size of the CM memory mapped registers */
 
+#define MIPS_CM_GCR_SIZE	0x8000
 
+
 
+/* Size of the L2-only sync region */
 
+#define MIPS_CM_L2SYNC_SIZE	0x1000
 
+
 
+/* Macros to ease the creation of register access functions */
 
+#define BUILD_CM_R_(name, off)					\
 
+static inline u32 *addr_gcr_##name(void)			\
 
+{								\
 
+	return (u32 *)(mips_cm_base + (off));			\
 
+}								\
 
+								\
 
+static inline u32 read_gcr_##name(void)				\
 
+{								\
 
+	return __raw_readl(addr_gcr_##name());			\
 
+}
 
+
 
+#define BUILD_CM__W(name, off)					\
 
+static inline void write_gcr_##name(u32 value)			\
 
+{								\
 
+	__raw_writel(value, addr_gcr_##name());			\
 
+}
 
+
 
+#define BUILD_CM_RW(name, off)					\
 
+	BUILD_CM_R_(name, off)					\
 
+	BUILD_CM__W(name, off)
 
+
 
+#define BUILD_CM_Cx_R_(name, off)				\
 
+	BUILD_CM_R_(cl_##name, MIPS_CM_CLCB_OFS + (off))	\
 
+	BUILD_CM_R_(co_##name, MIPS_CM_COCB_OFS + (off))
 
+
 
+#define BUILD_CM_Cx__W(name, off)				\
 
+	BUILD_CM__W(cl_##name, MIPS_CM_CLCB_OFS + (off))	\
 
+	BUILD_CM__W(co_##name, MIPS_CM_COCB_OFS + (off))
 
+
 
+#define BUILD_CM_Cx_RW(name, off)				\
 
+	BUILD_CM_Cx_R_(name, off)				\
 
+	BUILD_CM_Cx__W(name, off)
 
+
 
+/* GCB register accessor functions */
 
+BUILD_CM_R_(config,		MIPS_CM_GCB_OFS + 0x00)
 
+BUILD_CM_RW(base,		MIPS_CM_GCB_OFS + 0x08)
 
+BUILD_CM_RW(access,		MIPS_CM_GCB_OFS + 0x20)
 
+BUILD_CM_R_(rev,		MIPS_CM_GCB_OFS + 0x30)
 
+BUILD_CM_RW(error_mask,		MIPS_CM_GCB_OFS + 0x40)
 
+BUILD_CM_RW(error_cause,	MIPS_CM_GCB_OFS + 0x48)
 
+BUILD_CM_RW(error_addr,		MIPS_CM_GCB_OFS + 0x50)
 
+BUILD_CM_RW(error_mult,		MIPS_CM_GCB_OFS + 0x58)
 
+BUILD_CM_RW(l2_only_sync_base,	MIPS_CM_GCB_OFS + 0x70)
 
+BUILD_CM_RW(gic_base,		MIPS_CM_GCB_OFS + 0x80)
 
+BUILD_CM_RW(cpc_base,		MIPS_CM_GCB_OFS + 0x88)
 
+BUILD_CM_RW(reg0_base,		MIPS_CM_GCB_OFS + 0x90)
 
+BUILD_CM_RW(reg0_mask,		MIPS_CM_GCB_OFS + 0x98)
 
+BUILD_CM_RW(reg1_base,		MIPS_CM_GCB_OFS + 0xa0)
 
+BUILD_CM_RW(reg1_mask,		MIPS_CM_GCB_OFS + 0xa8)
 
+BUILD_CM_RW(reg2_base,		MIPS_CM_GCB_OFS + 0xb0)
 
+BUILD_CM_RW(reg2_mask,		MIPS_CM_GCB_OFS + 0xb8)
 
+BUILD_CM_RW(reg3_base,		MIPS_CM_GCB_OFS + 0xc0)
 
+BUILD_CM_RW(reg3_mask,		MIPS_CM_GCB_OFS + 0xc8)
 
+BUILD_CM_R_(gic_status,		MIPS_CM_GCB_OFS + 0xd0)
 
+BUILD_CM_R_(cpc_status,		MIPS_CM_GCB_OFS + 0xf0)
 
+
 
+/* Core Local & Core Other register accessor functions */
 
+BUILD_CM_Cx_RW(reset_release,	0x00)
 
+BUILD_CM_Cx_RW(coherence,	0x08)
 
+BUILD_CM_Cx_R_(config,		0x10)
 
+BUILD_CM_Cx_RW(other,		0x18)
 
+BUILD_CM_Cx_RW(reset_base,	0x20)
 
+BUILD_CM_Cx_R_(id,		0x28)
 
+BUILD_CM_Cx_RW(reset_ext_base,	0x30)
 
+BUILD_CM_Cx_R_(tcid_0_priority,	0x40)
 
+BUILD_CM_Cx_R_(tcid_1_priority,	0x48)
 
+BUILD_CM_Cx_R_(tcid_2_priority,	0x50)
 
+BUILD_CM_Cx_R_(tcid_3_priority,	0x58)
 
+BUILD_CM_Cx_R_(tcid_4_priority,	0x60)
 
+BUILD_CM_Cx_R_(tcid_5_priority,	0x68)
 
+BUILD_CM_Cx_R_(tcid_6_priority,	0x70)
 
+BUILD_CM_Cx_R_(tcid_7_priority,	0x78)
 
+BUILD_CM_Cx_R_(tcid_8_priority,	0x80)
 
+
 
+/* GCR_CONFIG register fields */
 
+#define CM_GCR_CONFIG_NUMIOCU_SHF		8
 
+#define CM_GCR_CONFIG_NUMIOCU_MSK		(_ULCAST_(0xf) << 8)
 
+#define CM_GCR_CONFIG_PCORES_SHF		0
 
+#define CM_GCR_CONFIG_PCORES_MSK		(_ULCAST_(0xff) << 0)
 
+
 
+/* GCR_BASE register fields */
 
+#define CM_GCR_BASE_GCRBASE_SHF			15
 
+#define CM_GCR_BASE_GCRBASE_MSK			(_ULCAST_(0x1ffff) << 15)
 
+#define CM_GCR_BASE_CMDEFTGT_SHF		0
 
+#define CM_GCR_BASE_CMDEFTGT_MSK		(_ULCAST_(0x3) << 0)
 
+#define  CM_GCR_BASE_CMDEFTGT_DISABLED		0
 
+#define  CM_GCR_BASE_CMDEFTGT_MEM		1
 
+#define  CM_GCR_BASE_CMDEFTGT_IOCU0		2
 
+#define  CM_GCR_BASE_CMDEFTGT_IOCU1		3
 
+
 
+/* GCR_ACCESS register fields */
 
+#define CM_GCR_ACCESS_ACCESSEN_SHF		0
 
+#define CM_GCR_ACCESS_ACCESSEN_MSK		(_ULCAST_(0xff) << 0)
 
+
 
+/* GCR_REV register fields */
 
+#define CM_GCR_REV_MAJOR_SHF			8
 
+#define CM_GCR_REV_MAJOR_MSK			(_ULCAST_(0xff) << 8)
 
+#define CM_GCR_REV_MINOR_SHF			0
 
+#define CM_GCR_REV_MINOR_MSK			(_ULCAST_(0xff) << 0)
 
+
 
+/* GCR_ERROR_CAUSE register fields */
 
+#define CM_GCR_ERROR_CAUSE_ERRTYPE_SHF		27
 
+#define CM_GCR_ERROR_CAUSE_ERRTYPE_MSK		(_ULCAST_(0x1f) << 27)
 
+#define CM_GCR_ERROR_CAUSE_ERRINFO_SHF		0
 
+#define CM_GCR_ERROR_CAUSE_ERRINGO_MSK		(_ULCAST_(0x7ffffff) << 0)
 
+
 
+/* GCR_ERROR_MULT register fields */
 
+#define CM_GCR_ERROR_MULT_ERR2ND_SHF		0
 
+#define CM_GCR_ERROR_MULT_ERR2ND_MSK		(_ULCAST_(0x1f) << 0)
 
+
 
+/* GCR_L2_ONLY_SYNC_BASE register fields */
 
+#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_SHF	12
 
+#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_MSK	(_ULCAST_(0xfffff) << 12)
 
+#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_SHF	0
 
+#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_MSK	(_ULCAST_(0x1) << 0)
 
+
 
+/* GCR_GIC_BASE register fields */
 
+#define CM_GCR_GIC_BASE_GICBASE_SHF		17
 
+#define CM_GCR_GIC_BASE_GICBASE_MSK		(_ULCAST_(0x7fff) << 17)
 
+#define CM_GCR_GIC_BASE_GICEN_SHF		0
 
+#define CM_GCR_GIC_BASE_GICEN_MSK		(_ULCAST_(0x1) << 0)
 
+
 
+/* GCR_CPC_BASE register fields */
 
+#define CM_GCR_CPC_BASE_CPCBASE_SHF		17
 
+#define CM_GCR_CPC_BASE_CPCBASE_MSK		(_ULCAST_(0x7fff) << 17)
 
+#define CM_GCR_CPC_BASE_CPCEN_SHF		0
 
+#define CM_GCR_CPC_BASE_CPCEN_MSK		(_ULCAST_(0x1) << 0)
 
+
 
+/* GCR_REGn_BASE register fields */
 
+#define CM_GCR_REGn_BASE_BASEADDR_SHF		16
 
+#define CM_GCR_REGn_BASE_BASEADDR_MSK		(_ULCAST_(0xffff) << 16)
 
+
 
+/* GCR_REGn_MASK register fields */
 
+#define CM_GCR_REGn_MASK_ADDRMASK_SHF		16
 
+#define CM_GCR_REGn_MASK_ADDRMASK_MSK		(_ULCAST_(0xffff) << 16)
 
+#define CM_GCR_REGn_MASK_CCAOVR_SHF		5
 
+#define CM_GCR_REGn_MASK_CCAOVR_MSK		(_ULCAST_(0x3) << 5)
 
+#define CM_GCR_REGn_MASK_CCAOVREN_SHF		4
 
+#define CM_GCR_REGn_MASK_CCAOVREN_MSK		(_ULCAST_(0x1) << 4)
 
+#define CM_GCR_REGn_MASK_DROPL2_SHF		2
 
+#define CM_GCR_REGn_MASK_DROPL2_MSK		(_ULCAST_(0x1) << 2)
 
+#define CM_GCR_REGn_MASK_CMTGT_SHF		0
 
+#define CM_GCR_REGn_MASK_CMTGT_MSK		(_ULCAST_(0x3) << 0)
 
+#define  CM_GCR_REGn_MASK_CMTGT_DISABLED	(_ULCAST_(0x0) << 0)
 
+#define  CM_GCR_REGn_MASK_CMTGT_MEM		(_ULCAST_(0x1) << 0)
 
+#define  CM_GCR_REGn_MASK_CMTGT_IOCU0		(_ULCAST_(0x2) << 0)
 
+#define  CM_GCR_REGn_MASK_CMTGT_IOCU1		(_ULCAST_(0x3) << 0)
 
+
 
+/* GCR_GIC_STATUS register fields */
 
+#define CM_GCR_GIC_STATUS_EX_SHF		0
 
+#define CM_GCR_GIC_STATUS_EX_MSK		(_ULCAST_(0x1) << 0)
 
+
 
+/* GCR_CPC_STATUS register fields */
 
+#define CM_GCR_CPC_STATUS_EX_SHF		0
 
+#define CM_GCR_CPC_STATUS_EX_MSK		(_ULCAST_(0x1) << 0)
 
+
 
+/* GCR_Cx_COHERENCE register fields */
 
+#define CM_GCR_Cx_COHERENCE_COHDOMAINEN_SHF	0
 
+#define CM_GCR_Cx_COHERENCE_COHDOMAINEN_MSK	(_ULCAST_(0xff) << 0)
 
+
 
+/* GCR_Cx_CONFIG register fields */
 
+#define CM_GCR_Cx_CONFIG_IOCUTYPE_SHF		10
 
+#define CM_GCR_Cx_CONFIG_IOCUTYPE_MSK		(_ULCAST_(0x3) << 10)
 
+#define CM_GCR_Cx_CONFIG_PVPE_SHF		0
 
+#define CM_GCR_Cx_CONFIG_PVPE_MSK		(_ULCAST_(0x1ff) << 0)
 
+
 
+/* GCR_Cx_OTHER register fields */
 
+#define CM_GCR_Cx_OTHER_CORENUM_SHF		16
 
+#define CM_GCR_Cx_OTHER_CORENUM_MSK		(_ULCAST_(0xffff) << 16)
 
+
 
+/* GCR_Cx_RESET_BASE register fields */
 
+#define CM_GCR_Cx_RESET_BASE_BEVEXCBASE_SHF	12
 
+#define CM_GCR_Cx_RESET_BASE_BEVEXCBASE_MSK	(_ULCAST_(0xfffff) << 12)
 
+
 
+/* GCR_Cx_RESET_EXT_BASE register fields */
 
+#define CM_GCR_Cx_RESET_EXT_BASE_EVARESET_SHF	31
 
+#define CM_GCR_Cx_RESET_EXT_BASE_EVARESET_MSK	(_ULCAST_(0x1) << 31)
 
+#define CM_GCR_Cx_RESET_EXT_BASE_UEB_SHF	30
 
+#define CM_GCR_Cx_RESET_EXT_BASE_UEB_MSK	(_ULCAST_(0x1) << 30)
 
+#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK_SHF	20
 
+#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK_MSK	(_ULCAST_(0xff) << 20)
 
+#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA_SHF	1
 
+#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA_MSK	(_ULCAST_(0x7f) << 1)
 
+#define CM_GCR_Cx_RESET_EXT_BASE_PRESENT_SHF	0
 
+#define CM_GCR_Cx_RESET_EXT_BASE_PRESENT_MSK	(_ULCAST_(0x1) << 0)
 
+
 
+/**
 
+ * mips_cm_numcores - return the number of cores present in the system
 
+ *
 
+ * Returns the value of the PCORES field of the GCR_CONFIG register plus 1, or
 
+ * zero if no Coherence Manager is present.
 
+ */
 
+static inline unsigned mips_cm_numcores(void)
 
+{
 
+	if (!mips_cm_present())
 
+		return 0;
 
+
 
+	return ((read_gcr_config() & CM_GCR_CONFIG_PCORES_MSK)
 
+		>> CM_GCR_CONFIG_PCORES_SHF) + 1;
 
+}
 
+
 
+/**
 
+ * mips_cm_numiocu - return the number of IOCUs present in the system
 
+ *
 
+ * Returns the value of the NUMIOCU field of the GCR_CONFIG register, or zero
 
+ * if no Coherence Manager is present.
 
+ */
 
+static inline unsigned mips_cm_numiocu(void)
 
+{
 
+	if (!mips_cm_present())
 
+		return 0;
 
+
 
+	return (read_gcr_config() & CM_GCR_CONFIG_NUMIOCU_MSK)
 
+		>> CM_GCR_CONFIG_NUMIOCU_SHF;
 
+}
 
+
 
+/**
 
+ * mips_cm_l2sync - perform an L2-only sync operation
 
+ *
 
+ * If an L2-only sync region is present in the system then this function
 
+ * performs and L2-only sync and returns zero. Otherwise it returns -ENODEV.
 
+ */
 
+static inline int mips_cm_l2sync(void)
 
+{
 
+	if (!mips_cm_has_l2sync())
 
+		return -ENODEV;
 
+
 
+	writel(0, mips_cm_l2sync_base);
 
+	return 0;
 
+}
 
+
 
+#endif /* __MIPS_ASM_MIPS_CM_H__ */

+ 150 - 0
arch/mips/include/asm/mips-cpc.h
Vizualizați fișierul 

@@ -0,0 +1,150 @@
 
+/*
 
+ * Copyright (C) 2013 Imagination Technologies
 
+ * Author: Paul Burton <paul.burton@imgtec.com>
 
+ *
 
+ * This program is free software; you can redistribute it and/or modify it
 
+ * under the terms of the GNU General Public License as published by the
 
+ * Free Software Foundation;  either version 2 of the  License, or (at your
 
+ * option) any later version.
 
+ */
 
+
 
+#ifndef __MIPS_ASM_MIPS_CPC_H__
 
+#define __MIPS_ASM_MIPS_CPC_H__
 
+
 
+#include <linux/io.h>
 
+#include <linux/types.h>
 
+
 
+/* The base address of the CPC registers */
 
+extern void __iomem *mips_cpc_base;
 
+
 
+/**
 
+ * mips_cpc_default_phys_base - retrieve the default physical base address of
 
+ *                              the CPC
 
+ *
 
+ * Returns the default physical base address of the Cluster Power Controller
 
+ * memory mapped registers. This is platform dependant & must therefore be
 
+ * implemented per-platform.
 
+ */
 
+extern phys_t mips_cpc_default_phys_base(void);
 
+
 
+/**
 
+ * mips_cpc_phys_base - retrieve the physical base address of the CPC
 
+ *
 
+ * This function returns the physical base address of the Cluster Power
 
+ * Controller memory mapped registers, or 0 if no Cluster Power Controller
 
+ * is present. It may be overriden by individual platforms which determine
 
+ * this address in a different way.
 
+ */
 
+extern phys_t __weak mips_cpc_phys_base(void);
 
+
 
+/**
 
+ * mips_cpc_probe - probe for a Cluster Power Controller
 
+ *
 
+ * Attempt to detect the presence of a Cluster Power Controller. Returns 0 if
 
+ * a CPC is successfully detected, else -errno.
 
+ */
 
+#ifdef CONFIG_MIPS_CPC
 
+extern int mips_cpc_probe(void);
 
+#else
 
+static inline int mips_cpc_probe(void)
 
+{
 
+	return -ENODEV;
 
+}
 
+#endif
 
+
 
+/**
 
+ * mips_cpc_present - determine whether a Cluster Power Controller is present
 
+ *
 
+ * Returns true if a CPC is present in the system, else false.
 
+ */
 
+static inline bool mips_cpc_present(void)
 
+{
 
+#ifdef CONFIG_MIPS_CPC
 
+	return mips_cpc_base != NULL;
 
+#else
 
+	return false;
 
+#endif
 
+}
 
+
 
+/* Offsets from the CPC base address to various control blocks */
 
+#define MIPS_CPC_GCB_OFS	0x0000
 
+#define MIPS_CPC_CLCB_OFS	0x2000
 
+#define MIPS_CPC_COCB_OFS	0x4000
 
+
 
+/* Macros to ease the creation of register access functions */
 
+#define BUILD_CPC_R_(name, off) \
 
+static inline u32 read_cpc_##name(void)				\
 
+{								\
 
+	return __raw_readl(mips_cpc_base + (off));		\
 
+}
 
+
 
+#define BUILD_CPC__W(name, off) \
 
+static inline void write_cpc_##name(u32 value)			\
 
+{								\
 
+	__raw_writel(value, mips_cpc_base + (off));		\
 
+}
 
+
 
+#define BUILD_CPC_RW(name, off)					\
 
+	BUILD_CPC_R_(name, off)					\
 
+	BUILD_CPC__W(name, off)
 
+
 
+#define BUILD_CPC_Cx_R_(name, off)				\
 
+	BUILD_CPC_R_(cl_##name, MIPS_CPC_CLCB_OFS + (off))	\
 
+	BUILD_CPC_R_(co_##name, MIPS_CPC_COCB_OFS + (off))
 
+
 
+#define BUILD_CPC_Cx__W(name, off)				\
 
+	BUILD_CPC__W(cl_##name, MIPS_CPC_CLCB_OFS + (off))	\
 
+	BUILD_CPC__W(co_##name, MIPS_CPC_COCB_OFS + (off))
 
+
 
+#define BUILD_CPC_Cx_RW(name, off)				\
 
+	BUILD_CPC_Cx_R_(name, off)				\
 
+	BUILD_CPC_Cx__W(name, off)
 
+
 
+/* GCB register accessor functions */
 
+BUILD_CPC_RW(access,		MIPS_CPC_GCB_OFS + 0x00)
 
+BUILD_CPC_RW(seqdel,		MIPS_CPC_GCB_OFS + 0x08)
 
+BUILD_CPC_RW(rail,		MIPS_CPC_GCB_OFS + 0x10)
 
+BUILD_CPC_RW(resetlen,		MIPS_CPC_GCB_OFS + 0x18)
 
+BUILD_CPC_R_(revision,		MIPS_CPC_GCB_OFS + 0x20)
 
+
 
+/* Core Local & Core Other accessor functions */
 
+BUILD_CPC_Cx_RW(cmd,		0x00)
 
+BUILD_CPC_Cx_RW(stat_conf,	0x08)
 
+BUILD_CPC_Cx_RW(other,		0x10)
 
+
 
+/* CPC_Cx_CMD register fields */
 
+#define CPC_Cx_CMD_SHF				0
 
+#define CPC_Cx_CMD_MSK				(_ULCAST_(0xf) << 0)
 
+#define  CPC_Cx_CMD_CLOCKOFF			(_ULCAST_(0x1) << 0)
 
+#define  CPC_Cx_CMD_PWRDOWN			(_ULCAST_(0x2) << 0)
 
+#define  CPC_Cx_CMD_PWRUP			(_ULCAST_(0x3) << 0)
 
+#define  CPC_Cx_CMD_RESET			(_ULCAST_(0x4) << 0)
 
+
 
+/* CPC_Cx_STAT_CONF register fields */
 
+#define CPC_Cx_STAT_CONF_PWRUPE_SHF		23
 
+#define CPC_Cx_STAT_CONF_PWRUPE_MSK		(_ULCAST_(0x1) << 23)
 
+#define CPC_Cx_STAT_CONF_SEQSTATE_SHF		19
 
+#define CPC_Cx_STAT_CONF_SEQSTATE_MSK		(_ULCAST_(0xf) << 19)
 
+#define  CPC_Cx_STAT_CONF_SEQSTATE_D0		(_ULCAST_(0x0) << 19)
 
+#define  CPC_Cx_STAT_CONF_SEQSTATE_U0		(_ULCAST_(0x1) << 19)
 
+#define  CPC_Cx_STAT_CONF_SEQSTATE_U1		(_ULCAST_(0x2) << 19)
 
+#define  CPC_Cx_STAT_CONF_SEQSTATE_U2		(_ULCAST_(0x3) << 19)
 
+#define  CPC_Cx_STAT_CONF_SEQSTATE_U3		(_ULCAST_(0x4) << 19)
 
+#define  CPC_Cx_STAT_CONF_SEQSTATE_U4		(_ULCAST_(0x5) << 19)
 
+#define  CPC_Cx_STAT_CONF_SEQSTATE_U5		(_ULCAST_(0x6) << 19)
 
+#define  CPC_Cx_STAT_CONF_SEQSTATE_U6		(_ULCAST_(0x7) << 19)
 
+#define  CPC_Cx_STAT_CONF_SEQSTATE_D1		(_ULCAST_(0x8) << 19)
 
+#define  CPC_Cx_STAT_CONF_SEQSTATE_D3		(_ULCAST_(0x9) << 19)
 
+#define  CPC_Cx_STAT_CONF_SEQSTATE_D2		(_ULCAST_(0xa) << 19)
 
+#define CPC_Cx_STAT_CONF_CLKGAT_IMPL_SHF	17
 
+#define CPC_Cx_STAT_CONF_CLKGAT_IMPL_MSK	(_ULCAST_(0x1) << 17)
 
+#define CPC_Cx_STAT_CONF_PWRDN_IMPL_SHF		16
 
+#define CPC_Cx_STAT_CONF_PWRDN_IMPL_MSK		(_ULCAST_(0x1) << 16)
 
+#define CPC_Cx_STAT_CONF_EJTAG_PROBE_SHF	15
 
+#define CPC_Cx_STAT_CONF_EJTAG_PROBE_MSK	(_ULCAST_(0x1) << 15)
 
+
 
+/* CPC_Cx_OTHER register fields */
 
+#define CPC_Cx_OTHER_CORENUM_SHF		16
 
+#define CPC_Cx_OTHER_CORENUM_MSK		(_ULCAST_(0xff) << 16)
 
+
 
+#endif /* __MIPS_ASM_MIPS_CPC_H__ */

+ 5 - 0
arch/mips/include/asm/mips_mt.h
Vizualizați fișierul 

@@ -18,7 +18,12 @@ extern cpumask_t mt_fpu_cpumask;
 
 extern unsigned long mt_fpemul_threshold;
 
 extern unsigned long mt_fpemul_threshold;
 
 
 
 extern void mips_mt_regdump(unsigned long previous_mvpcontrol_value);
 
 extern void mips_mt_regdump(unsigned long previous_mvpcontrol_value);
 
+
 
+#ifdef CONFIG_MIPS_MT
 
 extern void mips_mt_set_cpuoptions(void);
 
 extern void mips_mt_set_cpuoptions(void);
 
+#else
 
+static inline void mips_mt_set_cpuoptions(void) { }
 
+#endif
 
 
 
 struct class;
 
 struct class;
 
 extern struct class *mt_class;
 
 extern struct class *mt_class;

+ 11 - 0
arch/mips/include/asm/mipsmtregs.h
Vizualizați fișierul 

@@ -176,6 +176,17 @@
 
 
 
 #ifndef __ASSEMBLY__
 
 #ifndef __ASSEMBLY__
 
 
 
+static inline unsigned core_nvpes(void)
 
+{
 
+	unsigned conf0;
 
+
 
+	if (!cpu_has_mipsmt)
 
+		return 1;
 
+
 
+	conf0 = read_c0_mvpconf0();
 
+	return ((conf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
 
+}
 
+
 
 static inline unsigned int dvpe(void)
 
 static inline unsigned int dvpe(void)
 
 {
 
 {
 
 	int res = 0;
 
 	int res = 0;

+ 22 - 0
arch/mips/include/asm/mipsregs.h
Vizualizați fișierul 

@@ -568,11 +568,23 @@
 
 #define MIPS_CONF1_PC		(_ULCAST_(1) <<	 4)
 
 #define MIPS_CONF1_PC		(_ULCAST_(1) <<	 4)
 
 #define MIPS_CONF1_MD		(_ULCAST_(1) <<	 5)
 
 #define MIPS_CONF1_MD		(_ULCAST_(1) <<	 5)
 
 #define MIPS_CONF1_C2		(_ULCAST_(1) <<	 6)
 
 #define MIPS_CONF1_C2		(_ULCAST_(1) <<	 6)
 
+#define MIPS_CONF1_DA_SHF	7
 
+#define MIPS_CONF1_DA_SZ	3
 
 #define MIPS_CONF1_DA		(_ULCAST_(7) <<	 7)
 
 #define MIPS_CONF1_DA		(_ULCAST_(7) <<	 7)
 
+#define MIPS_CONF1_DL_SHF	10
 
+#define MIPS_CONF1_DL_SZ	3
 
 #define MIPS_CONF1_DL		(_ULCAST_(7) << 10)
 
 #define MIPS_CONF1_DL		(_ULCAST_(7) << 10)
 
+#define MIPS_CONF1_DS_SHF	13
 
+#define MIPS_CONF1_DS_SZ	3
 
 #define MIPS_CONF1_DS		(_ULCAST_(7) << 13)
 
 #define MIPS_CONF1_DS		(_ULCAST_(7) << 13)
 
+#define MIPS_CONF1_IA_SHF	16
 
+#define MIPS_CONF1_IA_SZ	3
 
 #define MIPS_CONF1_IA		(_ULCAST_(7) << 16)
 
 #define MIPS_CONF1_IA		(_ULCAST_(7) << 16)
 
+#define MIPS_CONF1_IL_SHF	19
 
+#define MIPS_CONF1_IL_SZ	3
 
 #define MIPS_CONF1_IL		(_ULCAST_(7) << 19)
 
 #define MIPS_CONF1_IL		(_ULCAST_(7) << 19)
 
+#define MIPS_CONF1_IS_SHF	22
 
+#define MIPS_CONF1_IS_SZ	3
 
 #define MIPS_CONF1_IS		(_ULCAST_(7) << 22)
 
 #define MIPS_CONF1_IS		(_ULCAST_(7) << 22)
 
 #define MIPS_CONF1_TLBS_SHIFT   (25)
 
 #define MIPS_CONF1_TLBS_SHIFT   (25)
 
 #define MIPS_CONF1_TLBS_SIZE    (6)
 
 #define MIPS_CONF1_TLBS_SIZE    (6)
 
@@ -653,9 +665,16 @@
 
 
 
 #define MIPS_CONF7_RPS		(_ULCAST_(1) << 2)
 
 #define MIPS_CONF7_RPS		(_ULCAST_(1) << 2)
 
 
 
+#define MIPS_CONF7_IAR		(_ULCAST_(1) << 10)
 
+#define MIPS_CONF7_AR		(_ULCAST_(1) << 16)
 
+
 
 /*  EntryHI bit definition */
 
 /*  EntryHI bit definition */
 
 #define MIPS_ENTRYHI_EHINV	(_ULCAST_(1) << 10)
 
 #define MIPS_ENTRYHI_EHINV	(_ULCAST_(1) << 10)
 
 
 
+/* CMGCRBase bit definitions */
 
+#define MIPS_CMGCRB_BASE	11
 
+#define MIPS_CMGCRF_BASE	(~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
 
+
 
 /*
 
 /*
 
  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
 
  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
 
  */
 
  */
 
@@ -1010,6 +1029,8 @@ do {									\
 
 
 
 #define read_c0_prid()		__read_32bit_c0_register($15, 0)
 
 #define read_c0_prid()		__read_32bit_c0_register($15, 0)
 
 
 
+#define read_c0_cmgcrbase()	__read_ulong_c0_register($15, 3)
 
+
 
 #define read_c0_config()	__read_32bit_c0_register($16, 0)
 
 #define read_c0_config()	__read_32bit_c0_register($16, 0)
 
 #define read_c0_config1()	__read_32bit_c0_register($16, 1)
 
 #define read_c0_config1()	__read_32bit_c0_register($16, 1)
 
 #define read_c0_config2()	__read_32bit_c0_register($16, 2)
 
 #define read_c0_config2()	__read_32bit_c0_register($16, 2)
 
@@ -1883,6 +1904,7 @@ change_c0_##name(unsigned int change, unsigned int newbits)	\
 
 __BUILD_SET_C0(status)
 
 __BUILD_SET_C0(status)
 
 __BUILD_SET_C0(cause)
 
 __BUILD_SET_C0(cause)
 
 __BUILD_SET_C0(config)
 
 __BUILD_SET_C0(config)
 
+__BUILD_SET_C0(config5)
 
 __BUILD_SET_C0(intcontrol)
 
 __BUILD_SET_C0(intcontrol)
 
 __BUILD_SET_C0(intctl)
 
 __BUILD_SET_C0(intctl)
 
 __BUILD_SET_C0(srsmap)
 
 __BUILD_SET_C0(srsmap)

+ 2 - 0
arch/mips/include/asm/module.h
Vizualizați fișierul 

@@ -126,6 +126,8 @@ search_module_dbetables(unsigned long addr)
 
 #define MODULE_PROC_FAMILY "LOONGSON1 "
 
 #define MODULE_PROC_FAMILY "LOONGSON1 "
 
 #elif defined CONFIG_CPU_LOONGSON2
 
 #elif defined CONFIG_CPU_LOONGSON2
 
 #define MODULE_PROC_FAMILY "LOONGSON2 "
 
 #define MODULE_PROC_FAMILY "LOONGSON2 "
 
+#elif defined CONFIG_CPU_LOONGSON3
 
+#define MODULE_PROC_FAMILY "LOONGSON3 "
 
 #elif defined CONFIG_CPU_CAVIUM_OCTEON
 
 #elif defined CONFIG_CPU_CAVIUM_OCTEON
 
 #define MODULE_PROC_FAMILY "OCTEON "
 
 #define MODULE_PROC_FAMILY "OCTEON "
 
 #elif defined CONFIG_CPU_XLR
 
 #elif defined CONFIG_CPU_XLR

+ 203 - 0
arch/mips/include/asm/msa.h
Vizualizați fișierul 

@@ -0,0 +1,203 @@
 
+/*
 
+ * Copyright (C) 2013 Imagination Technologies
 
+ * Author: Paul Burton <paul.burton@imgtec.com>
 
+ *
 
+ * This program is free software; you can redistribute it and/or modify it
 
+ * under the terms of the GNU General Public License as published by the
 
+ * Free Software Foundation;  either version 2 of the  License, or (at your
 
+ * option) any later version.
 
+ */
 
+#ifndef _ASM_MSA_H
 
+#define _ASM_MSA_H
 
+
 
+#include <asm/mipsregs.h>
 
+
 
+extern void _save_msa(struct task_struct *);
 
+extern void _restore_msa(struct task_struct *);
 
+
 
+static inline void enable_msa(void)
 
+{
 
+	if (cpu_has_msa) {
 
+		set_c0_config5(MIPS_CONF5_MSAEN);
 
+		enable_fpu_hazard();
 
+	}
 
+}
 
+
 
+static inline void disable_msa(void)
 
+{
 
+	if (cpu_has_msa) {
 
+		clear_c0_config5(MIPS_CONF5_MSAEN);
 
+		disable_fpu_hazard();
 
+	}
 
+}
 
+
 
+static inline int is_msa_enabled(void)
 
+{
 
+	if (!cpu_has_msa)
 
+		return 0;
 
+
 
+	return read_c0_config5() & MIPS_CONF5_MSAEN;
 
+}
 
+
 
+static inline int thread_msa_context_live(void)
 
+{
 
+	/*
 
+	 * Check cpu_has_msa only if it's a constant. This will allow the
 
+	 * compiler to optimise out code for CPUs without MSA without adding
 
+	 * an extra redundant check for CPUs with MSA.
 
+	 */
 
+	if (__builtin_constant_p(cpu_has_msa) && !cpu_has_msa)
 
+		return 0;
 
+
 
+	return test_thread_flag(TIF_MSA_CTX_LIVE);
 
+}
 
+
 
+static inline void save_msa(struct task_struct *t)
 
+{
 
+	if (cpu_has_msa)
 
+		_save_msa(t);
 
+}
 
+
 
+static inline void restore_msa(struct task_struct *t)
 
+{
 
+	if (cpu_has_msa)
 
+		_restore_msa(t);
 
+}
 
+
 
+#ifdef TOOLCHAIN_SUPPORTS_MSA
 
+
 
+#define __BUILD_MSA_CTL_REG(name, cs)				\
 
+static inline unsigned int read_msa_##name(void)		\
 
+{								\
 
+	unsigned int reg;					\
 
+	__asm__ __volatile__(					\
 
+	"	.set	push\n"					\
 
+	"	.set	msa\n"					\
 
+	"	cfcmsa	%0, $" #cs "\n"				\
 
+	"	.set	pop\n"					\
 
+	: "=r"(reg));						\
 
+	return reg;						\
 
+}								\
 
+								\
 
+static inline void write_msa_##name(unsigned int val)		\
 
+{								\
 
+	__asm__ __volatile__(					\
 
+	"	.set	push\n"					\
 
+	"	.set	msa\n"					\
 
+	"	cfcmsa	$" #cs ", %0\n"				\
 
+	"	.set	pop\n"					\
 
+	: : "r"(val));						\
 
+}
 
+
 
+#else /* !TOOLCHAIN_SUPPORTS_MSA */
 
+
 
+/*
 
+ * Define functions using .word for the c[ft]cmsa instructions in order to
 
+ * allow compilation with toolchains that do not support MSA. Once all
 
+ * toolchains in use support MSA these can be removed.
 
+ */
 
+
 
+#define __BUILD_MSA_CTL_REG(name, cs)				\
 
+static inline unsigned int read_msa_##name(void)		\
 
+{								\
 
+	unsigned int reg;					\
 
+	__asm__ __volatile__(					\
 
+	"	.set	push\n"					\
 
+	"	.set	noat\n"					\
 
+	"	.word	0x787e0059 | (" #cs " << 11)\n"		\
 
+	"	move	%0, $1\n"				\
 
+	"	.set	pop\n"					\
 
+	: "=r"(reg));						\
 
+	return reg;						\
 
+}								\
 
+								\
 
+static inline void write_msa_##name(unsigned int val)		\
 
+{								\
 
+	__asm__ __volatile__(					\
 
+	"	.set	push\n"					\
 
+	"	.set	noat\n"					\
 
+	"	move	$1, %0\n"				\
 
+	"	.word	0x783e0819 | (" #cs " << 6)\n"		\
 
+	"	.set	pop\n"					\
 
+	: : "r"(val));						\
 
+}
 
+
 
+#endif /* !TOOLCHAIN_SUPPORTS_MSA */
 
+
 
+#define MSA_IR		0
 
+#define MSA_CSR		1
 
+#define MSA_ACCESS	2
 
+#define MSA_SAVE	3
 
+#define MSA_MODIFY	4
 
+#define MSA_REQUEST	5
 
+#define MSA_MAP		6
 
+#define MSA_UNMAP	7
 
+
 
+__BUILD_MSA_CTL_REG(ir, 0)
 
+__BUILD_MSA_CTL_REG(csr, 1)
 
+__BUILD_MSA_CTL_REG(access, 2)
 
+__BUILD_MSA_CTL_REG(save, 3)
 
+__BUILD_MSA_CTL_REG(modify, 4)
 
+__BUILD_MSA_CTL_REG(request, 5)
 
+__BUILD_MSA_CTL_REG(map, 6)
 
+__BUILD_MSA_CTL_REG(unmap, 7)
 
+
 
+/* MSA Implementation Register (MSAIR) */
 
+#define MSA_IR_REVB		0
 
+#define MSA_IR_REVF		(_ULCAST_(0xff) << MSA_IR_REVB)
 
+#define MSA_IR_PROCB		8
 
+#define MSA_IR_PROCF		(_ULCAST_(0xff) << MSA_IR_PROCB)
 
+#define MSA_IR_WRPB		16
 
+#define MSA_IR_WRPF		(_ULCAST_(0x1) << MSA_IR_WRPB)
 
+
 
+/* MSA Control & Status Register (MSACSR) */
 
+#define MSA_CSR_RMB		0
 
+#define MSA_CSR_RMF		(_ULCAST_(0x3) << MSA_CSR_RMB)
 
+#define MSA_CSR_RM_NEAREST	0
 
+#define MSA_CSR_RM_TO_ZERO	1
 
+#define MSA_CSR_RM_TO_POS	2
 
+#define MSA_CSR_RM_TO_NEG	3
 
+#define MSA_CSR_FLAGSB		2
 
+#define MSA_CSR_FLAGSF		(_ULCAST_(0x1f) << MSA_CSR_FLAGSB)
 
+#define MSA_CSR_FLAGS_IB	2
 
+#define MSA_CSR_FLAGS_IF	(_ULCAST_(0x1) << MSA_CSR_FLAGS_IB)
 
+#define MSA_CSR_FLAGS_UB	3
 
+#define MSA_CSR_FLAGS_UF	(_ULCAST_(0x1) << MSA_CSR_FLAGS_UB)
 
+#define MSA_CSR_FLAGS_OB	4
 
+#define MSA_CSR_FLAGS_OF	(_ULCAST_(0x1) << MSA_CSR_FLAGS_OB)
 
+#define MSA_CSR_FLAGS_ZB	5
 
+#define MSA_CSR_FLAGS_ZF	(_ULCAST_(0x1) << MSA_CSR_FLAGS_ZB)
 
+#define MSA_CSR_FLAGS_VB	6
 
+#define MSA_CSR_FLAGS_VF	(_ULCAST_(0x1) << MSA_CSR_FLAGS_VB)
 
+#define MSA_CSR_ENABLESB	7
 
+#define MSA_CSR_ENABLESF	(_ULCAST_(0x1f) << MSA_CSR_ENABLESB)
 
+#define MSA_CSR_ENABLES_IB	7
 
+#define MSA_CSR_ENABLES_IF	(_ULCAST_(0x1) << MSA_CSR_ENABLES_IB)
 
+#define MSA_CSR_ENABLES_UB	8
 
+#define MSA_CSR_ENABLES_UF	(_ULCAST_(0x1) << MSA_CSR_ENABLES_UB)
 
+#define MSA_CSR_ENABLES_OB	9
 
+#define MSA_CSR_ENABLES_OF	(_ULCAST_(0x1) << MSA_CSR_ENABLES_OB)
 
+#define MSA_CSR_ENABLES_ZB	10
 
+#define MSA_CSR_ENABLES_ZF	(_ULCAST_(0x1) << MSA_CSR_ENABLES_ZB)
 
+#define MSA_CSR_ENABLES_VB	11
 
+#define MSA_CSR_ENABLES_VF	(_ULCAST_(0x1) << MSA_CSR_ENABLES_VB)
 
+#define MSA_CSR_CAUSEB		12
 
+#define MSA_CSR_CAUSEF		(_ULCAST_(0x3f) << MSA_CSR_CAUSEB)
 
+#define MSA_CSR_CAUSE_IB	12
 
+#define MSA_CSR_CAUSE_IF	(_ULCAST_(0x1) << MSA_CSR_CAUSE_IB)
 
+#define MSA_CSR_CAUSE_UB	13
 
+#define MSA_CSR_CAUSE_UF	(_ULCAST_(0x1) << MSA_CSR_CAUSE_UB)
 
+#define MSA_CSR_CAUSE_OB	14
 
+#define MSA_CSR_CAUSE_OF	(_ULCAST_(0x1) << MSA_CSR_CAUSE_OB)
 
+#define MSA_CSR_CAUSE_ZB	15
 
+#define MSA_CSR_CAUSE_ZF	(_ULCAST_(0x1) << MSA_CSR_CAUSE_ZB)
 
+#define MSA_CSR_CAUSE_VB	16
 
+#define MSA_CSR_CAUSE_VF	(_ULCAST_(0x1) << MSA_CSR_CAUSE_VB)
 
+#define MSA_CSR_CAUSE_EB	17
 
+#define MSA_CSR_CAUSE_EF	(_ULCAST_(0x1) << MSA_CSR_CAUSE_EB)
 
+#define MSA_CSR_NXB		18
 
+#define MSA_CSR_NXF		(_ULCAST_(0x1) << MSA_CSR_NXB)
 
+#define MSA_CSR_FSB		24
 
+#define MSA_CSR_FSF		(_ULCAST_(0x1) << MSA_CSR_FSB)
 
+
 
+#endif /* _ASM_MSA_H */

+ 2 - 0
arch/mips/include/asm/page.h
Vizualizați fișierul 

@@ -190,7 +190,9 @@ typedef struct { unsigned long pgprot; } pgprot_t;
 
  * https://patchwork.linux-mips.org/patch/1541/
 
  * https://patchwork.linux-mips.org/patch/1541/
 
  */
 
  */
 
 
 
+#ifndef __pa_symbol
 
 #define __pa_symbol(x)	__pa(RELOC_HIDE((unsigned long)(x), 0))
 
 #define __pa_symbol(x)	__pa(RELOC_HIDE((unsigned long)(x), 0))
 
+#endif
 
 
 
 #define pfn_to_kaddr(pfn)	__va((pfn) << PAGE_SHIFT)
 
 #define pfn_to_kaddr(pfn)	__va((pfn) << PAGE_SHIFT)

+ 9 - 0
arch/mips/include/asm/pgtable-bits.h
Vizualizați fișierul 

@@ -235,6 +235,15 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
 
 #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
 
 #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
 
 #define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
 
 #define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
 
 
 
+#elif defined(CONFIG_CPU_LOONGSON3)
 
+
 
+/* Using COHERENT flag for NONCOHERENT doesn't hurt. */
 
+
 
+#define _CACHE_UNCACHED             (2<<_CACHE_SHIFT)  /* LOONGSON       */
 
+#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)  /* LOONGSON       */
 
+#define _CACHE_CACHABLE_COHERENT    (3<<_CACHE_SHIFT)  /* LOONGSON-3     */
 
+#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)  /* LOONGSON       */
 
+
 
 #else
 
 #else
 
 
 
 #define _CACHE_CACHABLE_NO_WA	    (0<<_CACHE_SHIFT)  /* R4600 only	  */
 
 #define _CACHE_CACHABLE_NO_WA	    (0<<_CACHE_SHIFT)  /* R4600 only	  */

+ 38 - 7
arch/mips/include/asm/processor.h
Vizualizați fișierul 

@@ -97,18 +97,48 @@ extern unsigned int vced_count, vcei_count;
 
 
 
 #define NUM_FPU_REGS	32
 
 #define NUM_FPU_REGS	32
 
 
 
-typedef __u64 fpureg_t;
 
+#ifdef CONFIG_CPU_HAS_MSA
 
+# define FPU_REG_WIDTH	128
 
+#else
 
+# define FPU_REG_WIDTH	64
 
+#endif
 
+
 
+union fpureg {
 
+	__u32	val32[FPU_REG_WIDTH / 32];
 
+	__u64	val64[FPU_REG_WIDTH / 64];
 
+};
 
+
 
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
 
+# define FPR_IDX(width, idx)	(idx)
 
+#else
 
+# define FPR_IDX(width, idx)	((FPU_REG_WIDTH / (width)) - 1 - (idx))
 
+#endif
 
+
 
+#define BUILD_FPR_ACCESS(width) \
 
+static inline u##width get_fpr##width(union fpureg *fpr, unsigned idx)	\
 
+{									\
 
+	return fpr->val##width[FPR_IDX(width, idx)];			\
 
+}									\
 
+									\
 
+static inline void set_fpr##width(union fpureg *fpr, unsigned idx,	\
 
+				  u##width val)				\
 
+{									\
 
+	fpr->val##width[FPR_IDX(width, idx)] = val;			\
 
+}
 
+
 
+BUILD_FPR_ACCESS(32)
 
+BUILD_FPR_ACCESS(64)
 
 
 
 /*
 
 /*
 
- * It would be nice to add some more fields for emulator statistics, but there
 
- * are a number of fixed offsets in offset.h and elsewhere that would have to
 
- * be recalculated by hand.  So the additional information will be private to
 
- * the FPU emulator for now.  See asm-mips/fpu_emulator.h.
 
+ * It would be nice to add some more fields for emulator statistics,
 
+ * the additional information is private to the FPU emulator for now.
 
+ * See arch/mips/include/asm/fpu_emulator.h.
 
  */
 
  */
 
 
 
 struct mips_fpu_struct {
 
 struct mips_fpu_struct {
 
-	fpureg_t	fpr[NUM_FPU_REGS];
 
+	union fpureg	fpr[NUM_FPU_REGS];
 
 	unsigned int	fcr31;
 
 	unsigned int	fcr31;
 
+	unsigned int	msacsr;
 
 };
 
 };
 
 
 
 #define NUM_DSP_REGS   6
 
 #define NUM_DSP_REGS   6
 
@@ -284,8 +314,9 @@ struct thread_struct {
 
 	 * Saved FPU/FPU emulator stuff				\
 
 	 * Saved FPU/FPU emulator stuff				\
 
 	 */							\
 
 	 */							\
 
 	.fpu			= {				\
 
 	.fpu			= {				\
 
-		.fpr		= {0,},				\
 
+		.fpr		= {{{0,},},},			\
 
 		.fcr31		= 0,				\
 
 		.fcr31		= 0,				\
 
+		.msacsr		= 0,				\
 
 	},							\
 
 	},							\
 
 	/*							\
 
 	/*							\
 
 	 * FPU affinity state (null if not FPAFF)		\
 
 	 * FPU affinity state (null if not FPAFF)		\

+ 1 - 1
arch/mips/include/asm/ptrace.h
Vizualizați fișierul 

@@ -82,7 +82,7 @@ static inline long regs_return_value(struct pt_regs *regs)
 
 #define instruction_pointer(regs) ((regs)->cp0_epc)
 
 #define instruction_pointer(regs) ((regs)->cp0_epc)
 
 #define profile_pc(regs) instruction_pointer(regs)
 
 #define profile_pc(regs) instruction_pointer(regs)
 
 
 
-extern asmlinkage void syscall_trace_enter(struct pt_regs *regs);
 
+extern asmlinkage long syscall_trace_enter(struct pt_regs *regs, long syscall);
 
 extern asmlinkage void syscall_trace_leave(struct pt_regs *regs);
 
 extern asmlinkage void syscall_trace_leave(struct pt_regs *regs);
 
 
 
 extern void die(const char *, struct pt_regs *) __noreturn;
 
 extern void die(const char *, struct pt_regs *) __noreturn;

+ 172 - 3
arch/mips/include/asm/r4kcache.h
Vizualizați fișierul 

@@ -17,6 +17,7 @@
 
 #include <asm/cpu-features.h>
 
 #include <asm/cpu-features.h>
 
 #include <asm/cpu-type.h>
 
 #include <asm/cpu-type.h>
 
 #include <asm/mipsmtregs.h>
 
 #include <asm/mipsmtregs.h>
 
+#include <asm/uaccess.h> /* for segment_eq() */
 
 
 
 /*
 
 /*
 
  * This macro return a properly sign-extended address suitable as base address
 
  * This macro return a properly sign-extended address suitable as base address
 
@@ -35,7 +36,7 @@
 
 	__asm__ __volatile__(						\
 
 	__asm__ __volatile__(						\
 
 	"	.set	push					\n"	\
 
 	"	.set	push					\n"	\
 
 	"	.set	noreorder				\n"	\
 
 	"	.set	noreorder				\n"	\
 
-	"	.set	mips3\n\t				\n"	\
 
+	"	.set	arch=r4000				\n"	\
 
 	"	cache	%0, %1					\n"	\
 
 	"	cache	%0, %1					\n"	\
 
 	"	.set	pop					\n"	\
 
 	"	.set	pop					\n"	\
 
 	:								\
 
 	:								\
 
@@ -203,7 +204,7 @@ static inline void flush_scache_line(unsigned long addr)
 
 	__asm__ __volatile__(					\
 
 	__asm__ __volatile__(					\
 
 	"	.set	push			\n"		\
 
 	"	.set	push			\n"		\
 
 	"	.set	noreorder		\n"		\
 
 	"	.set	noreorder		\n"		\
 
-	"	.set	mips3			\n"		\
 
+	"	.set	arch=r4000		\n"		\
 
 	"1:	cache	%0, (%1)		\n"		\
 
 	"1:	cache	%0, (%1)		\n"		\
 
 	"2:	.set	pop			\n"		\
 
 	"2:	.set	pop			\n"		\
 
 	"	.section __ex_table,\"a\"	\n"		\
 
 	"	.section __ex_table,\"a\"	\n"		\
 
@@ -212,6 +213,20 @@ static inline void flush_scache_line(unsigned long addr)
 
 	:							\
 
 	:							\
 
 	: "i" (op), "r" (addr))
 
 	: "i" (op), "r" (addr))
 
 
 
+#define protected_cachee_op(op,addr)				\
 
+	__asm__ __volatile__(					\
 
+	"	.set	push			\n"		\
 
+	"	.set	noreorder		\n"		\
 
+	"	.set	mips0			\n"		\
 
+	"	.set	eva			\n"		\
 
+	"1:	cachee	%0, (%1)		\n"		\
 
+	"2:	.set	pop			\n"		\
 
+	"	.section __ex_table,\"a\"	\n"		\
 
+	"	"STR(PTR)" 1b, 2b		\n"		\
 
+	"	.previous"					\
 
+	:							\
 
+	: "i" (op), "r" (addr))
 
+
 
 /*
 
 /*
 
  * The next two are for badland addresses like signal trampolines.
 
  * The next two are for badland addresses like signal trampolines.
 
  */
 
  */
 
@@ -223,7 +238,11 @@ static inline void protected_flush_icache_line(unsigned long addr)
 
 		break;
 
 		break;
 
 
 
 	default:
 
 	default:
 
+#ifdef CONFIG_EVA
 
+		protected_cachee_op(Hit_Invalidate_I, addr);
 
+#else
 
 		protected_cache_op(Hit_Invalidate_I, addr);
 
 		protected_cache_op(Hit_Invalidate_I, addr);
 
+#endif
 
 		break;
 
 		break;
 
 	}
 
 	}
 
 }
 
 }
 
@@ -356,6 +375,91 @@ static inline void invalidate_tcache_page(unsigned long addr)
 
 		: "r" (base),						\
 
 		: "r" (base),						\
 
 		  "i" (op));
 
 		  "i" (op));
 
 
 
+/*
 
+ * Perform the cache operation specified by op using a user mode virtual
 
+ * address while in kernel mode.
 
+ */
 
+#define cache16_unroll32_user(base,op)					\
 
+	__asm__ __volatile__(						\
 
+	"	.set push					\n"	\
 
+	"	.set noreorder					\n"	\
 
+	"	.set mips0					\n"	\
 
+	"	.set eva					\n"	\
 
+	"	cachee %1, 0x000(%0); cachee %1, 0x010(%0)	\n"	\
 
+	"	cachee %1, 0x020(%0); cachee %1, 0x030(%0)	\n"	\
 
+	"	cachee %1, 0x040(%0); cachee %1, 0x050(%0)	\n"	\
 
+	"	cachee %1, 0x060(%0); cachee %1, 0x070(%0)	\n"	\
 
+	"	cachee %1, 0x080(%0); cachee %1, 0x090(%0)	\n"	\
 
+	"	cachee %1, 0x0a0(%0); cachee %1, 0x0b0(%0)	\n"	\
 
+	"	cachee %1, 0x0c0(%0); cachee %1, 0x0d0(%0)	\n"	\
 
+	"	cachee %1, 0x0e0(%0); cachee %1, 0x0f0(%0)	\n"	\
 
+	"	cachee %1, 0x100(%0); cachee %1, 0x110(%0)	\n"	\
 
+	"	cachee %1, 0x120(%0); cachee %1, 0x130(%0)	\n"	\
 
+	"	cachee %1, 0x140(%0); cachee %1, 0x150(%0)	\n"	\
 
+	"	cachee %1, 0x160(%0); cachee %1, 0x170(%0)	\n"	\
 
+	"	cachee %1, 0x180(%0); cachee %1, 0x190(%0)	\n"	\
 
+	"	cachee %1, 0x1a0(%0); cachee %1, 0x1b0(%0)	\n"	\
 
+	"	cachee %1, 0x1c0(%0); cachee %1, 0x1d0(%0)	\n"	\
 
+	"	cachee %1, 0x1e0(%0); cachee %1, 0x1f0(%0)	\n"	\
 
+	"	.set pop					\n"	\
 
+		:							\
 
+		: "r" (base),						\
 
+		  "i" (op));
 
+
 
+#define cache32_unroll32_user(base, op)					\
 
+	__asm__ __volatile__(						\
 
+	"	.set push					\n"	\
 
+	"	.set noreorder					\n"	\
 
+	"	.set mips0					\n"	\
 
+	"	.set eva					\n"	\
 
+	"	cachee %1, 0x000(%0); cachee %1, 0x020(%0)	\n"	\
 
+	"	cachee %1, 0x040(%0); cachee %1, 0x060(%0)	\n"	\
 
+	"	cachee %1, 0x080(%0); cachee %1, 0x0a0(%0)	\n"	\
 
+	"	cachee %1, 0x0c0(%0); cachee %1, 0x0e0(%0)	\n"	\
 
+	"	cachee %1, 0x100(%0); cachee %1, 0x120(%0)	\n"	\
 
+	"	cachee %1, 0x140(%0); cachee %1, 0x160(%0)	\n"	\
 
+	"	cachee %1, 0x180(%0); cachee %1, 0x1a0(%0)	\n"	\
 
+	"	cachee %1, 0x1c0(%0); cachee %1, 0x1e0(%0)	\n"	\
 
+	"	cachee %1, 0x200(%0); cachee %1, 0x220(%0)	\n"	\
 
+	"	cachee %1, 0x240(%0); cachee %1, 0x260(%0)	\n"	\
 
+	"	cachee %1, 0x280(%0); cachee %1, 0x2a0(%0)	\n"	\
 
+	"	cachee %1, 0x2c0(%0); cachee %1, 0x2e0(%0)	\n"	\
 
+	"	cachee %1, 0x300(%0); cachee %1, 0x320(%0)	\n"	\
 
+	"	cachee %1, 0x340(%0); cachee %1, 0x360(%0)	\n"	\
 
+	"	cachee %1, 0x380(%0); cachee %1, 0x3a0(%0)	\n"	\
 
+	"	cachee %1, 0x3c0(%0); cachee %1, 0x3e0(%0)	\n"	\
 
+	"	.set pop					\n"	\
 
+		:							\
 
+		: "r" (base),						\
 
+		  "i" (op));
 
+
 
+#define cache64_unroll32_user(base, op)					\
 
+	__asm__ __volatile__(						\
 
+	"	.set push					\n"	\
 
+	"	.set noreorder					\n"	\
 
+	"	.set mips0					\n"	\
 
+	"	.set eva					\n"	\
 
+	"	cachee %1, 0x000(%0); cachee %1, 0x040(%0)	\n"	\
 
+	"	cachee %1, 0x080(%0); cachee %1, 0x0c0(%0)	\n"	\
 
+	"	cachee %1, 0x100(%0); cachee %1, 0x140(%0)	\n"	\
 
+	"	cachee %1, 0x180(%0); cachee %1, 0x1c0(%0)	\n"	\
 
+	"	cachee %1, 0x200(%0); cachee %1, 0x240(%0)	\n"	\
 
+	"	cachee %1, 0x280(%0); cachee %1, 0x2c0(%0)	\n"	\
 
+	"	cachee %1, 0x300(%0); cachee %1, 0x340(%0)	\n"	\
 
+	"	cachee %1, 0x380(%0); cachee %1, 0x3c0(%0)	\n"	\
 
+	"	cachee %1, 0x400(%0); cachee %1, 0x440(%0)	\n"	\
 
+	"	cachee %1, 0x480(%0); cachee %1, 0x4c0(%0)	\n"	\
 
+	"	cachee %1, 0x500(%0); cachee %1, 0x540(%0)	\n"	\
 
+	"	cachee %1, 0x580(%0); cachee %1, 0x5c0(%0)	\n"	\
 
+	"	cachee %1, 0x600(%0); cachee %1, 0x640(%0)	\n"	\
 
+	"	cachee %1, 0x680(%0); cachee %1, 0x6c0(%0)	\n"	\
 
+	"	cachee %1, 0x700(%0); cachee %1, 0x740(%0)	\n"	\
 
+	"	cachee %1, 0x780(%0); cachee %1, 0x7c0(%0)	\n"	\
 
+	"	.set pop					\n"	\
 
+		:							\
 
+		: "r" (base),						\
 
+		  "i" (op));
 
+
 
 /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
 
 /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
 
 #define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra)	\
 
 #define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra)	\
 
 static inline void extra##blast_##pfx##cache##lsize(void)		\
 
 static inline void extra##blast_##pfx##cache##lsize(void)		\
 
@@ -429,6 +533,32 @@ __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32
 
 __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
 
 __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
 
 __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
 
 __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
 
 
 
+#define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \
 
+static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \
 
+{									\
 
+	unsigned long start = page;					\
 
+	unsigned long end = page + PAGE_SIZE;				\
 
+									\
 
+	__##pfx##flush_prologue						\
 
+									\
 
+	do {								\
 
+		cache##lsize##_unroll32_user(start, hitop);             \
 
+		start += lsize * 32;					\
 
+	} while (start < end);						\
 
+									\
 
+	__##pfx##flush_epilogue						\
 
+}
 
+
 
+__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
 
+			 16)
 
+__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
 
+__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
 
+			 32)
 
+__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
 
+__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
 
+			 64)
 
+__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
 
+
 
 /* build blast_xxx_range, protected_blast_xxx_range */
 
 /* build blast_xxx_range, protected_blast_xxx_range */
 
 #define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra)	\
 
 #define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra)	\
 
 static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \
 
 static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \
 
@@ -450,12 +580,51 @@ static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start,
 
 	__##pfx##flush_epilogue						\
 
 	__##pfx##flush_epilogue						\
 
 }
 
 }
 
 
 
+#ifndef CONFIG_EVA
 
+
 
 __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
 
 __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
 
-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
 
 __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
 
 __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
 
+
 
+#else
 
+
 
+#define __BUILD_PROT_BLAST_CACHE_RANGE(pfx, desc, hitop)		\
 
+static inline void protected_blast_##pfx##cache##_range(unsigned long start,\
 
+							unsigned long end) \
 
+{									\
 
+	unsigned long lsize = cpu_##desc##_line_size();			\
 
+	unsigned long addr = start & ~(lsize - 1);			\
 
+	unsigned long aend = (end - 1) & ~(lsize - 1);			\
 
+									\
 
+	__##pfx##flush_prologue						\
 
+									\
 
+	if (segment_eq(get_fs(), USER_DS)) {				\
 
+		while (1) {						\
 
+			protected_cachee_op(hitop, addr);		\
 
+			if (addr == aend)				\
 
+				break;					\
 
+			addr += lsize;					\
 
+		}							\
 
+	} else {							\
 
+		while (1) {						\
 
+			protected_cache_op(hitop, addr);		\
 
+			if (addr == aend)				\
 
+				break;					\
 
+			addr += lsize;					\
 
+		}                                                       \
 
+									\
 
+	}								\
 
+	__##pfx##flush_epilogue						\
 
+}
 
+
 
+__BUILD_PROT_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D)
 
+__BUILD_PROT_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I)
 
+
 
+#endif
 
+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
 
 __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \
 
 __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \
 
 	protected_, loongson2_)
 
 	protected_, loongson2_)
 
 __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
 
 __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
 
+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , )
 
 __BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
 
 __BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
 
 /* blast_inv_dcache_range */
 
 /* blast_inv_dcache_range */
 
 __BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )
 
 __BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )

+ 2 - 0
arch/mips/include/asm/sigcontext.h
Vizualizați fișierul 

@@ -32,6 +32,8 @@ struct sigcontext32 {
 
 	__u32		sc_lo2;
 
 	__u32		sc_lo2;
 
 	__u32		sc_hi3;
 
 	__u32		sc_hi3;
 
 	__u32		sc_lo3;
 
 	__u32		sc_lo3;
 
+	__u64		sc_msaregs[32];	/* Most significant 64 bits */
 
+	__u32		sc_msa_csr;
 
 };
 
 };
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
 
 #endif /* _ASM_SIGCONTEXT_H */
 
 #endif /* _ASM_SIGCONTEXT_H */

+ 33 - 0
arch/mips/include/asm/smp-cps.h
Vizualizați fișierul 

@@ -0,0 +1,33 @@
 
+/*
 
+ * Copyright (C) 2013 Imagination Technologies
 
+ * Author: Paul Burton <paul.burton@imgtec.com>
 
+ *
 
+ * This program is free software; you can redistribute it and/or modify it
 
+ * under the terms of the GNU General Public License as published by the
 
+ * Free Software Foundation;  either version 2 of the  License, or (at your
 
+ * option) any later version.
 
+ */
 
+
 
+#ifndef __MIPS_ASM_SMP_CPS_H__
 
+#define __MIPS_ASM_SMP_CPS_H__
 
+
 
+#ifndef __ASSEMBLY__
 
+
 
+struct boot_config {
 
+	unsigned int core;
 
+	unsigned int vpe;
 
+	unsigned long pc;
 
+	unsigned long sp;
 
+	unsigned long gp;
 
+};
 
+
 
+extern struct boot_config mips_cps_bootcfg;
 
+
 
+extern void mips_cps_core_entry(void);
 
+
 
+#else /* __ASSEMBLY__ */
 
+
 
+.extern mips_cps_bootcfg;
 
+
 
+#endif /* __ASSEMBLY__ */
 
+#endif /* __MIPS_ASM_SMP_CPS_H__ */

+ 17 - 0
arch/mips/include/asm/smp-ops.h
Vizualizați fișierul 

@@ -13,6 +13,8 @@
 
 
 
 #include <linux/errno.h>
 
 #include <linux/errno.h>
 
 
 
+#include <asm/mips-cm.h>
 
+
 
 #ifdef CONFIG_SMP
 
 #ifdef CONFIG_SMP
 
 
 
 #include <linux/cpumask.h>
 
 #include <linux/cpumask.h>
 
@@ -43,6 +45,9 @@ static inline void plat_smp_setup(void)
 
 	mp_ops->smp_setup();
 
 	mp_ops->smp_setup();
 
 }
 
 }
 
 
 
+extern void gic_send_ipi_single(int cpu, unsigned int action);
 
+extern void gic_send_ipi_mask(const struct cpumask *mask, unsigned int action);
 
+
 
 #else /* !CONFIG_SMP */
 
 #else /* !CONFIG_SMP */
 
 
 
 struct plat_smp_ops;
 
 struct plat_smp_ops;
 
@@ -76,6 +81,9 @@ static inline int register_cmp_smp_ops(void)
 
 #ifdef CONFIG_MIPS_CMP
 
 #ifdef CONFIG_MIPS_CMP
 
 	extern struct plat_smp_ops cmp_smp_ops;
 
 	extern struct plat_smp_ops cmp_smp_ops;
 
 
 
+	if (!mips_cm_present())
 
+		return -ENODEV;
 
+
 
 	register_smp_ops(&cmp_smp_ops);
 
 	register_smp_ops(&cmp_smp_ops);
 
 
 
 	return 0;
 
 	return 0;
 
@@ -97,4 +105,13 @@ static inline int register_vsmp_smp_ops(void)
 
 #endif
 
 #endif
 
 }
 
 }
 
 
 
+#ifdef CONFIG_MIPS_CPS
 
+extern int register_cps_smp_ops(void);
 
+#else
 
+static inline int register_cps_smp_ops(void)
 
+{
 
+	return -ENODEV;
 
+}
 
+#endif
 
+
 
 #endif /* __ASM_SMP_OPS_H */
 
 #endif /* __ASM_SMP_OPS_H */

+ 1 - 0
arch/mips/include/asm/smp.h
Vizualizați fișierul 

@@ -42,6 +42,7 @@ extern int __cpu_logical_map[NR_CPUS];
 
 #define SMP_ICACHE_FLUSH	0x4
 
 #define SMP_ICACHE_FLUSH	0x4
 
 /* Used by kexec crashdump to save all cpu's state */
 
 /* Used by kexec crashdump to save all cpu's state */
 
 #define SMP_DUMP		0x8
 
 #define SMP_DUMP		0x8
 
+#define SMP_ASK_C0COUNT		0x10
 
 
 
 extern volatile cpumask_t cpu_callin_map;
 
 extern volatile cpumask_t cpu_callin_map;

+ 1 - 1
arch/mips/include/asm/stackframe.h
Vizualizați fișierul 

@@ -435,7 +435,7 @@
 
 
 
 		.macro	RESTORE_SP_AND_RET
 
 		.macro	RESTORE_SP_AND_RET
 
 		LONG_L	sp, PT_R29(sp)
 
 		LONG_L	sp, PT_R29(sp)
 
-		.set	mips3
 
+		.set	arch=r4000
 
 		eret
 
 		eret
 
 		.set	mips0
 
 		.set	mips0
 
 		.endm
 
 		.endm

+ 17 - 5
arch/mips/include/asm/switch_to.h
Vizualizați fișierul 

@@ -16,22 +16,29 @@
 
 #include <asm/watch.h>
 
 #include <asm/watch.h>
 
 #include <asm/dsp.h>
 
 #include <asm/dsp.h>
 
 #include <asm/cop2.h>
 
 #include <asm/cop2.h>
 
+#include <asm/msa.h>
 
 
 
 struct task_struct;
 
 struct task_struct;
 
 
 
+enum {
 
+	FP_SAVE_NONE	= 0,
 
+	FP_SAVE_VECTOR	= -1,
 
+	FP_SAVE_SCALAR	= 1,
 
+};
 
+
 
 /**
 
 /**
 
  * resume - resume execution of a task
 
  * resume - resume execution of a task
 
  * @prev:	The task previously executed.
 
  * @prev:	The task previously executed.
 
  * @next:	The task to begin executing.
 
  * @next:	The task to begin executing.
 
  * @next_ti:	task_thread_info(next).
 
  * @next_ti:	task_thread_info(next).
 
- * @usedfpu:	Non-zero if prev's FP context should be saved.
 
+ * @fp_save:	Which, if any, FP context to save for prev.
 
  *
 
  *
 
  * This function is used whilst scheduling to save the context of prev & load
 
  * This function is used whilst scheduling to save the context of prev & load
 
  * the context of next. Returns prev.
 
  * the context of next. Returns prev.
 
  */
 
  */
 
 extern asmlinkage struct task_struct *resume(struct task_struct *prev,
 
 extern asmlinkage struct task_struct *resume(struct task_struct *prev,
 
 		struct task_struct *next, struct thread_info *next_ti,
 
 		struct task_struct *next, struct thread_info *next_ti,
 
-		u32 usedfpu);
 
+		s32 fp_save);
 
 
 
 extern unsigned int ll_bit;
 
 extern unsigned int ll_bit;
 
 extern struct task_struct *ll_task;
 
 extern struct task_struct *ll_task;
 
@@ -75,7 +82,8 @@ do {									\
 
 
 
 #define switch_to(prev, next, last)					\
 
 #define switch_to(prev, next, last)					\
 
 do {									\
 
 do {									\
 
-	u32 __usedfpu, __c0_stat;					\
 
+	u32 __c0_stat;							\
 
+	s32 __fpsave = FP_SAVE_NONE;					\
 
 	__mips_mt_fpaff_switch_to(prev);				\
 
 	__mips_mt_fpaff_switch_to(prev);				\
 
 	if (cpu_has_dsp)						\
 
 	if (cpu_has_dsp)						\
 
 		__save_dsp(prev);					\
 
 		__save_dsp(prev);					\
 
@@ -88,8 +96,12 @@ do {									\
 
 		write_c0_status(__c0_stat & ~ST0_CU2);			\
 
 		write_c0_status(__c0_stat & ~ST0_CU2);			\
 
 	}								\
 
 	}								\
 
 	__clear_software_ll_bit();					\
 
 	__clear_software_ll_bit();					\
 
-	__usedfpu = test_and_clear_tsk_thread_flag(prev, TIF_USEDFPU);	\
 
-	(last) = resume(prev, next, task_thread_info(next), __usedfpu); \
 
+	if (test_and_clear_tsk_thread_flag(prev, TIF_USEDFPU))		\
 
+		__fpsave = FP_SAVE_SCALAR;				\
 
+	if (test_and_clear_tsk_thread_flag(prev, TIF_USEDMSA))		\
 
+		__fpsave = FP_SAVE_VECTOR;				\
 
+	(last) = resume(prev, next, task_thread_info(next), __fpsave);	\
 
+	disable_msa();							\
 
 } while (0)
 
 } while (0)
 
 
 
 #define finish_arch_switch(prev)					\
 
 #define finish_arch_switch(prev)					\

+ 29 - 3
arch/mips/include/asm/syscall.h
Vizualizați fișierul 

@@ -20,11 +20,22 @@
 
 #include <linux/sched.h>
 
 #include <linux/sched.h>
 
 #include <linux/uaccess.h>
 
 #include <linux/uaccess.h>
 
 #include <asm/ptrace.h>
 
 #include <asm/ptrace.h>
 
+#include <asm/unistd.h>
 
+
 
+#ifndef __NR_syscall /* Only defined if _MIPS_SIM == _MIPS_SIM_ABI32 */
 
+#define __NR_syscall 4000
 
+#endif
 
 
 
 static inline long syscall_get_nr(struct task_struct *task,
 
 static inline long syscall_get_nr(struct task_struct *task,
 
 				  struct pt_regs *regs)
 
 				  struct pt_regs *regs)
 
 {
 
 {
 
-	return regs->regs[2];
 
+	/* O32 ABI syscall() - Either 64-bit with O32 or 32-bit */
 
+	if ((config_enabled(CONFIG_32BIT) ||
 
+	    test_tsk_thread_flag(task, TIF_32BIT_REGS)) &&
 
+	    (regs->regs[2] == __NR_syscall))
 
+		return regs->regs[4];
 
+	else
 
+		return regs->regs[2];
 
 }
 
 }
 
 
 
 static inline unsigned long mips_get_syscall_arg(unsigned long *arg,
 
 static inline unsigned long mips_get_syscall_arg(unsigned long *arg,
 
@@ -68,6 +79,12 @@ static inline long syscall_get_return_value(struct task_struct *task,
 
 	return regs->regs[2];
 
 	return regs->regs[2];
 
 }
 
 }
 
 
 
+static inline void syscall_rollback(struct task_struct *task,
 
+				    struct pt_regs *regs)
 
+{
 
+	/* Do nothing */
 
+}
 
+
 
 static inline void syscall_set_return_value(struct task_struct *task,
 
 static inline void syscall_set_return_value(struct task_struct *task,
 
 					    struct pt_regs *regs,
 
 					    struct pt_regs *regs,
 
 					    int error, long val)
 
 					    int error, long val)
 
@@ -87,6 +104,13 @@ static inline void syscall_get_arguments(struct task_struct *task,
 
 					 unsigned long *args)
 
 					 unsigned long *args)
 
 {
 
 {
 
 	int ret;
 
 	int ret;
 
+	/* O32 ABI syscall() - Either 64-bit with O32 or 32-bit */
 
+	if ((config_enabled(CONFIG_32BIT) ||
 
+	    test_tsk_thread_flag(task, TIF_32BIT_REGS)) &&
 
+	    (regs->regs[2] == __NR_syscall)) {
 
+		i++;
 
+		n++;
 
+	}
 
 
 
 	while (n--)
 
 	while (n--)
 
 		ret |= mips_get_syscall_arg(args++, task, regs, i++);
 
 		ret |= mips_get_syscall_arg(args++, task, regs, i++);
 
@@ -103,11 +127,13 @@ extern const unsigned long sys_call_table[];
 
 extern const unsigned long sys32_call_table[];
 
 extern const unsigned long sys32_call_table[];
 
 extern const unsigned long sysn32_call_table[];
 
 extern const unsigned long sysn32_call_table[];
 
 
 
-static inline int __syscall_get_arch(void)
 
+static inline int syscall_get_arch(struct task_struct *task,
 
+				   struct pt_regs *regs)
 
 {
 
 {
 
 	int arch = EM_MIPS;
 
 	int arch = EM_MIPS;
 
 #ifdef CONFIG_64BIT
 
 #ifdef CONFIG_64BIT
 
-	arch |=  __AUDIT_ARCH_64BIT;
 
+	if (!test_tsk_thread_flag(task, TIF_32BIT_REGS))
 
+		arch |= __AUDIT_ARCH_64BIT;
 
 #endif
 
 #endif
 
 #if defined(__LITTLE_ENDIAN)
 
 #if defined(__LITTLE_ENDIAN)
 
 	arch |=  __AUDIT_ARCH_LE;
 
 	arch |=  __AUDIT_ARCH_LE;

+ 6 - 1
arch/mips/include/asm/thread_info.h
Vizualizați fișierul 

@@ -116,6 +116,8 @@ static inline struct thread_info *current_thread_info(void)
 
 #define TIF_LOAD_WATCH		25	/* If set, load watch registers */
 
 #define TIF_LOAD_WATCH		25	/* If set, load watch registers */
 
 #define TIF_SYSCALL_TRACEPOINT	26	/* syscall tracepoint instrumentation */
 
 #define TIF_SYSCALL_TRACEPOINT	26	/* syscall tracepoint instrumentation */
 
 #define TIF_32BIT_FPREGS	27	/* 32-bit floating point registers */
 
 #define TIF_32BIT_FPREGS	27	/* 32-bit floating point registers */
 
+#define TIF_USEDMSA		29	/* MSA has been used this quantum */
 
+#define TIF_MSA_CTX_LIVE	30	/* MSA context must be preserved */
 
 #define TIF_SYSCALL_TRACE	31	/* syscall trace active */
 
 #define TIF_SYSCALL_TRACE	31	/* syscall trace active */
 
 
 
 #define _TIF_SYSCALL_TRACE	(1<<TIF_SYSCALL_TRACE)
 
 #define _TIF_SYSCALL_TRACE	(1<<TIF_SYSCALL_TRACE)
 
@@ -133,10 +135,13 @@ static inline struct thread_info *current_thread_info(void)
 
 #define _TIF_FPUBOUND		(1<<TIF_FPUBOUND)
 
 #define _TIF_FPUBOUND		(1<<TIF_FPUBOUND)
 
 #define _TIF_LOAD_WATCH		(1<<TIF_LOAD_WATCH)
 
 #define _TIF_LOAD_WATCH		(1<<TIF_LOAD_WATCH)
 
 #define _TIF_32BIT_FPREGS	(1<<TIF_32BIT_FPREGS)
 
 #define _TIF_32BIT_FPREGS	(1<<TIF_32BIT_FPREGS)
 
+#define _TIF_USEDMSA		(1<<TIF_USEDMSA)
 
+#define _TIF_MSA_CTX_LIVE	(1<<TIF_MSA_CTX_LIVE)
 
 #define _TIF_SYSCALL_TRACEPOINT	(1<<TIF_SYSCALL_TRACEPOINT)
 
 #define _TIF_SYSCALL_TRACEPOINT	(1<<TIF_SYSCALL_TRACEPOINT)
 
 
 
 #define _TIF_WORK_SYSCALL_ENTRY	(_TIF_NOHZ | _TIF_SYSCALL_TRACE |	\
 
 #define _TIF_WORK_SYSCALL_ENTRY	(_TIF_NOHZ | _TIF_SYSCALL_TRACE |	\
 
-				 _TIF_SYSCALL_AUDIT | _TIF_SYSCALL_TRACEPOINT)
 
+				 _TIF_SYSCALL_AUDIT | \
 
+				 _TIF_SYSCALL_TRACEPOINT | _TIF_SECCOMP)
 
 
 
 /* work to do in syscall_trace_leave() */
 
 /* work to do in syscall_trace_leave() */
 
 #define _TIF_WORK_SYSCALL_EXIT	(_TIF_NOHZ | _TIF_SYSCALL_TRACE |	\
 
 #define _TIF_WORK_SYSCALL_EXIT	(_TIF_NOHZ | _TIF_SYSCALL_TRACE |	\

+ 432 - 127
arch/mips/include/asm/uaccess.h
Vizualizați fișierul 

@@ -6,6 +6,7 @@
 
  * Copyright (C) 1996, 1997, 1998, 1999, 2000, 03, 04 by Ralf Baechle
 
  * Copyright (C) 1996, 1997, 1998, 1999, 2000, 03, 04 by Ralf Baechle
 
  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
 
  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
 
  * Copyright (C) 2007  Maciej W. Rozycki
 
  * Copyright (C) 2007  Maciej W. Rozycki
 
+ * Copyright (C) 2014, Imagination Technologies Ltd.
 
  */
 
  */
 
 #ifndef _ASM_UACCESS_H
 
 #ifndef _ASM_UACCESS_H
 
 #define _ASM_UACCESS_H
 
 #define _ASM_UACCESS_H
 
@@ -13,6 +14,7 @@
 
 #include <linux/kernel.h>
 
 #include <linux/kernel.h>
 
 #include <linux/errno.h>
 
 #include <linux/errno.h>
 
 #include <linux/thread_info.h>
 
 #include <linux/thread_info.h>
 
+#include <asm/asm-eva.h>
 
 
 
 /*
 
 /*
 
  * The fs value determines whether argument validity checking should be
 
  * The fs value determines whether argument validity checking should be
 
@@ -222,11 +224,44 @@ struct __large_struct { unsigned long buf[100]; };
 
  * Yuck.  We need two variants, one for 64bit operation and one
 
  * Yuck.  We need two variants, one for 64bit operation and one
 
  * for 32 bit mode and old iron.
 
  * for 32 bit mode and old iron.
 
  */
 
  */
 
+#ifndef CONFIG_EVA
 
+#define __get_kernel_common(val, size, ptr) __get_user_common(val, size, ptr)
 
+#else
 
+/*
 
+ * Kernel specific functions for EVA. We need to use normal load instructions
 
+ * to read data from kernel when operating in EVA mode. We use these macros to
 
+ * avoid redefining __get_user_asm for EVA.
 
+ */
 
+#undef _loadd
 
+#undef _loadw
 
+#undef _loadh
 
+#undef _loadb
 
 #ifdef CONFIG_32BIT
 
 #ifdef CONFIG_32BIT
 
-#define __GET_USER_DW(val, ptr) __get_user_asm_ll32(val, ptr)
 
+#define _loadd			_loadw
 
+#else
 
+#define _loadd(reg, addr)	"ld " reg ", " addr
 
+#endif
 
+#define _loadw(reg, addr)	"lw " reg ", " addr
 
+#define _loadh(reg, addr)	"lh " reg ", " addr
 
+#define _loadb(reg, addr)	"lb " reg ", " addr
 
+
 
+#define __get_kernel_common(val, size, ptr)				\
 
+do {									\
 
+	switch (size) {							\
 
+	case 1: __get_data_asm(val, _loadb, ptr); break;		\
 
+	case 2: __get_data_asm(val, _loadh, ptr); break;		\
 
+	case 4: __get_data_asm(val, _loadw, ptr); break;		\
 
+	case 8: __GET_DW(val, _loadd, ptr); break;			\
 
+	default: __get_user_unknown(); break;				\
 
+	}								\
 
+} while (0)
 
+#endif
 
+
 
+#ifdef CONFIG_32BIT
 
+#define __GET_DW(val, insn, ptr) __get_data_asm_ll32(val, insn, ptr)
 
 #endif
 
 #endif
 
 #ifdef CONFIG_64BIT
 
 #ifdef CONFIG_64BIT
 
-#define __GET_USER_DW(val, ptr) __get_user_asm(val, "ld", ptr)
 
+#define __GET_DW(val, insn, ptr) __get_data_asm(val, insn, ptr)
 
 #endif
 
 #endif
 
 
 
 extern void __get_user_unknown(void);
 
 extern void __get_user_unknown(void);
 
@@ -234,10 +269,10 @@ extern void __get_user_unknown(void);
 
 #define __get_user_common(val, size, ptr)				\
 
 #define __get_user_common(val, size, ptr)				\
 
 do {									\
 
 do {									\
 
 	switch (size) {							\
 
 	switch (size) {							\
 
-	case 1: __get_user_asm(val, "lb", ptr); break;			\
 
-	case 2: __get_user_asm(val, "lh", ptr); break;			\
 
-	case 4: __get_user_asm(val, "lw", ptr); break;			\
 
-	case 8: __GET_USER_DW(val, ptr); break;				\
 
+	case 1: __get_data_asm(val, user_lb, ptr); break;		\
 
+	case 2: __get_data_asm(val, user_lh, ptr); break;		\
 
+	case 4: __get_data_asm(val, user_lw, ptr); break;		\
 
+	case 8: __GET_DW(val, user_ld, ptr); break;			\
 
 	default: __get_user_unknown(); break;				\
 
 	default: __get_user_unknown(); break;				\
 
 	}								\
 
 	}								\
 
 } while (0)
 
 } while (0)
 
@@ -246,8 +281,12 @@ do {									\
 
 ({									\
 
 ({									\
 
 	int __gu_err;							\
 
 	int __gu_err;							\
 
 									\
 
 									\
 
-	__chk_user_ptr(ptr);						\
 
-	__get_user_common((x), size, ptr);				\
 
+	if (segment_eq(get_fs(), get_ds())) {				\
 
+		__get_kernel_common((x), size, ptr);			\
 
+	} else {							\
 
+		__chk_user_ptr(ptr);					\
 
+		__get_user_common((x), size, ptr);			\
 
+	}								\
 
 	__gu_err;							\
 
 	__gu_err;							\
 
 })
 
 })
 
 
 
@@ -257,18 +296,22 @@ do {									\
 
 	const __typeof__(*(ptr)) __user * __gu_ptr = (ptr);		\
 
 	const __typeof__(*(ptr)) __user * __gu_ptr = (ptr);		\
 
 									\
 
 									\
 
 	might_fault();							\
 
 	might_fault();							\
 
-	if (likely(access_ok(VERIFY_READ,  __gu_ptr, size)))		\
 
-		__get_user_common((x), size, __gu_ptr);			\
 
+	if (likely(access_ok(VERIFY_READ,  __gu_ptr, size))) {		\
 
+		if (segment_eq(get_fs(), get_ds()))			\
 
+			__get_kernel_common((x), size, __gu_ptr);	\
 
+		else							\
 
+			__get_user_common((x), size, __gu_ptr);		\
 
+	}								\
 
 									\
 
 									\
 
 	__gu_err;							\
 
 	__gu_err;							\
 
 })
 
 })
 
 
 
-#define __get_user_asm(val, insn, addr)					\
 
+#define __get_data_asm(val, insn, addr)					\
 
 {									\
 
 {									\
 
 	long __gu_tmp;							\
 
 	long __gu_tmp;							\
 
 									\
 
 									\
 
 	__asm__ __volatile__(						\
 
 	__asm__ __volatile__(						\
 
-	"1:	" insn "	%1, %3				\n"	\
 
+	"1:	"insn("%1", "%3")"				\n"	\
 
 	"2:							\n"	\
 
 	"2:							\n"	\
 
 	"	.insn						\n"	\
 
 	"	.insn						\n"	\
 
 	"	.section .fixup,\"ax\"				\n"	\
 
 	"	.section .fixup,\"ax\"				\n"	\
 
@@ -287,7 +330,7 @@ do {									\
 
 /*
 
 /*
 
  * Get a long long 64 using 32 bit registers.
 
  * Get a long long 64 using 32 bit registers.
 
  */
 
  */
 
-#define __get_user_asm_ll32(val, addr)					\
 
+#define __get_data_asm_ll32(val, insn, addr)				\
 
 {									\
 
 {									\
 
 	union {								\
 
 	union {								\
 
 		unsigned long long	l;				\
 
 		unsigned long long	l;				\
 
@@ -295,8 +338,8 @@ do {									\
 
 	} __gu_tmp;							\
 
 	} __gu_tmp;							\
 
 									\
 
 									\
 
 	__asm__ __volatile__(						\
 
 	__asm__ __volatile__(						\
 
-	"1:	lw	%1, (%3)				\n"	\
 
-	"2:	lw	%D1, 4(%3)				\n"	\
 
+	"1:	" insn("%1", "(%3)")"				\n"	\
 
+	"2:	" insn("%D1", "4(%3)")"				\n"	\
 
 	"3:							\n"	\
 
 	"3:							\n"	\
 
 	"	.insn						\n"	\
 
 	"	.insn						\n"	\
 
 	"	.section	.fixup,\"ax\"			\n"	\
 
 	"	.section	.fixup,\"ax\"			\n"	\
 
@@ -315,30 +358,73 @@ do {									\
 
 	(val) = __gu_tmp.t;						\
 
 	(val) = __gu_tmp.t;						\
 
 }
 
 }
 
 
 
+#ifndef CONFIG_EVA
 
+#define __put_kernel_common(ptr, size) __put_user_common(ptr, size)
 
+#else
 
+/*
 
+ * Kernel specific functions for EVA. We need to use normal load instructions
 
+ * to read data from kernel when operating in EVA mode. We use these macros to
 
+ * avoid redefining __get_data_asm for EVA.
 
+ */
 
+#undef _stored
 
+#undef _storew
 
+#undef _storeh
 
+#undef _storeb
 
+#ifdef CONFIG_32BIT
 
+#define _stored			_storew
 
+#else
 
+#define _stored(reg, addr)	"ld " reg ", " addr
 
+#endif
 
+
 
+#define _storew(reg, addr)	"sw " reg ", " addr
 
+#define _storeh(reg, addr)	"sh " reg ", " addr
 
+#define _storeb(reg, addr)	"sb " reg ", " addr
 
+
 
+#define __put_kernel_common(ptr, size)					\
 
+do {									\
 
+	switch (size) {							\
 
+	case 1: __put_data_asm(_storeb, ptr); break;			\
 
+	case 2: __put_data_asm(_storeh, ptr); break;			\
 
+	case 4: __put_data_asm(_storew, ptr); break;			\
 
+	case 8: __PUT_DW(_stored, ptr); break;				\
 
+	default: __put_user_unknown(); break;				\
 
+	}								\
 
+} while(0)
 
+#endif
 
+
 
 /*
 
 /*
 
  * Yuck.  We need two variants, one for 64bit operation and one
 
  * Yuck.  We need two variants, one for 64bit operation and one
 
  * for 32 bit mode and old iron.
 
  * for 32 bit mode and old iron.
 
  */
 
  */
 
 #ifdef CONFIG_32BIT
 
 #ifdef CONFIG_32BIT
 
-#define __PUT_USER_DW(ptr) __put_user_asm_ll32(ptr)
 
+#define __PUT_DW(insn, ptr) __put_data_asm_ll32(insn, ptr)
 
 #endif
 
 #endif
 
 #ifdef CONFIG_64BIT
 
 #ifdef CONFIG_64BIT
 
-#define __PUT_USER_DW(ptr) __put_user_asm("sd", ptr)
 
+#define __PUT_DW(insn, ptr) __put_data_asm(insn, ptr)
 
 #endif
 
 #endif
 
 
 
+#define __put_user_common(ptr, size)					\
 
+do {									\
 
+	switch (size) {							\
 
+	case 1: __put_data_asm(user_sb, ptr); break;			\
 
+	case 2: __put_data_asm(user_sh, ptr); break;			\
 
+	case 4: __put_data_asm(user_sw, ptr); break;			\
 
+	case 8: __PUT_DW(user_sd, ptr); break;				\
 
+	default: __put_user_unknown(); break;				\
 
+	}								\
 
+} while (0)
 
+
 
 #define __put_user_nocheck(x, ptr, size)				\
 
 #define __put_user_nocheck(x, ptr, size)				\
 
 ({									\
 
 ({									\
 
 	__typeof__(*(ptr)) __pu_val;					\
 
 	__typeof__(*(ptr)) __pu_val;					\
 
 	int __pu_err = 0;						\
 
 	int __pu_err = 0;						\
 
 									\
 
 									\
 
-	__chk_user_ptr(ptr);						\
 
 	__pu_val = (x);							\
 
 	__pu_val = (x);							\
 
-	switch (size) {							\
 
-	case 1: __put_user_asm("sb", ptr); break;			\
 
-	case 2: __put_user_asm("sh", ptr); break;			\
 
-	case 4: __put_user_asm("sw", ptr); break;			\
 
-	case 8: __PUT_USER_DW(ptr); break;				\
 
-	default: __put_user_unknown(); break;				\
 
+	if (segment_eq(get_fs(), get_ds())) {				\
 
+		__put_kernel_common(ptr, size);				\
 
+	} else {							\
 
+		__chk_user_ptr(ptr);					\
 
+		__put_user_common(ptr, size);				\
 
 	}								\
 
 	}								\
 
 	__pu_err;							\
 
 	__pu_err;							\
 
 })
 
 })
 
@@ -351,21 +437,19 @@ do {									\
 
 									\
 
 									\
 
 	might_fault();							\
 
 	might_fault();							\
 
 	if (likely(access_ok(VERIFY_WRITE,  __pu_addr, size))) {	\
 
 	if (likely(access_ok(VERIFY_WRITE,  __pu_addr, size))) {	\
 
-		switch (size) {						\
 
-		case 1: __put_user_asm("sb", __pu_addr); break;		\
 
-		case 2: __put_user_asm("sh", __pu_addr); break;		\
 
-		case 4: __put_user_asm("sw", __pu_addr); break;		\
 
-		case 8: __PUT_USER_DW(__pu_addr); break;		\
 
-		default: __put_user_unknown(); break;			\
 
-		}							\
 
+		if (segment_eq(get_fs(), get_ds()))			\
 
+			__put_kernel_common(__pu_addr, size);		\
 
+		else							\
 
+			__put_user_common(__pu_addr, size);		\
 
 	}								\
 
 	}								\
 
+									\
 
 	__pu_err;							\
 
 	__pu_err;							\
 
 })
 
 })
 
 
 
-#define __put_user_asm(insn, ptr)					\
 
+#define __put_data_asm(insn, ptr)					\
 
 {									\
 
 {									\
 
 	__asm__ __volatile__(						\
 
 	__asm__ __volatile__(						\
 
-	"1:	" insn "	%z2, %3		# __put_user_asm\n"	\
 
+	"1:	"insn("%z2", "%3")"	# __put_data_asm	\n"	\
 
 	"2:							\n"	\
 
 	"2:							\n"	\
 
 	"	.insn						\n"	\
 
 	"	.insn						\n"	\
 
 	"	.section	.fixup,\"ax\"			\n"	\
 
 	"	.section	.fixup,\"ax\"			\n"	\
 
@@ -380,11 +464,11 @@ do {									\
 
 	  "i" (-EFAULT));						\
 
 	  "i" (-EFAULT));						\
 
 }
 
 }
 
 
 
-#define __put_user_asm_ll32(ptr)					\
 
+#define __put_data_asm_ll32(insn, ptr)					\
 
 {									\
 
 {									\
 
 	__asm__ __volatile__(						\
 
 	__asm__ __volatile__(						\
 
-	"1:	sw	%2, (%3)	# __put_user_asm_ll32	\n"	\
 
-	"2:	sw	%D2, 4(%3)				\n"	\
 
+	"1:	"insn("%2", "(%3)")"	# __put_data_asm_ll32	\n"	\
 
+	"2:	"insn("%D2", "4(%3)")"				\n"	\
 
 	"3:							\n"	\
 
 	"3:							\n"	\
 
 	"	.insn						\n"	\
 
 	"	.insn						\n"	\
 
 	"	.section	.fixup,\"ax\"			\n"	\
 
 	"	.section	.fixup,\"ax\"			\n"	\
 
@@ -402,6 +486,11 @@ do {									\
 
 
 
 extern void __put_user_unknown(void);
 
 extern void __put_user_unknown(void);
 
 
 
+/*
 
+ * ul{b,h,w} are macros and there are no equivalent macros for EVA.
 
+ * EVA unaligned access is handled in the ADE exception handler.
 
+ */
 
+#ifndef CONFIG_EVA
 
 /*
 
 /*
 
  * put_user_unaligned: - Write a simple value into user space.
 
  * put_user_unaligned: - Write a simple value into user space.
 
  * @x:	 Value to copy to user space.
 
  * @x:	 Value to copy to user space.
 
@@ -504,7 +593,7 @@ extern void __get_user_unaligned_unknown(void);
 
 #define __get_user_unaligned_common(val, size, ptr)			\
 
 #define __get_user_unaligned_common(val, size, ptr)			\
 
 do {									\
 
 do {									\
 
 	switch (size) {							\
 
 	switch (size) {							\
 
-	case 1: __get_user_asm(val, "lb", ptr); break;			\
 
+	case 1: __get_data_asm(val, "lb", ptr); break;			\
 
 	case 2: __get_user_unaligned_asm(val, "ulh", ptr); break;	\
 
 	case 2: __get_user_unaligned_asm(val, "ulh", ptr); break;	\
 
 	case 4: __get_user_unaligned_asm(val, "ulw", ptr); break;	\
 
 	case 4: __get_user_unaligned_asm(val, "ulw", ptr); break;	\
 
 	case 8: __GET_USER_UNALIGNED_DW(val, ptr); break;		\
 
 	case 8: __GET_USER_UNALIGNED_DW(val, ptr); break;		\
 
@@ -531,7 +620,7 @@ do {									\
 
 	__gu_err;							\
 
 	__gu_err;							\
 
 })
 
 })
 
 
 
-#define __get_user_unaligned_asm(val, insn, addr)			\
 
+#define __get_data_unaligned_asm(val, insn, addr)			\
 
 {									\
 
 {									\
 
 	long __gu_tmp;							\
 
 	long __gu_tmp;							\
 
 									\
 
 									\
 
@@ -594,19 +683,23 @@ do {									\
 
 #define __PUT_USER_UNALIGNED_DW(ptr) __put_user_unaligned_asm("usd", ptr)
 
 #define __PUT_USER_UNALIGNED_DW(ptr) __put_user_unaligned_asm("usd", ptr)
 
 #endif
 
 #endif
 
 
 
+#define __put_user_unaligned_common(ptr, size)				\
 
+do {									\
 
+	switch (size) {							\
 
+	case 1: __put_data_asm("sb", ptr); break;			\
 
+	case 2: __put_user_unaligned_asm("ush", ptr); break;		\
 
+	case 4: __put_user_unaligned_asm("usw", ptr); break;		\
 
+	case 8: __PUT_USER_UNALIGNED_DW(ptr); break;			\
 
+	default: __put_user_unaligned_unknown(); break;			\
 
+} while (0)
 
+
 
 #define __put_user_unaligned_nocheck(x,ptr,size)			\
 
 #define __put_user_unaligned_nocheck(x,ptr,size)			\
 
 ({									\
 
 ({									\
 
 	__typeof__(*(ptr)) __pu_val;					\
 
 	__typeof__(*(ptr)) __pu_val;					\
 
 	int __pu_err = 0;						\
 
 	int __pu_err = 0;						\
 
 									\
 
 									\
 
 	__pu_val = (x);							\
 
 	__pu_val = (x);							\
 
-	switch (size) {							\
 
-	case 1: __put_user_asm("sb", ptr); break;			\
 
-	case 2: __put_user_unaligned_asm("ush", ptr); break;		\
 
-	case 4: __put_user_unaligned_asm("usw", ptr); break;		\
 
-	case 8: __PUT_USER_UNALIGNED_DW(ptr); break;			\
 
-	default: __put_user_unaligned_unknown(); break;			\
 
-	}								\
 
+	__put_user_unaligned_common(ptr, size);				\
 
 	__pu_err;							\
 
 	__pu_err;							\
 
 })
 
 })
 
 
 
@@ -616,15 +709,9 @@ do {									\
 
 	__typeof__(*(ptr)) __pu_val = (x);				\
 
 	__typeof__(*(ptr)) __pu_val = (x);				\
 
 	int __pu_err = -EFAULT;						\
 
 	int __pu_err = -EFAULT;						\
 
 									\
 
 									\
 
-	if (likely(access_ok(VERIFY_WRITE,  __pu_addr, size))) {	\
 
-		switch (size) {						\
 
-		case 1: __put_user_asm("sb", __pu_addr); break;		\
 
-		case 2: __put_user_unaligned_asm("ush", __pu_addr); break; \
 
-		case 4: __put_user_unaligned_asm("usw", __pu_addr); break; \
 
-		case 8: __PUT_USER_UNALGINED_DW(__pu_addr); break;	\
 
-		default: __put_user_unaligned_unknown(); break;		\
 
-		}							\
 
-	}								\
 
+	if (likely(access_ok(VERIFY_WRITE,  __pu_addr, size)))		\
 
+		__put_user_unaligned_common(__pu_addr, size);		\
 
+									\
 
 	__pu_err;							\
 
 	__pu_err;							\
 
 })
 
 })
 
 
 
@@ -669,6 +756,7 @@ do {									\
 
 }
 
 }
 
 
 
 extern void __put_user_unaligned_unknown(void);
 
 extern void __put_user_unaligned_unknown(void);
 
+#endif
 
 
 
 /*
 
 /*
 
  * We're generating jump to subroutines which will be outside the range of
 
  * We're generating jump to subroutines which will be outside the range of
 
@@ -693,6 +781,7 @@ extern void __put_user_unaligned_unknown(void);
 
 
 
 extern size_t __copy_user(void *__to, const void *__from, size_t __n);
 
 extern size_t __copy_user(void *__to, const void *__from, size_t __n);
 
 
 
+#ifndef CONFIG_EVA
 
 #define __invoke_copy_to_user(to, from, n)				\
 
 #define __invoke_copy_to_user(to, from, n)				\
 
 ({									\
 
 ({									\
 
 	register void __user *__cu_to_r __asm__("$4");			\
 
 	register void __user *__cu_to_r __asm__("$4");			\
 
@@ -711,6 +800,11 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
 
 	__cu_len_r;							\
 
 	__cu_len_r;							\
 
 })
 
 })
 
 
 
+#define __invoke_copy_to_kernel(to, from, n)				\
 
+	__invoke_copy_to_user(to, from, n)
 
+
 
+#endif
 
+
 
 /*
 
 /*
 
  * __copy_to_user: - Copy a block of data into user space, with less checking.
 
  * __copy_to_user: - Copy a block of data into user space, with less checking.
 
  * @to:	  Destination address, in user space.
 
  * @to:	  Destination address, in user space.
 
@@ -735,7 +829,12 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
 
 	__cu_from = (from);						\
 
 	__cu_from = (from);						\
 
 	__cu_len = (n);							\
 
 	__cu_len = (n);							\
 
 	might_fault();							\
 
 	might_fault();							\
 
-	__cu_len = __invoke_copy_to_user(__cu_to, __cu_from, __cu_len); \
 
+	if (segment_eq(get_fs(), get_ds()))				\
 
+		__cu_len = __invoke_copy_to_kernel(__cu_to, __cu_from,	\
 
+						   __cu_len);		\
 
+	else								\
 
+		__cu_len = __invoke_copy_to_user(__cu_to, __cu_from,	\
 
+						 __cu_len);		\
 
 	__cu_len;							\
 
 	__cu_len;							\
 
 })
 
 })
 
 
 
@@ -750,7 +849,12 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
 
 	__cu_to = (to);							\
 
 	__cu_to = (to);							\
 
 	__cu_from = (from);						\
 
 	__cu_from = (from);						\
 
 	__cu_len = (n);							\
 
 	__cu_len = (n);							\
 
-	__cu_len = __invoke_copy_to_user(__cu_to, __cu_from, __cu_len); \
 
+	if (segment_eq(get_fs(), get_ds()))				\
 
+		__cu_len = __invoke_copy_to_kernel(__cu_to, __cu_from,	\
 
+						   __cu_len);		\
 
+	else								\
 
+		__cu_len = __invoke_copy_to_user(__cu_to, __cu_from,	\
 
+						 __cu_len);		\
 
 	__cu_len;							\
 
 	__cu_len;							\
 
 })
 
 })
 
 
 
@@ -763,8 +867,14 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
 
 	__cu_to = (to);							\
 
 	__cu_to = (to);							\
 
 	__cu_from = (from);						\
 
 	__cu_from = (from);						\
 
 	__cu_len = (n);							\
 
 	__cu_len = (n);							\
 
-	__cu_len = __invoke_copy_from_user_inatomic(__cu_to, __cu_from, \
 
-						    __cu_len);		\
 
+	if (segment_eq(get_fs(), get_ds()))				\
 
+		__cu_len = __invoke_copy_from_kernel_inatomic(__cu_to,	\
 
+							      __cu_from,\
 
+							      __cu_len);\
 
+	else								\
 
+		__cu_len = __invoke_copy_from_user_inatomic(__cu_to,	\
 
+							    __cu_from,	\
 
+							    __cu_len);	\
 
 	__cu_len;							\
 
 	__cu_len;							\
 
 })
 
 })
 
 
 
@@ -790,14 +900,23 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
 
 	__cu_to = (to);							\
 
 	__cu_to = (to);							\
 
 	__cu_from = (from);						\
 
 	__cu_from = (from);						\
 
 	__cu_len = (n);							\
 
 	__cu_len = (n);							\
 
-	if (access_ok(VERIFY_WRITE, __cu_to, __cu_len)) {		\
 
-		might_fault();						\
 
-		__cu_len = __invoke_copy_to_user(__cu_to, __cu_from,	\
 
-						 __cu_len);		\
 
+	if (segment_eq(get_fs(), get_ds())) {				\
 
+		__cu_len = __invoke_copy_to_kernel(__cu_to,		\
 
+						   __cu_from,		\
 
+						   __cu_len);		\
 
+	} else {							\
 
+		if (access_ok(VERIFY_WRITE, __cu_to, __cu_len)) {       \
 
+			might_fault();                                  \
 
+			__cu_len = __invoke_copy_to_user(__cu_to,	\
 
+							 __cu_from,	\
 
+							 __cu_len);     \
 
+		}							\
 
 	}								\
 
 	}								\
 
 	__cu_len;							\
 
 	__cu_len;							\
 
 })
 
 })
 
 
 
+#ifndef CONFIG_EVA
 
+
 
 #define __invoke_copy_from_user(to, from, n)				\
 
 #define __invoke_copy_from_user(to, from, n)				\
 
 ({									\
 
 ({									\
 
 	register void *__cu_to_r __asm__("$4");				\
 
 	register void *__cu_to_r __asm__("$4");				\
 
@@ -821,6 +940,17 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
 
 	__cu_len_r;							\
 
 	__cu_len_r;							\
 
 })
 
 })
 
 
 
+#define __invoke_copy_from_kernel(to, from, n)				\
 
+	__invoke_copy_from_user(to, from, n)
 
+
 
+/* For userland <-> userland operations */
 
+#define ___invoke_copy_in_user(to, from, n)				\
 
+	__invoke_copy_from_user(to, from, n)
 
+
 
+/* For kernel <-> kernel operations */
 
+#define ___invoke_copy_in_kernel(to, from, n)				\
 
+	__invoke_copy_from_user(to, from, n)
 
+
 
 #define __invoke_copy_from_user_inatomic(to, from, n)			\
 
 #define __invoke_copy_from_user_inatomic(to, from, n)			\
 
 ({									\
 
 ({									\
 
 	register void *__cu_to_r __asm__("$4");				\
 
 	register void *__cu_to_r __asm__("$4");				\
 
@@ -844,6 +974,97 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
 
 	__cu_len_r;							\
 
 	__cu_len_r;							\
 
 })
 
 })
 
 
 
+#define __invoke_copy_from_kernel_inatomic(to, from, n)			\
 
+	__invoke_copy_from_user_inatomic(to, from, n)			\
 
+
 
+#else
 
+
 
+/* EVA specific functions */
 
+
 
+extern size_t __copy_user_inatomic_eva(void *__to, const void *__from,
 
+				       size_t __n);
 
+extern size_t __copy_from_user_eva(void *__to, const void *__from,
 
+				   size_t __n);
 
+extern size_t __copy_to_user_eva(void *__to, const void *__from,
 
+				 size_t __n);
 
+extern size_t __copy_in_user_eva(void *__to, const void *__from, size_t __n);
 
+
 
+#define __invoke_copy_from_user_eva_generic(to, from, n, func_ptr)	\
 
+({									\
 
+	register void *__cu_to_r __asm__("$4");				\
 
+	register const void __user *__cu_from_r __asm__("$5");		\
 
+	register long __cu_len_r __asm__("$6");				\
 
+									\
 
+	__cu_to_r = (to);						\
 
+	__cu_from_r = (from);						\
 
+	__cu_len_r = (n);						\
 
+	__asm__ __volatile__(						\
 
+	".set\tnoreorder\n\t"						\
 
+	__MODULE_JAL(func_ptr)						\
 
+	".set\tnoat\n\t"						\
 
+	__UA_ADDU "\t$1, %1, %2\n\t"					\
 
+	".set\tat\n\t"							\
 
+	".set\treorder"							\
 
+	: "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r)	\
 
+	:								\
 
+	: "$8", "$9", "$10", "$11", "$12", "$14", "$15", "$24", "$31",	\
 
+	  DADDI_SCRATCH, "memory");					\
 
+	__cu_len_r;							\
 
+})
 
+
 
+#define __invoke_copy_to_user_eva_generic(to, from, n, func_ptr)	\
 
+({									\
 
+	register void *__cu_to_r __asm__("$4");				\
 
+	register const void __user *__cu_from_r __asm__("$5");		\
 
+	register long __cu_len_r __asm__("$6");				\
 
+									\
 
+	__cu_to_r = (to);						\
 
+	__cu_from_r = (from);						\
 
+	__cu_len_r = (n);						\
 
+	__asm__ __volatile__(						\
 
+	__MODULE_JAL(func_ptr)						\
 
+	: "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r)	\
 
+	:								\
 
+	: "$8", "$9", "$10", "$11", "$12", "$14", "$15", "$24", "$31",	\
 
+	  DADDI_SCRATCH, "memory");					\
 
+	__cu_len_r;							\
 
+})
 
+
 
+/*
 
+ * Source or destination address is in userland. We need to go through
 
+ * the TLB
 
+ */
 
+#define __invoke_copy_from_user(to, from, n)				\
 
+	__invoke_copy_from_user_eva_generic(to, from, n, __copy_from_user_eva)
 
+
 
+#define __invoke_copy_from_user_inatomic(to, from, n)			\
 
+	__invoke_copy_from_user_eva_generic(to, from, n,		\
 
+					    __copy_user_inatomic_eva)
 
+
 
+#define __invoke_copy_to_user(to, from, n)				\
 
+	__invoke_copy_to_user_eva_generic(to, from, n, __copy_to_user_eva)
 
+
 
+#define ___invoke_copy_in_user(to, from, n)				\
 
+	__invoke_copy_from_user_eva_generic(to, from, n, __copy_in_user_eva)
 
+
 
+/*
 
+ * Source or destination address in the kernel. We are not going through
 
+ * the TLB
 
+ */
 
+#define __invoke_copy_from_kernel(to, from, n)				\
 
+	__invoke_copy_from_user_eva_generic(to, from, n, __copy_user)
 
+
 
+#define __invoke_copy_from_kernel_inatomic(to, from, n)			\
 
+	__invoke_copy_from_user_eva_generic(to, from, n, __copy_user_inatomic)
 
+
 
+#define __invoke_copy_to_kernel(to, from, n)				\
 
+	__invoke_copy_to_user_eva_generic(to, from, n, __copy_user)
 
+
 
+#define ___invoke_copy_in_kernel(to, from, n)				\
 
+	__invoke_copy_from_user_eva_generic(to, from, n, __copy_user)
 
+
 
+#endif /* CONFIG_EVA */
 
+
 
 /*
 
 /*
 
  * __copy_from_user: - Copy a block of data from user space, with less checking.
 
  * __copy_from_user: - Copy a block of data from user space, with less checking.
 
  * @to:	  Destination address, in kernel space.
 
  * @to:	  Destination address, in kernel space.
 
@@ -901,10 +1122,17 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
 
 	__cu_to = (to);							\
 
 	__cu_to = (to);							\
 
 	__cu_from = (from);						\
 
 	__cu_from = (from);						\
 
 	__cu_len = (n);							\
 
 	__cu_len = (n);							\
 
-	if (access_ok(VERIFY_READ, __cu_from, __cu_len)) {		\
 
-		might_fault();						\
 
-		__cu_len = __invoke_copy_from_user(__cu_to, __cu_from,	\
 
-						   __cu_len);		\
 
+	if (segment_eq(get_fs(), get_ds())) {				\
 
+		__cu_len = __invoke_copy_from_kernel(__cu_to,		\
 
+						     __cu_from,		\
 
+						     __cu_len);		\
 
+	} else {							\
 
+		if (access_ok(VERIFY_READ, __cu_from, __cu_len)) {	\
 
+			might_fault();                                  \
 
+			__cu_len = __invoke_copy_from_user(__cu_to,	\
 
+							   __cu_from,	\
 
+							   __cu_len);   \
 
+		}							\
 
 	}								\
 
 	}								\
 
 	__cu_len;							\
 
 	__cu_len;							\
 
 })
 
 })
 
@@ -918,9 +1146,14 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
 
 	__cu_to = (to);							\
 
 	__cu_to = (to);							\
 
 	__cu_from = (from);						\
 
 	__cu_from = (from);						\
 
 	__cu_len = (n);							\
 
 	__cu_len = (n);							\
 
-	might_fault();							\
 
-	__cu_len = __invoke_copy_from_user(__cu_to, __cu_from,		\
 
-					   __cu_len);			\
 
+	if (segment_eq(get_fs(), get_ds())) {				\
 
+		__cu_len = ___invoke_copy_in_kernel(__cu_to, __cu_from,	\
 
+						    __cu_len);		\
 
+	} else {							\
 
+		might_fault();						\
 
+		__cu_len = ___invoke_copy_in_user(__cu_to, __cu_from,	\
 
+						  __cu_len);		\
 
+	}								\
 
 	__cu_len;							\
 
 	__cu_len;							\
 
 })
 
 })
 
 
 
@@ -933,11 +1166,17 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
 
 	__cu_to = (to);							\
 
 	__cu_to = (to);							\
 
 	__cu_from = (from);						\
 
 	__cu_from = (from);						\
 
 	__cu_len = (n);							\
 
 	__cu_len = (n);							\
 
-	if (likely(access_ok(VERIFY_READ, __cu_from, __cu_len) &&	\
 
-		   access_ok(VERIFY_WRITE, __cu_to, __cu_len))) {	\
 
-		might_fault();						\
 
-		__cu_len = __invoke_copy_from_user(__cu_to, __cu_from,	\
 
-						   __cu_len);		\
 
+	if (segment_eq(get_fs(), get_ds())) {				\
 
+		__cu_len = ___invoke_copy_in_kernel(__cu_to,__cu_from,	\
 
+						    __cu_len);		\
 
+	} else {							\
 
+		if (likely(access_ok(VERIFY_READ, __cu_from, __cu_len) &&\
 
+			   access_ok(VERIFY_WRITE, __cu_to, __cu_len))) {\
 
+			might_fault();					\
 
+			__cu_len = ___invoke_copy_in_user(__cu_to,	\
 
+							  __cu_from,	\
 
+							  __cu_len);	\
 
+		}							\
 
 	}								\
 
 	}								\
 
 	__cu_len;							\
 
 	__cu_len;							\
 
 })
 
 })
 
@@ -1007,16 +1246,28 @@ __strncpy_from_user(char *__to, const char __user *__from, long __len)
 
 {
 
 {
 
 	long res;
 
 	long res;
 
 
 
-	might_fault();
 
-	__asm__ __volatile__(
 
-		"move\t$4, %1\n\t"
 
-		"move\t$5, %2\n\t"
 
-		"move\t$6, %3\n\t"
 
-		__MODULE_JAL(__strncpy_from_user_nocheck_asm)
 
-		"move\t%0, $2"
 
-		: "=r" (res)
 
-		: "r" (__to), "r" (__from), "r" (__len)
 
-		: "$2", "$3", "$4", "$5", "$6", __UA_t0, "$31", "memory");
 
+	if (segment_eq(get_fs(), get_ds())) {
 
+		__asm__ __volatile__(
 
+			"move\t$4, %1\n\t"
 
+			"move\t$5, %2\n\t"
 
+			"move\t$6, %3\n\t"
 
+			__MODULE_JAL(__strncpy_from_kernel_nocheck_asm)
 
+			"move\t%0, $2"
 
+			: "=r" (res)
 
+			: "r" (__to), "r" (__from), "r" (__len)
 
+			: "$2", "$3", "$4", "$5", "$6", __UA_t0, "$31", "memory");
 
+	} else {
 
+		might_fault();
 
+		__asm__ __volatile__(
 
+			"move\t$4, %1\n\t"
 
+			"move\t$5, %2\n\t"
 
+			"move\t$6, %3\n\t"
 
+			__MODULE_JAL(__strncpy_from_user_nocheck_asm)
 
+			"move\t%0, $2"
 
+			: "=r" (res)
 
+			: "r" (__to), "r" (__from), "r" (__len)
 
+			: "$2", "$3", "$4", "$5", "$6", __UA_t0, "$31", "memory");
 
+	}
 
 
 
 	return res;
 
 	return res;
 
 }
 
 }
 
@@ -1044,16 +1295,28 @@ strncpy_from_user(char *__to, const char __user *__from, long __len)
 
 {
 
 {
 
 	long res;
 
 	long res;
 
 
 
-	might_fault();
 
-	__asm__ __volatile__(
 
-		"move\t$4, %1\n\t"
 
-		"move\t$5, %2\n\t"
 
-		"move\t$6, %3\n\t"
 
-		__MODULE_JAL(__strncpy_from_user_asm)
 
-		"move\t%0, $2"
 
-		: "=r" (res)
 
-		: "r" (__to), "r" (__from), "r" (__len)
 
-		: "$2", "$3", "$4", "$5", "$6", __UA_t0, "$31", "memory");
 
+	if (segment_eq(get_fs(), get_ds())) {
 
+		__asm__ __volatile__(
 
+			"move\t$4, %1\n\t"
 
+			"move\t$5, %2\n\t"
 
+			"move\t$6, %3\n\t"
 
+			__MODULE_JAL(__strncpy_from_kernel_asm)
 
+			"move\t%0, $2"
 
+			: "=r" (res)
 
+			: "r" (__to), "r" (__from), "r" (__len)
 
+			: "$2", "$3", "$4", "$5", "$6", __UA_t0, "$31", "memory");
 
+	} else {
 
+		might_fault();
 
+		__asm__ __volatile__(
 
+			"move\t$4, %1\n\t"
 
+			"move\t$5, %2\n\t"
 
+			"move\t$6, %3\n\t"
 
+			__MODULE_JAL(__strncpy_from_user_asm)
 
+			"move\t%0, $2"
 
+			: "=r" (res)
 
+			: "r" (__to), "r" (__from), "r" (__len)
 
+			: "$2", "$3", "$4", "$5", "$6", __UA_t0, "$31", "memory");
 
+	}
 
 
 
 	return res;
 
 	return res;
 
 }
 
 }
 
@@ -1063,14 +1326,24 @@ static inline long __strlen_user(const char __user *s)
 
 {
 
 {
 
 	long res;
 
 	long res;
 
 
 
-	might_fault();
 
-	__asm__ __volatile__(
 
-		"move\t$4, %1\n\t"
 
-		__MODULE_JAL(__strlen_user_nocheck_asm)
 
-		"move\t%0, $2"
 
-		: "=r" (res)
 
-		: "r" (s)
 
-		: "$2", "$4", __UA_t0, "$31");
 
+	if (segment_eq(get_fs(), get_ds())) {
 
+		__asm__ __volatile__(
 
+			"move\t$4, %1\n\t"
 
+			__MODULE_JAL(__strlen_kernel_nocheck_asm)
 
+			"move\t%0, $2"
 
+			: "=r" (res)
 
+			: "r" (s)
 
+			: "$2", "$4", __UA_t0, "$31");
 
+	} else {
 
+		might_fault();
 
+		__asm__ __volatile__(
 
+			"move\t$4, %1\n\t"
 
+			__MODULE_JAL(__strlen_user_nocheck_asm)
 
+			"move\t%0, $2"
 
+			: "=r" (res)
 
+			: "r" (s)
 
+			: "$2", "$4", __UA_t0, "$31");
 
+	}
 
 
 
 	return res;
 
 	return res;
 
 }
 
 }
 
@@ -1093,14 +1366,24 @@ static inline long strlen_user(const char __user *s)
 
 {
 
 {
 
 	long res;
 
 	long res;
 
 
 
-	might_fault();
 
-	__asm__ __volatile__(
 
-		"move\t$4, %1\n\t"
 
-		__MODULE_JAL(__strlen_user_asm)
 
-		"move\t%0, $2"
 
-		: "=r" (res)
 
-		: "r" (s)
 
-		: "$2", "$4", __UA_t0, "$31");
 
+	if (segment_eq(get_fs(), get_ds())) {
 
+		__asm__ __volatile__(
 
+			"move\t$4, %1\n\t"
 
+			__MODULE_JAL(__strlen_kernel_asm)
 
+			"move\t%0, $2"
 
+			: "=r" (res)
 
+			: "r" (s)
 
+			: "$2", "$4", __UA_t0, "$31");
 
+	} else {
 
+		might_fault();
 
+		__asm__ __volatile__(
 
+			"move\t$4, %1\n\t"
 
+			__MODULE_JAL(__strlen_kernel_asm)
 
+			"move\t%0, $2"
 
+			: "=r" (res)
 
+			: "r" (s)
 
+			: "$2", "$4", __UA_t0, "$31");
 
+	}
 
 
 
 	return res;
 
 	return res;
 
 }
 
 }
 
@@ -1110,15 +1393,26 @@ static inline long __strnlen_user(const char __user *s, long n)
 
 {
 
 {
 
 	long res;
 
 	long res;
 
 
 
-	might_fault();
 
-	__asm__ __volatile__(
 
-		"move\t$4, %1\n\t"
 
-		"move\t$5, %2\n\t"
 
-		__MODULE_JAL(__strnlen_user_nocheck_asm)
 
-		"move\t%0, $2"
 
-		: "=r" (res)
 
-		: "r" (s), "r" (n)
 
-		: "$2", "$4", "$5", __UA_t0, "$31");
 
+	if (segment_eq(get_fs(), get_ds())) {
 
+		__asm__ __volatile__(
 
+			"move\t$4, %1\n\t"
 
+			"move\t$5, %2\n\t"
 
+			__MODULE_JAL(__strnlen_kernel_nocheck_asm)
 
+			"move\t%0, $2"
 
+			: "=r" (res)
 
+			: "r" (s), "r" (n)
 
+			: "$2", "$4", "$5", __UA_t0, "$31");
 
+	} else {
 
+		might_fault();
 
+		__asm__ __volatile__(
 
+			"move\t$4, %1\n\t"
 
+			"move\t$5, %2\n\t"
 
+			__MODULE_JAL(__strnlen_user_nocheck_asm)
 
+			"move\t%0, $2"
 
+			: "=r" (res)
 
+			: "r" (s), "r" (n)
 
+			: "$2", "$4", "$5", __UA_t0, "$31");
 
+	}
 
 
 
 	return res;
 
 	return res;
 
 }
 
 }
 
@@ -1142,14 +1436,25 @@ static inline long strnlen_user(const char __user *s, long n)
 
 	long res;
 
 	long res;
 
 
 
 	might_fault();
 
 	might_fault();
 
-	__asm__ __volatile__(
 
-		"move\t$4, %1\n\t"
 
-		"move\t$5, %2\n\t"
 
-		__MODULE_JAL(__strnlen_user_asm)
 
-		"move\t%0, $2"
 
-		: "=r" (res)
 
-		: "r" (s), "r" (n)
 
-		: "$2", "$4", "$5", __UA_t0, "$31");
 
+	if (segment_eq(get_fs(), get_ds())) {
 
+		__asm__ __volatile__(
 
+			"move\t$4, %1\n\t"
 
+			"move\t$5, %2\n\t"
 
+			__MODULE_JAL(__strnlen_kernel_asm)
 
+			"move\t%0, $2"
 
+			: "=r" (res)
 
+			: "r" (s), "r" (n)
 
+			: "$2", "$4", "$5", __UA_t0, "$31");
 
+	} else {
 
+		__asm__ __volatile__(
 
+			"move\t$4, %1\n\t"
 
+			"move\t$5, %2\n\t"
 
+			__MODULE_JAL(__strnlen_user_asm)
 
+			"move\t%0, $2"
 
+			: "=r" (res)
 
+			: "r" (s), "r" (n)
 
+			: "$2", "$4", "$5", __UA_t0, "$31");
 
+	}
 
 
 
 	return res;
 
 	return res;
 
 }
 
 }

+ 21 - 4
arch/mips/include/uapi/asm/inst.h
Vizualizați fișierul 

@@ -8,6 +8,7 @@
 
  * Copyright (C) 1996, 2000 by Ralf Baechle
 
  * Copyright (C) 1996, 2000 by Ralf Baechle
 
  * Copyright (C) 2006 by Thiemo Seufer
 
  * Copyright (C) 2006 by Thiemo Seufer
 
  * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
 
  * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
 
+ * Copyright (C) 2014 Imagination Technologies Ltd.
 
  */
 
  */
 
 #ifndef _UAPI_ASM_INST_H
 
 #ifndef _UAPI_ASM_INST_H
 
 #define _UAPI_ASM_INST_H
 
 #define _UAPI_ASM_INST_H
 
@@ -73,10 +74,16 @@ enum spec2_op {
 
 enum spec3_op {
 
 enum spec3_op {
 
 	ext_op, dextm_op, dextu_op, dext_op,
 
 	ext_op, dextm_op, dextu_op, dext_op,
 
 	ins_op, dinsm_op, dinsu_op, dins_op,
 
 	ins_op, dinsm_op, dinsu_op, dins_op,
 
-	lx_op = 0x0a,
 
-	bshfl_op = 0x20,
 
-	dbshfl_op = 0x24,
 
-	rdhwr_op = 0x3b
 
+	lx_op     = 0x0a, lwle_op   = 0x19,
 
+	lwre_op   = 0x1a, cachee_op = 0x1b,
 
+	sbe_op    = 0x1c, she_op    = 0x1d,
 
+	sce_op    = 0x1e, swe_op    = 0x1f,
 
+	bshfl_op  = 0x20, swle_op   = 0x21,
 
+	swre_op   = 0x22, prefe_op  = 0x23,
 
+	dbshfl_op = 0x24, lbue_op   = 0x28,
 
+	lhue_op   = 0x29, lbe_op    = 0x2c,
 
+	lhe_op    = 0x2d, lle_op    = 0x2e,
 
+	lwe_op    = 0x2f, rdhwr_op  = 0x3b
 
 };
 
 };
 
 
 
 /*
 
 /*
 
@@ -592,6 +599,15 @@ struct v_format {				/* MDMX vector format */
 
 	;)))))))
 
 	;)))))))
 
 };
 
 };
 
 
 
+struct spec3_format {   /* SPEC3 */
 
+	BITFIELD_FIELD(unsigned int opcode:6,
 
+	BITFIELD_FIELD(unsigned int rs:5,
 
+	BITFIELD_FIELD(unsigned int rt:5,
 
+	BITFIELD_FIELD(signed int simmediate:9,
 
+	BITFIELD_FIELD(unsigned int func:7,
 
+	;)))))
 
+};
 
+
 
 /*
 
 /*
 
  * microMIPS instruction formats (32-bit length)
 
  * microMIPS instruction formats (32-bit length)
 
  *
 
  *
 
@@ -863,6 +879,7 @@ union mips_instruction {
 
 	struct b_format b_format;
 
 	struct b_format b_format;
 
 	struct ps_format ps_format;
 
 	struct ps_format ps_format;
 
 	struct v_format v_format;
 
 	struct v_format v_format;
 
+	struct spec3_format spec3_format;
 
 	struct fb_format fb_format;
 
 	struct fb_format fb_format;
 
 	struct fp0_format fp0_format;
 
 	struct fp0_format fp0_format;
 
 	struct mm_fp0_format mm_fp0_format;
 
 	struct mm_fp0_format mm_fp0_format;

+ 8 - 0
arch/mips/include/uapi/asm/sigcontext.h
Vizualizați fișierul 

@@ -12,6 +12,10 @@
 
 #include <linux/types.h>
 
 #include <linux/types.h>
 
 #include <asm/sgidefs.h>
 
 #include <asm/sgidefs.h>
 
 
 
+/* Bits which may be set in sc_used_math */
 
+#define USEDMATH_FP	(1 << 0)
 
+#define USEDMATH_MSA	(1 << 1)
 
+
 
 #if _MIPS_SIM == _MIPS_SIM_ABI32
 
 #if _MIPS_SIM == _MIPS_SIM_ABI32
 
 
 
 /*
 
 /*
 
@@ -37,6 +41,8 @@ struct sigcontext {
 
 	unsigned long		sc_lo2;
 
 	unsigned long		sc_lo2;
 
 	unsigned long		sc_hi3;
 
 	unsigned long		sc_hi3;
 
 	unsigned long		sc_lo3;
 
 	unsigned long		sc_lo3;
 
+	unsigned long long	sc_msaregs[32];	/* Most significant 64 bits */
 
+	unsigned long		sc_msa_csr;
 
 };
 
 };
 
 
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
 
@@ -70,6 +76,8 @@ struct sigcontext {
 
 	__u32	sc_used_math;
 
 	__u32	sc_used_math;
 
 	__u32	sc_dsp;
 
 	__u32	sc_dsp;
 
 	__u32	sc_reserved;
 
 	__u32	sc_reserved;
 
+	__u64	sc_msaregs[32];
 
+	__u32	sc_msa_csr;
 
 };
 
 };

+ 5 - 0
arch/mips/kernel/Makefile
Vizualizați fișierul 

@@ -53,6 +53,8 @@ obj-$(CONFIG_MIPS_MT_FPAFF)	+= mips-mt-fpaff.o
 
 obj-$(CONFIG_MIPS_MT_SMTC)	+= smtc.o smtc-asm.o smtc-proc.o
 
 obj-$(CONFIG_MIPS_MT_SMTC)	+= smtc.o smtc-asm.o smtc-proc.o
 
 obj-$(CONFIG_MIPS_MT_SMP)	+= smp-mt.o
 
 obj-$(CONFIG_MIPS_MT_SMP)	+= smp-mt.o
 
 obj-$(CONFIG_MIPS_CMP)		+= smp-cmp.o
 
 obj-$(CONFIG_MIPS_CMP)		+= smp-cmp.o
 
+obj-$(CONFIG_MIPS_CPS)		+= smp-cps.o cps-vec.o
 
+obj-$(CONFIG_MIPS_GIC_IPI)	+= smp-gic.o
 
 obj-$(CONFIG_CPU_MIPSR2)	+= spram.o
 
 obj-$(CONFIG_CPU_MIPSR2)	+= spram.o
 
 
 
 obj-$(CONFIG_MIPS_VPE_LOADER)	+= vpe.o
 
 obj-$(CONFIG_MIPS_VPE_LOADER)	+= vpe.o
 
@@ -102,6 +104,9 @@ obj-$(CONFIG_HW_PERF_EVENTS)	+= perf_event_mipsxx.o
 
 
 
 obj-$(CONFIG_JUMP_LABEL)	+= jump_label.o
 
 obj-$(CONFIG_JUMP_LABEL)	+= jump_label.o
 
 
 
+obj-$(CONFIG_MIPS_CM)		+= mips-cm.o
 
+obj-$(CONFIG_MIPS_CPC)		+= mips-cpc.o
 
+
 
 #
 
 #
 
 # DSP ASE supported for MIPS32 or MIPS64 Release 2 cores only. It is not
 
 # DSP ASE supported for MIPS32 or MIPS64 Release 2 cores only. It is not
 
 # safe to unconditionnaly use the assembler -mdsp / -mdspr2 switches
 
 # safe to unconditionnaly use the assembler -mdsp / -mdspr2 switches

+ 82 - 0
arch/mips/kernel/asm-offsets.c
Vizualizați fișierul 

@@ -16,6 +16,7 @@
 
 #include <linux/suspend.h>
 
 #include <linux/suspend.h>
 
 #include <asm/ptrace.h>
 
 #include <asm/ptrace.h>
 
 #include <asm/processor.h>
 
 #include <asm/processor.h>
 
+#include <asm/smp-cps.h>
 
 
 
 #include <linux/kvm_host.h>
 
 #include <linux/kvm_host.h>
 
 
 
@@ -168,6 +169,72 @@ void output_thread_fpu_defines(void)
 
 	OFFSET(THREAD_FPR30, task_struct, thread.fpu.fpr[30]);
 
 	OFFSET(THREAD_FPR30, task_struct, thread.fpu.fpr[30]);
 
 	OFFSET(THREAD_FPR31, task_struct, thread.fpu.fpr[31]);
 
 	OFFSET(THREAD_FPR31, task_struct, thread.fpu.fpr[31]);
 
 
 
+	/* the least significant 64 bits of each FP register */
 
+	OFFSET(THREAD_FPR0_LS64, task_struct,
 
+	       thread.fpu.fpr[0].val64[FPR_IDX(64, 0)]);
 
+	OFFSET(THREAD_FPR1_LS64, task_struct,
 
+	       thread.fpu.fpr[1].val64[FPR_IDX(64, 0)]);
 
+	OFFSET(THREAD_FPR2_LS64, task_struct,
 
+	       thread.fpu.fpr[2].val64[FPR_IDX(64, 0)]);
 
+	OFFSET(THREAD_FPR3_LS64, task_struct,
 
+	       thread.fpu.fpr[3].val64[FPR_IDX(64, 0)]);
 
+	OFFSET(THREAD_FPR4_LS64, task_struct,
 
+	       thread.fpu.fpr[4].val64[FPR_IDX(64, 0)]);
 
+	OFFSET(THREAD_FPR5_LS64, task_struct,
 
+	       thread.fpu.fpr[5].val64[FPR_IDX(64, 0)]);
 
+	OFFSET(THREAD_FPR6_LS64, task_struct,
 
+	       thread.fpu.fpr[6].val64[FPR_IDX(64, 0)]);
 
+	OFFSET(THREAD_FPR7_LS64, task_struct,
 
+	       thread.fpu.fpr[7].val64[FPR_IDX(64, 0)]);
 
+	OFFSET(THREAD_FPR8_LS64, task_struct,
 
+	       thread.fpu.fpr[8].val64[FPR_IDX(64, 0)]);
 
+	OFFSET(THREAD_FPR9_LS64, task_struct,
 
+	       thread.fpu.fpr[9].val64[FPR_IDX(64, 0)]);
 
+	OFFSET(THREAD_FPR10_LS64, task_struct,
 
+	       thread.fpu.fpr[10].val64[FPR_IDX(64, 0)]);
 
+	OFFSET(THREAD_FPR11_LS64, task_struct,
 
+	       thread.fpu.fpr[11].val64[FPR_IDX(64, 0)]);
 
+	OFFSET(THREAD_FPR12_LS64, task_struct,
 
+	       thread.fpu.fpr[12].val64[FPR_IDX(64, 0)]);
 
+	OFFSET(THREAD_FPR13_LS64, task_struct,
 
+	       thread.fpu.fpr[13].val64[FPR_IDX(64, 0)]);
 
+	OFFSET(THREAD_FPR14_LS64, task_struct,
 
+	       thread.fpu.fpr[14].val64[FPR_IDX(64, 0)]);
 
+	OFFSET(THREAD_FPR15_LS64, task_struct,
 
+	       thread.fpu.fpr[15].val64[FPR_IDX(64, 0)]);
 
+	OFFSET(THREAD_FPR16_LS64, task_struct,
 
+	       thread.fpu.fpr[16].val64[FPR_IDX(64, 0)]);
 
+	OFFSET(THREAD_FPR17_LS64, task_struct,
 
+	       thread.fpu.fpr[17].val64[FPR_IDX(64, 0)]);
 
+	OFFSET(THREAD_FPR18_LS64, task_struct,
 
+	       thread.fpu.fpr[18].val64[FPR_IDX(64, 0)]);
 
+	OFFSET(THREAD_FPR19_LS64, task_struct,
 
+	       thread.fpu.fpr[19].val64[FPR_IDX(64, 0)]);
 
+	OFFSET(THREAD_FPR20_LS64, task_struct,
 
+	       thread.fpu.fpr[20].val64[FPR_IDX(64, 0)]);
 
+	OFFSET(THREAD_FPR21_LS64, task_struct,
 
+	       thread.fpu.fpr[21].val64[FPR_IDX(64, 0)]);
 
+	OFFSET(THREAD_FPR22_LS64, task_struct,
 
+	       thread.fpu.fpr[22].val64[FPR_IDX(64, 0)]);
 
+	OFFSET(THREAD_FPR23_LS64, task_struct,
 
+	       thread.fpu.fpr[23].val64[FPR_IDX(64, 0)]);
 
+	OFFSET(THREAD_FPR24_LS64, task_struct,
 
+	       thread.fpu.fpr[24].val64[FPR_IDX(64, 0)]);
 
+	OFFSET(THREAD_FPR25_LS64, task_struct,
 
+	       thread.fpu.fpr[25].val64[FPR_IDX(64, 0)]);
 
+	OFFSET(THREAD_FPR26_LS64, task_struct,
 
+	       thread.fpu.fpr[26].val64[FPR_IDX(64, 0)]);
 
+	OFFSET(THREAD_FPR27_LS64, task_struct,
 
+	       thread.fpu.fpr[27].val64[FPR_IDX(64, 0)]);
 
+	OFFSET(THREAD_FPR28_LS64, task_struct,
 
+	       thread.fpu.fpr[28].val64[FPR_IDX(64, 0)]);
 
+	OFFSET(THREAD_FPR29_LS64, task_struct,
 
+	       thread.fpu.fpr[29].val64[FPR_IDX(64, 0)]);
 
+	OFFSET(THREAD_FPR30_LS64, task_struct,
 
+	       thread.fpu.fpr[30].val64[FPR_IDX(64, 0)]);
 
+	OFFSET(THREAD_FPR31_LS64, task_struct,
 
+	       thread.fpu.fpr[31].val64[FPR_IDX(64, 0)]);
 
+
 
 	OFFSET(THREAD_FCR31, task_struct, thread.fpu.fcr31);
 
 	OFFSET(THREAD_FCR31, task_struct, thread.fpu.fcr31);
 
 	BLANK();
 
 	BLANK();
 
 }
 
 }
 
@@ -228,6 +295,7 @@ void output_sc_defines(void)
 
 	OFFSET(SC_LO2, sigcontext, sc_lo2);
 
 	OFFSET(SC_LO2, sigcontext, sc_lo2);
 
 	OFFSET(SC_HI3, sigcontext, sc_hi3);
 
 	OFFSET(SC_HI3, sigcontext, sc_hi3);
 
 	OFFSET(SC_LO3, sigcontext, sc_lo3);
 
 	OFFSET(SC_LO3, sigcontext, sc_lo3);
 
+	OFFSET(SC_MSAREGS, sigcontext, sc_msaregs);
 
 	BLANK();
 
 	BLANK();
 
 }
 
 }
 
 #endif
 
 #endif
 
@@ -242,6 +310,7 @@ void output_sc_defines(void)
 
 	OFFSET(SC_MDLO, sigcontext, sc_mdlo);
 
 	OFFSET(SC_MDLO, sigcontext, sc_mdlo);
 
 	OFFSET(SC_PC, sigcontext, sc_pc);
 
 	OFFSET(SC_PC, sigcontext, sc_pc);
 
 	OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr);
 
 	OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr);
 
+	OFFSET(SC_MSAREGS, sigcontext, sc_msaregs);
 
 	BLANK();
 
 	BLANK();
 
 }
 
 }
 
 #endif
 
 #endif
 
@@ -253,6 +322,7 @@ void output_sc32_defines(void)
 
 	OFFSET(SC32_FPREGS, sigcontext32, sc_fpregs);
 
 	OFFSET(SC32_FPREGS, sigcontext32, sc_fpregs);
 
 	OFFSET(SC32_FPC_CSR, sigcontext32, sc_fpc_csr);
 
 	OFFSET(SC32_FPC_CSR, sigcontext32, sc_fpc_csr);
 
 	OFFSET(SC32_FPC_EIR, sigcontext32, sc_fpc_eir);
 
 	OFFSET(SC32_FPC_EIR, sigcontext32, sc_fpc_eir);
 
+	OFFSET(SC32_MSAREGS, sigcontext32, sc_msaregs);
 
 	BLANK();
 
 	BLANK();
 
 }
 
 }
 
 #endif
 
 #endif
 
@@ -397,3 +467,15 @@ void output_kvm_defines(void)
 
 	OFFSET(COP0_STATUS, mips_coproc, reg[MIPS_CP0_STATUS][0]);
 
 	OFFSET(COP0_STATUS, mips_coproc, reg[MIPS_CP0_STATUS][0]);
 
 	BLANK();
 
 	BLANK();
 
 }
 
 }
 
+
 
+#ifdef CONFIG_MIPS_CPS
 
+void output_cps_defines(void)
 
+{
 
+	COMMENT(" MIPS CPS offsets. ");
 
+	OFFSET(BOOTCFG_CORE, boot_config, core);
 
+	OFFSET(BOOTCFG_VPE, boot_config, vpe);
 
+	OFFSET(BOOTCFG_PC, boot_config, pc);
 
+	OFFSET(BOOTCFG_SP, boot_config, sp);
 
+	OFFSET(BOOTCFG_GP, boot_config, gp);
 
+}
 
+#endif

+ 1 - 1
arch/mips/kernel/bmips_vec.S
Vizualizați fișierul 

@@ -122,7 +122,7 @@ NESTED(bmips_reset_nmi_vec, PT_SIZE, sp)
 
 	jr	k0
 
 	jr	k0
 
 
 
 	RESTORE_ALL
 
 	RESTORE_ALL
 
-	.set	mips3
 
+	.set	arch=r4000
 
 	eret
 
 	eret
 
 
 
 /***********************************************************************
 
 /***********************************************************************

+ 191 - 0
arch/mips/kernel/cps-vec.S
Vizualizați fișierul 

@@ -0,0 +1,191 @@
 
+/*
 
+ * Copyright (C) 2013 Imagination Technologies
 
+ * Author: Paul Burton <paul.burton@imgtec.com>
 
+ *
 
+ * This program is free software; you can redistribute it and/or modify it
 
+ * under the terms of the GNU General Public License as published by the
 
+ * Free Software Foundation;  either version 2 of the  License, or (at your
 
+ * option) any later version.
 
+ */
 
+
 
+#include <asm/addrspace.h>
 
+#include <asm/asm.h>
 
+#include <asm/asm-offsets.h>
 
+#include <asm/asmmacro.h>
 
+#include <asm/cacheops.h>
 
+#include <asm/mipsregs.h>
 
+
 
+#define GCR_CL_COHERENCE_OFS 0x2008
 
+
 
+.section .text.cps-vec
 
+.balign 0x1000
 
+.set noreorder
 
+
 
+LEAF(mips_cps_core_entry)
 
+	/*
 
+	 * These first 8 bytes will be patched by cps_smp_setup to load the
 
+	 * base address of the CM GCRs into register v1.
 
+	 */
 
+	.quad	0
 
+
 
+	/* Check whether we're here due to an NMI */
 
+	mfc0	k0, CP0_STATUS
 
+	and	k0, k0, ST0_NMI
 
+	beqz	k0, not_nmi
 
+	 nop
 
+
 
+	/* This is an NMI */
 
+	la	k0, nmi_handler
 
+	jr	k0
 
+	 nop
 
+
 
+not_nmi:
 
+	/* Setup Cause */
 
+	li	t0, CAUSEF_IV
 
+	mtc0	t0, CP0_CAUSE
 
+
 
+	/* Setup Status */
 
+	li	t0, ST0_CU1 | ST0_CU0
 
+	mtc0	t0, CP0_STATUS
 
+
 
+	/*
 
+	 * Clear the bits used to index the caches. Note that the architecture
 
+	 * dictates that writing to any of TagLo or TagHi selects 0 or 2 should
 
+	 * be valid for all MIPS32 CPUs, even those for which said writes are
 
+	 * unnecessary.
 
+	 */
 
+	mtc0	zero, CP0_TAGLO, 0
 
+	mtc0	zero, CP0_TAGHI, 0
 
+	mtc0	zero, CP0_TAGLO, 2
 
+	mtc0	zero, CP0_TAGHI, 2
 
+	ehb
 
+
 
+	/* Primary cache configuration is indicated by Config1 */
 
+	mfc0	v0, CP0_CONFIG, 1
 
+
 
+	/* Detect I-cache line size */
 
+	_EXT	t0, v0, MIPS_CONF1_IL_SHF, MIPS_CONF1_IL_SZ
 
+	beqz	t0, icache_done
 
+	 li	t1, 2
 
+	sllv	t0, t1, t0
 
+
 
+	/* Detect I-cache size */
 
+	_EXT	t1, v0, MIPS_CONF1_IS_SHF, MIPS_CONF1_IS_SZ
 
+	xori	t2, t1, 0x7
 
+	beqz	t2, 1f
 
+	 li	t3, 32
 
+	addi	t1, t1, 1
 
+	sllv	t1, t3, t1
 
+1:	/* At this point t1 == I-cache sets per way */
 
+	_EXT	t2, v0, MIPS_CONF1_IA_SHF, MIPS_CONF1_IA_SZ
 
+	addi	t2, t2, 1
 
+	mul	t1, t1, t0
 
+	mul	t1, t1, t2
 
+
 
+	li	a0, KSEG0
 
+	add	a1, a0, t1
 
+1:	cache	Index_Store_Tag_I, 0(a0)
 
+	add	a0, a0, t0
 
+	bne	a0, a1, 1b
 
+	 nop
 
+icache_done:
 
+
 
+	/* Detect D-cache line size */
 
+	_EXT	t0, v0, MIPS_CONF1_DL_SHF, MIPS_CONF1_DL_SZ
 
+	beqz	t0, dcache_done
 
+	 li	t1, 2
 
+	sllv	t0, t1, t0
 
+
 
+	/* Detect D-cache size */
 
+	_EXT	t1, v0, MIPS_CONF1_DS_SHF, MIPS_CONF1_DS_SZ
 
+	xori	t2, t1, 0x7
 
+	beqz	t2, 1f
 
+	 li	t3, 32
 
+	addi	t1, t1, 1
 
+	sllv	t1, t3, t1
 
+1:	/* At this point t1 == D-cache sets per way */
 
+	_EXT	t2, v0, MIPS_CONF1_DA_SHF, MIPS_CONF1_DA_SZ
 
+	addi	t2, t2, 1
 
+	mul	t1, t1, t0
 
+	mul	t1, t1, t2
 
+
 
+	li	a0, KSEG0
 
+	addu	a1, a0, t1
 
+	subu	a1, a1, t0
 
+1:	cache	Index_Store_Tag_D, 0(a0)
 
+	bne	a0, a1, 1b
 
+	 add	a0, a0, t0
 
+dcache_done:
 
+
 
+	/* Set Kseg0 cacheable, coherent, write-back, write-allocate */
 
+	mfc0	t0, CP0_CONFIG
 
+	ori	t0, 0x7
 
+	xori	t0, 0x2
 
+	mtc0	t0, CP0_CONFIG
 
+	ehb
 
+
 
+	/* Enter the coherent domain */
 
+	li	t0, 0xff
 
+	sw	t0, GCR_CL_COHERENCE_OFS(v1)
 
+	ehb
 
+
 
+	/* Jump to kseg0 */
 
+	la	t0, 1f
 
+	jr	t0
 
+	 nop
 
+
 
+1:	/* We're up, cached & coherent */
 
+
 
+	/*
 
+	 * TODO: We should check the VPE number we intended to boot here, and
 
+	 *       if non-zero we should start that VPE and stop this one. For
 
+	 *       the moment this doesn't matter since CPUs are brought up
 
+	 *       sequentially and in order, but once hotplug is implemented
 
+	 *       this will need revisiting.
 
+	 */
 
+
 
+	/* Off we go! */
 
+	la	t0, mips_cps_bootcfg
 
+	lw	t1, BOOTCFG_PC(t0)
 
+	lw	gp, BOOTCFG_GP(t0)
 
+	lw	sp, BOOTCFG_SP(t0)
 
+	jr	t1
 
+	 nop
 
+	END(mips_cps_core_entry)
 
+
 
+.org 0x200
 
+LEAF(excep_tlbfill)
 
+	b	.
 
+	 nop
 
+	END(excep_tlbfill)
 
+
 
+.org 0x280
 
+LEAF(excep_xtlbfill)
 
+	b	.
 
+	 nop
 
+	END(excep_xtlbfill)
 
+
 
+.org 0x300
 
+LEAF(excep_cache)
 
+	b	.
 
+	 nop
 
+	END(excep_cache)
 
+
 
+.org 0x380
 
+LEAF(excep_genex)
 
+	b	.
 
+	 nop
 
+	END(excep_genex)
 
+
 
+.org 0x400
 
+LEAF(excep_intex)
 
+	b	.
 
+	 nop
 
+	END(excep_intex)
 
+
 
+.org 0x480
 
+LEAF(excep_ejtag)
 
+	la	k0, ejtag_debug_handler
 
+	jr	k0
 
+	 nop
 
+	END(excep_ejtag)

+ 62 - 12
arch/mips/kernel/cpu-probe.c
Vizualizați fișierul 

@@ -23,6 +23,8 @@
 
 #include <asm/cpu-type.h>
 
 #include <asm/cpu-type.h>
 
 #include <asm/fpu.h>
 
 #include <asm/fpu.h>
 
 #include <asm/mipsregs.h>
 
 #include <asm/mipsregs.h>
 
+#include <asm/mipsmtregs.h>
 
+#include <asm/msa.h>
 
 #include <asm/watch.h>
 
 #include <asm/watch.h>
 
 #include <asm/elf.h>
 
 #include <asm/elf.h>
 
 #include <asm/spram.h>
 
 #include <asm/spram.h>
 
@@ -126,6 +128,20 @@ static inline int __cpu_has_fpu(void)
 
 	return ((cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE);
 
 	return ((cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE);
 
 }
 
 }
 
 
 
+static inline unsigned long cpu_get_msa_id(void)
 
+{
 
+	unsigned long status, conf5, msa_id;
 
+
 
+	status = read_c0_status();
 
+	__enable_fpu(FPU_64BIT);
 
+	conf5 = read_c0_config5();
 
+	enable_msa();
 
+	msa_id = read_msa_ir();
 
+	write_c0_config5(conf5);
 
+	write_c0_status(status);
 
+	return msa_id;
 
+}
 
+
 
 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
 
 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
 
 {
 
 {
 
 #ifdef __NEED_VMBITS_PROBE
 
 #ifdef __NEED_VMBITS_PROBE
 
@@ -166,11 +182,12 @@ static char unknown_isa[] = KERN_ERR \
 
 static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
 
 static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
 
 {
 
 {
 
 	unsigned int config6;
 
 	unsigned int config6;
 
-	/*
 
-	 * Config6 is implementation dependent and it's currently only
 
-	 * used by proAptiv
 
-	 */
 
-	if (c->cputype == CPU_PROAPTIV) {
 
+
 
+	/* It's implementation dependent how the FTLB can be enabled */
 
+	switch (c->cputype) {
 
+	case CPU_PROAPTIV:
 
+	case CPU_P5600:
 
+		/* proAptiv & related cores use Config6 to enable the FTLB */
 
 		config6 = read_c0_config6();
 
 		config6 = read_c0_config6();
 
 		if (enable)
 
 		if (enable)
 
 			/* Enable FTLB */
 
 			/* Enable FTLB */
 
@@ -179,6 +196,7 @@ static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
 
 			/* Disable FTLB */
 
 			/* Disable FTLB */
 
 			write_c0_config6(config6 &  ~MIPS_CONF6_FTLBEN);
 
 			write_c0_config6(config6 &  ~MIPS_CONF6_FTLBEN);
 
 		back_to_back_c0_hazard();
 
 		back_to_back_c0_hazard();
 
+		break;
 
 	}
 
 	}
 
 }
 
 }
 
 
 
@@ -301,6 +319,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 
 		c->ases |= MIPS_ASE_VZ;
 
 		c->ases |= MIPS_ASE_VZ;
 
 	if (config3 & MIPS_CONF3_SC)
 
 	if (config3 & MIPS_CONF3_SC)
 
 		c->options |= MIPS_CPU_SEGMENTS;
 
 		c->options |= MIPS_CPU_SEGMENTS;
 
+	if (config3 & MIPS_CONF3_MSA)
 
+		c->ases |= MIPS_ASE_MSA;
 
 
 
 	return config3 & MIPS_CONF_M;
 
 	return config3 & MIPS_CONF_M;
 
 }
 
 }
 
@@ -367,6 +387,9 @@ static inline unsigned int decode_config5(struct cpuinfo_mips *c)
 
 	config5 &= ~MIPS_CONF5_UFR;
 
 	config5 &= ~MIPS_CONF5_UFR;
 
 	write_c0_config5(config5);
 
 	write_c0_config5(config5);
 
 
 
+	if (config5 & MIPS_CONF5_EVA)
 
+		c->options |= MIPS_CPU_EVA;
 
+
 
 	return config5 & MIPS_CONF_M;
 
 	return config5 & MIPS_CONF_M;
 
 }
 
 }
 
 
 
@@ -398,8 +421,13 @@ static void decode_configs(struct cpuinfo_mips *c)
 
 
 
 	mips_probe_watch_registers(c);
 
 	mips_probe_watch_registers(c);
 
 
 
-	if (cpu_has_mips_r2)
 
+#ifndef CONFIG_MIPS_CPS
 
+	if (cpu_has_mips_r2) {
 
 		c->core = read_c0_ebase() & 0x3ff;
 
 		c->core = read_c0_ebase() & 0x3ff;
 
+		if (cpu_has_mipsmt)
 
+			c->core >>= fls(core_nvpes()) - 1;
 
+	}
 
+#endif
 
 }
 
 }
 
 
 
 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
 
 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
 
@@ -710,17 +738,23 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 
 			     MIPS_CPU_LLSC;
 
 			     MIPS_CPU_LLSC;
 
 		c->tlbsize = 64;
 
 		c->tlbsize = 64;
 
 		break;
 
 		break;
 
-	case PRID_IMP_LOONGSON2:
 
-		c->cputype = CPU_LOONGSON2;
 
-		__cpu_name[cpu] = "ICT Loongson-2";
 
-
 
+	case PRID_IMP_LOONGSON_64:  /* Loongson-2/3 */
 
 		switch (c->processor_id & PRID_REV_MASK) {
 
 		switch (c->processor_id & PRID_REV_MASK) {
 
 		case PRID_REV_LOONGSON2E:
 
 		case PRID_REV_LOONGSON2E:
 
+			c->cputype = CPU_LOONGSON2;
 
+			__cpu_name[cpu] = "ICT Loongson-2";
 
 			set_elf_platform(cpu, "loongson2e");
 
 			set_elf_platform(cpu, "loongson2e");
 
 			break;
 
 			break;
 
 		case PRID_REV_LOONGSON2F:
 
 		case PRID_REV_LOONGSON2F:
 
+			c->cputype = CPU_LOONGSON2;
 
+			__cpu_name[cpu] = "ICT Loongson-2";
 
 			set_elf_platform(cpu, "loongson2f");
 
 			set_elf_platform(cpu, "loongson2f");
 
 			break;
 
 			break;
 
+		case PRID_REV_LOONGSON3A:
 
+			c->cputype = CPU_LOONGSON3;
 
+			__cpu_name[cpu] = "ICT Loongson-3";
 
+			set_elf_platform(cpu, "loongson3a");
 
+			break;
 
 		}
 
 		}
 
 
 
 		set_isa(c, MIPS_CPU_ISA_III);
 
 		set_isa(c, MIPS_CPU_ISA_III);
 
@@ -729,7 +763,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 
 			     MIPS_CPU_32FPR;
 
 			     MIPS_CPU_32FPR;
 
 		c->tlbsize = 64;
 
 		c->tlbsize = 64;
 
 		break;
 
 		break;
 
-	case PRID_IMP_LOONGSON1:
 
+	case PRID_IMP_LOONGSON_32:  /* Loongson-1 */
 
 		decode_configs(c);
 
 		decode_configs(c);
 
 
 
 		c->cputype = CPU_LOONGSON1;
 
 		c->cputype = CPU_LOONGSON1;
 
@@ -806,7 +840,7 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
 
 		__cpu_name[cpu] = "MIPS 1004Kc";
 
 		__cpu_name[cpu] = "MIPS 1004Kc";
 
 		break;
 
 		break;
 
 	case PRID_IMP_1074K:
 
 	case PRID_IMP_1074K:
 
-		c->cputype = CPU_74K;
 
+		c->cputype = CPU_1074K;
 
 		__cpu_name[cpu] = "MIPS 1074Kc";
 
 		__cpu_name[cpu] = "MIPS 1074Kc";
 
 		break;
 
 		break;
 
 	case PRID_IMP_INTERAPTIV_UP:
 
 	case PRID_IMP_INTERAPTIV_UP:
 
@@ -825,6 +859,14 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
 
 		c->cputype = CPU_PROAPTIV;
 
 		c->cputype = CPU_PROAPTIV;
 
 		__cpu_name[cpu] = "MIPS proAptiv (multi)";
 
 		__cpu_name[cpu] = "MIPS proAptiv (multi)";
 
 		break;
 
 		break;
 
+	case PRID_IMP_P5600:
 
+		c->cputype = CPU_P5600;
 
+		__cpu_name[cpu] = "MIPS P5600";
 
+		break;
 
+	case PRID_IMP_M5150:
 
+		c->cputype = CPU_M5150;
 
+		__cpu_name[cpu] = "MIPS M5150";
 
+		break;
 
 	}
 
 	}
 
 
 
 	decode_configs(c);
 
 	decode_configs(c);
 
@@ -1176,6 +1218,12 @@ void cpu_probe(void)
 
 	else
 
 	else
 
 		c->srsets = 1;
 
 		c->srsets = 1;
 
 
 
+	if (cpu_has_msa) {
 
+		c->msa_id = cpu_get_msa_id();
 
+		WARN(c->msa_id & MSA_IR_WRPF,
 
+		     "Vector register partitioning unimplemented!");
 
+	}
 
+
 
 	cpu_probe_vmbits(c);
 
 	cpu_probe_vmbits(c);
 
 
 
 #ifdef CONFIG_64BIT
 
 #ifdef CONFIG_64BIT
 
@@ -1192,4 +1240,6 @@ void cpu_report(void)
 
 		smp_processor_id(), c->processor_id, cpu_name_string());
 
 		smp_processor_id(), c->processor_id, cpu_name_string());
 
 	if (c->options & MIPS_CPU_FPU)
 
 	if (c->options & MIPS_CPU_FPU)
 
 		printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
 
 		printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
 
+	if (cpu_has_msa)
 
+		pr_info("MSA revision is: %08x\n", c->msa_id);
 
 }
 
 }

+ 4 - 0
arch/mips/kernel/ftrace.c
Vizualizați fișierul 

@@ -90,6 +90,7 @@ static inline void ftrace_dyn_arch_init_insns(void)
 
 static int ftrace_modify_code(unsigned long ip, unsigned int new_code)
 
 static int ftrace_modify_code(unsigned long ip, unsigned int new_code)
 
 {
 
 {
 
 	int faulted;
 
 	int faulted;
 
+	mm_segment_t old_fs;
 
 
 
 	/* *(unsigned int *)ip = new_code; */
 
 	/* *(unsigned int *)ip = new_code; */
 
 	safe_store_code(new_code, ip, faulted);
 
 	safe_store_code(new_code, ip, faulted);
 
@@ -97,7 +98,10 @@ static int ftrace_modify_code(unsigned long ip, unsigned int new_code)
 
 	if (unlikely(faulted))
 
 	if (unlikely(faulted))
 
 		return -EFAULT;
 
 		return -EFAULT;
 
 
 
+	old_fs = get_fs();
 
+	set_fs(get_ds());
 
 	flush_icache_range(ip, ip + 8);
 
 	flush_icache_range(ip, ip + 8);
 
+	set_fs(old_fs);
 
 
 
 	return 0;
 
 	return 0;
 
 }
 
 }

Unele fișiere nu au fost afișate deoarece prea multe fișiere au fost modificate în acest diff