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@@ -760,6 +760,13 @@ static int vcn_v1_0_start(struct amdgpu_device *adev)
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WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0);
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WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
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+ /* initialize wptr */
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+ ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
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+
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+ /* copy patch commands to the jpeg ring */
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+ vcn_v1_0_jpeg_ring_set_patch_ring(ring,
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+ (ring->wptr + ring->max_dw * amdgpu_sched_hw_submission));
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+
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return 0;
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}
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