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@@ -195,16 +195,16 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
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INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
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INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
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ar9485_1_1_baseband_core_txfir_coeff_japan_2484);
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ar9485_1_1_baseband_core_txfir_coeff_japan_2484);
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- if (ah->config.no_pll_pwrsave) {
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+ if (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) {
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INIT_INI_ARRAY(&ah->iniPcieSerdes,
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INIT_INI_ARRAY(&ah->iniPcieSerdes,
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- ar9485_1_1_pcie_phy_clkreq_disable_L1);
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+ ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
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INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
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INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
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- ar9485_1_1_pcie_phy_clkreq_disable_L1);
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+ ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
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} else {
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} else {
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INIT_INI_ARRAY(&ah->iniPcieSerdes,
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INIT_INI_ARRAY(&ah->iniPcieSerdes,
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- ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
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+ ar9485_1_1_pcie_phy_clkreq_disable_L1);
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INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
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INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
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- ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
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+ ar9485_1_1_pcie_phy_clkreq_disable_L1);
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}
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}
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} else if (AR_SREV_9462_21(ah)) {
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} else if (AR_SREV_9462_21(ah)) {
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
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