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@@ -368,6 +368,7 @@ enum cpu_type_enum {
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#define MIPS_CPU_HTW 0x100000000ull /* CPU support Hardware Page Table Walker */
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#define MIPS_CPU_HTW 0x100000000ull /* CPU support Hardware Page Table Walker */
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#define MIPS_CPU_RIXIEX 0x200000000ull /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
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#define MIPS_CPU_RIXIEX 0x200000000ull /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
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#define MIPS_CPU_MAAR 0x400000000ull /* MAAR(I) registers are present */
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#define MIPS_CPU_MAAR 0x400000000ull /* MAAR(I) registers are present */
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+#define MIPS_CPU_FRE 0x800000000ull /* FRE & UFE bits implemented */
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/*
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/*
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* CPU ASE encodings
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* CPU ASE encodings
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