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@@ -3822,7 +3822,7 @@ static int nand_get_bits_per_cell(u8 cellinfo)
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void nand_decode_ext_id(struct nand_chip *chip)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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- int extid, id_len = chip->id.len;
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+ int extid;
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u8 *id_data = chip->id.data;
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/* The 3rd id byte holds MLC / multichip data */
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chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
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@@ -3841,20 +3841,6 @@ void nand_decode_ext_id(struct nand_chip *chip)
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/* Get buswidth information */
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if (extid & 0x1)
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chip->options |= NAND_BUSWIDTH_16;
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-
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- /*
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- * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
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- * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
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- * follows:
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- * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
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- * 110b -> 24nm
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- * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
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- */
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- if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
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- nand_is_slc(chip) &&
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- (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
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- !(id_data[4] & 0x80) /* !BENAND */)
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- mtd->oobsize = 32 * mtd->writesize >> 9;
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}
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EXPORT_SYMBOL_GPL(nand_decode_ext_id);
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@@ -3914,8 +3900,7 @@ static void nand_decode_bbm_options(struct nand_chip *chip)
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* AMD/Spansion, and Macronix. All others scan only the first page.
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*/
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if ((nand_is_slc(chip) &&
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- (maf_id == NAND_MFR_TOSHIBA || maf_id == NAND_MFR_AMD ||
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- maf_id == NAND_MFR_MACRONIX)) ||
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+ (maf_id == NAND_MFR_AMD || maf_id == NAND_MFR_MACRONIX)) ||
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(mtd->writesize == 2048 && maf_id == NAND_MFR_MICRON))
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chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
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}
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